[linux-block.git] / drivers / pwm / pwm-mtk-disp.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * MediaTek display pulse-width-modulation controller driver.
 * Copyright (c) 2015 MediaTek Inc.
 * Author: YH Huang <yh.huang@mediatek.com>
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

#define DISP_PWM_EN		0x00

#define PWM_CLKDIV_SHIFT	16
#define PWM_CLKDIV_MAX		0x3ff
#define PWM_CLKDIV_MASK		(PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)

#define PWM_PERIOD_BIT_WIDTH	12
#define PWM_PERIOD_MASK		((1 << PWM_PERIOD_BIT_WIDTH) - 1)

#define PWM_HIGH_WIDTH_SHIFT	16
#define PWM_HIGH_WIDTH_MASK	(0x1fff << PWM_HIGH_WIDTH_SHIFT)

struct mtk_pwm_data {
	u32 enable_mask;
	unsigned int con0;
	u32 con0_sel;
	unsigned int con1;

	bool has_commit;
	unsigned int commit;
	unsigned int commit_mask;

	unsigned int bls_debug;
	u32 bls_debug_mask;
};

struct mtk_disp_pwm {
	struct pwm_chip chip;
	const struct mtk_pwm_data *data;
	struct clk *clk_main;
	struct clk *clk_mm;
	void __iomem *base;
	bool enabled;
};

static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct mtk_disp_pwm, chip);
}

static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
				     u32 mask, u32 data)
{
	void __iomem *address = mdp->base + offset;
	u32 value;

	value = readl(address);
	value &= ~mask;
	value |= data;
	writel(value, address);
}

static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      const struct pwm_state *state)
{
	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	u32 clk_div, period, high_width, value;
	u64 div, rate;
	int err;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
					 0x0);

		if (mdp->enabled) {
			clk_disable_unprepare(mdp->clk_mm);
			clk_disable_unprepare(mdp->clk_main);
		}

		mdp->enabled = false;
		return 0;
	}

	if (!mdp->enabled) {
		err = clk_prepare_enable(mdp->clk_main);
		if (err < 0) {
			dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
				ERR_PTR(err));
			return err;
		}

		err = clk_prepare_enable(mdp->clk_mm);
		if (err < 0) {
			dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
				ERR_PTR(err));
			clk_disable_unprepare(mdp->clk_main);
			return err;
		}
	}

	/*
	 * Find period, high_width and clk_div to suit duty_ns and period_ns.
	 * Calculate proper div value to keep period value in the bound.
	 *
	 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
	 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
	 *
	 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
	 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
	 */
	rate = clk_get_rate(mdp->clk_main);
	clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
			  PWM_PERIOD_BIT_WIDTH;
	if (clk_div > PWM_CLKDIV_MAX) {
		if (!mdp->enabled) {
			clk_disable_unprepare(mdp->clk_mm);
			clk_disable_unprepare(mdp->clk_main);
		}
		return -EINVAL;
	}

	div = NSEC_PER_SEC * (clk_div + 1);
	period = mul_u64_u64_div_u64(state->period, rate, div);
	if (period > 0)
		period--;

	high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
	value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);

	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
				 PWM_CLKDIV_MASK,
				 clk_div << PWM_CLKDIV_SHIFT);
	mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
				 PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
				 value);

	if (mdp->data->has_commit) {
		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
					 mdp->data->commit_mask,
					 mdp->data->commit_mask);
		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
					 mdp->data->commit_mask,
					 0x0);
	} else {
		/*
		 * For MT2701, disable double buffer before writing register
		 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
		 */
		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
					 mdp->data->bls_debug_mask,
					 mdp->data->bls_debug_mask);
		mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
					 mdp->data->con0_sel,
					 mdp->data->con0_sel);
	}

	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
				 mdp->data->enable_mask);
	mdp->enabled = true;

	return 0;
}

static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
				   struct pwm_device *pwm,
				   struct pwm_state *state)
{
	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	u64 rate, period, high_width;
	u32 clk_div, pwm_en, con0, con1;
	int err;

	err = clk_prepare_enable(mdp->clk_main);
	if (err < 0) {
		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
		return;
	}

	err = clk_prepare_enable(mdp->clk_mm);
	if (err < 0) {
		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
		clk_disable_unprepare(mdp->clk_main);
		return;
	}

	rate = clk_get_rate(mdp->clk_main);
	con0 = readl(mdp->base + mdp->data->con0);
	con1 = readl(mdp->base + mdp->data->con1);
	pwm_en = readl(mdp->base + DISP_PWM_EN);
	state->enabled = !!(pwm_en & mdp->data->enable_mask);
	clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
	period = FIELD_GET(PWM_PERIOD_MASK, con1);
	/*
	 * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
	 * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
	 */
	state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
	high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
	state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
					       rate);
	state->polarity = PWM_POLARITY_NORMAL;
	clk_disable_unprepare(mdp->clk_mm);
	clk_disable_unprepare(mdp->clk_main);
}

static const struct pwm_ops mtk_disp_pwm_ops = {
	.apply = mtk_disp_pwm_apply,
	.get_state = mtk_disp_pwm_get_state,
	.owner = THIS_MODULE,
};

static int mtk_disp_pwm_probe(struct platform_device *pdev)
{
	struct mtk_disp_pwm *mdp;
	int ret;

	mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
	if (!mdp)
		return -ENOMEM;

	mdp->data = of_device_get_match_data(&pdev->dev);

	mdp->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mdp->base))
		return PTR_ERR(mdp->base);

	mdp->clk_main = devm_clk_get(&pdev->dev, "main");
	if (IS_ERR(mdp->clk_main))
		return PTR_ERR(mdp->clk_main);

	mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
	if (IS_ERR(mdp->clk_mm))
		return PTR_ERR(mdp->clk_mm);

	mdp->chip.dev = &pdev->dev;
	mdp->chip.ops = &mtk_disp_pwm_ops;
	mdp->chip.npwm = 1;

	ret = pwmchip_add(&mdp->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
		return ret;
	}

	platform_set_drvdata(pdev, mdp);

	return 0;
}

static int mtk_disp_pwm_remove(struct platform_device *pdev)
{
	struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);

	pwmchip_remove(&mdp->chip);

	return 0;
}

static const struct mtk_pwm_data mt2701_pwm_data = {
	.enable_mask = BIT(16),
	.con0 = 0xa8,
	.con0_sel = 0x2,
	.con1 = 0xac,
	.has_commit = false,
	.bls_debug = 0xb0,
	.bls_debug_mask = 0x3,
};

static const struct mtk_pwm_data mt8173_pwm_data = {
	.enable_mask = BIT(0),
	.con0 = 0x10,
	.con0_sel = 0x0,
	.con1 = 0x14,
	.has_commit = true,
	.commit = 0x8,
	.commit_mask = 0x1,
};

static const struct mtk_pwm_data mt8183_pwm_data = {
	.enable_mask = BIT(0),
	.con0 = 0x18,
	.con0_sel = 0x0,
	.con1 = 0x1c,
	.has_commit = false,
	.bls_debug = 0x80,
	.bls_debug_mask = 0x3,
};

static const struct of_device_id mtk_disp_pwm_of_match[] = {
	{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
	{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
	{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
	{ .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
	{ }
};
MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);

static struct platform_driver mtk_disp_pwm_driver = {
	.driver = {
		.name = "mediatek-disp-pwm",
		.of_match_table = mtk_disp_pwm_of_match,
	},
	.probe = mtk_disp_pwm_probe,
	.remove = mtk_disp_pwm_remove,
};
module_platform_driver(mtk_disp_pwm_driver);

MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
7e3b7dc7 YH	2	/*
	3	* MediaTek display pulse-width-modulation controller driver.
	4	* Copyright (c) 2015 MediaTek Inc.
	5	* Author: YH Huang <yh.huang@mediatek.com>
7e3b7dc7 YH	6	*/
7e3b7dc7 YH	7
3f2b1673	8	#include <linux/bitfield.h>
7e3b7dc7 YH	9	#include <linux/clk.h>
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
cd4b45ac	14	#include <linux/of_device.h>
7e3b7dc7 YH	15	#include <linux/platform_device.h>
	16	#include <linux/pwm.h>
	17	#include <linux/slab.h>
	18
	19	#define DISP_PWM_EN 0x00
7e3b7dc7	20
7e3b7dc7 YH	21	#define PWM_CLKDIV_SHIFT 16
	22	#define PWM_CLKDIV_MAX 0x3ff
	23	#define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
	24
7e3b7dc7 YH	25	#define PWM_PERIOD_BIT_WIDTH 12
	26	#define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
	27
	28	#define PWM_HIGH_WIDTH_SHIFT 16
	29	#define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
	30
cd4b45ac WK	31	struct mtk_pwm_data {
	32	u32 enable_mask;
	33	unsigned int con0;
	34	u32 con0_sel;
	35	unsigned int con1;
	36
	37	bool has_commit;
	38	unsigned int commit;
	39	unsigned int commit_mask;
	40
	41	unsigned int bls_debug;
	42	u32 bls_debug_mask;
	43	};
	44
7e3b7dc7 YH	45	struct mtk_disp_pwm {
7e3b7dc7 YH	46	struct pwm_chip chip;
cd4b45ac	47	const struct mtk_pwm_data *data;
7e3b7dc7 YH	48	struct clk *clk_main;
	49	struct clk *clk_mm;
	50	void __iomem *base;
888a623d	51	bool enabled;
7e3b7dc7 YH	52	};
	53
	54	static inline struct mtk_disp_pwm to_mtk_disp_pwm(struct pwm_chip chip)
	55	{
	56	return container_of(chip, struct mtk_disp_pwm, chip);
	57	}
	58
	59	static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
	60	u32 mask, u32 data)
	61	{
	62	void __iomem *address = mdp->base + offset;
	63	u32 value;
	64
	65	value = readl(address);
	66	value &= ~mask;
	67	value \|= data;
	68	writel(value, address);
	69	}
	70
888a623d JS	71	static int mtk_disp_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
888a623d JS	72	const struct pwm_state *state)
7e3b7dc7 YH	73	{
	74	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	75	u32 clk_div, period, high_width, value;
	76	u64 div, rate;
	77	int err;
	78
888a623d JS	79	if (state->polarity != PWM_POLARITY_NORMAL)
	80	return -EINVAL;
	81
	82	if (!state->enabled) {
	83	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
	84	0x0);
	85
	86	if (mdp->enabled) {
	87	clk_disable_unprepare(mdp->clk_mm);
	88	clk_disable_unprepare(mdp->clk_main);
	89	}
	90
	91	mdp->enabled = false;
	92	return 0;
d7a4e582 JS	93	}
d7a4e582 JS	94
888a623d JS	95	if (!mdp->enabled) {
	96	err = clk_prepare_enable(mdp->clk_main);
	97	if (err < 0) {
	98	dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
	99	ERR_PTR(err));
	100	return err;
	101	}
	102
	103	err = clk_prepare_enable(mdp->clk_mm);
	104	if (err < 0) {
	105	dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
	106	ERR_PTR(err));
	107	clk_disable_unprepare(mdp->clk_main);
	108	return err;
	109	}
d7a4e582 JS	110	}
d7a4e582 JS	111
7e3b7dc7 YH	112	/*
	113	* Find period, high_width and clk_div to suit duty_ns and period_ns.
	114	* Calculate proper div value to keep period value in the bound.
	115	*
	116	* period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
	117	* duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
	118	*
	119	* period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
	120	* high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
	121	*/
	122	rate = clk_get_rate(mdp->clk_main);
331e049d	123	clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
7e3b7dc7	124	PWM_PERIOD_BIT_WIDTH;
d7a4e582	125	if (clk_div > PWM_CLKDIV_MAX) {
888a623d JS	126	if (!mdp->enabled) {
	127	clk_disable_unprepare(mdp->clk_mm);
	128	clk_disable_unprepare(mdp->clk_main);
	129	}
7e3b7dc7	130	return -EINVAL;
d7a4e582	131	}
7e3b7dc7 YH	132
7e3b7dc7 YH	133	div = NSEC_PER_SEC * (clk_div + 1);
331e049d	134	period = mul_u64_u64_div_u64(state->period, rate, div);
7e3b7dc7 YH	135	if (period > 0)
	136	period--;
	137
331e049d	138	high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
7e3b7dc7 YH	139	value = period \| (high_width << PWM_HIGH_WIDTH_SHIFT);
7e3b7dc7 YH	140
cd4b45ac WK	141	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
cd4b45ac WK	142	PWM_CLKDIV_MASK,
7e3b7dc7	143	clk_div << PWM_CLKDIV_SHIFT);
cd4b45ac WK	144	mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
	145	PWM_PERIOD_MASK \| PWM_HIGH_WIDTH_MASK,
	146	value);
	147
	148	if (mdp->data->has_commit) {
	149	mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
	150	mdp->data->commit_mask,
	151	mdp->data->commit_mask);
	152	mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
	153	mdp->data->commit_mask,
	154	0x0);
d7a4e582 JS	155	} else {
	156	/*
	157	* For MT2701, disable double buffer before writing register
	158	* and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
	159	*/
	160	mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
	161	mdp->data->bls_debug_mask,
	162	mdp->data->bls_debug_mask);
	163	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
	164	mdp->data->con0_sel,
	165	mdp->data->con0_sel);
cd4b45ac	166	}
7e3b7dc7	167
cd4b45ac WK	168	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
cd4b45ac WK	169	mdp->data->enable_mask);
888a623d	170	mdp->enabled = true;
7e3b7dc7 YH	171
	172	return 0;
	173	}
	174
3f2b1673 JS	175	static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
	176	struct pwm_device *pwm,
	177	struct pwm_state *state)
	178	{
	179	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	180	u64 rate, period, high_width;
0b5ef342	181	u32 clk_div, pwm_en, con0, con1;
3f2b1673 JS	182	int err;
	183
	184	err = clk_prepare_enable(mdp->clk_main);
	185	if (err < 0) {
	186	dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
	187	return;
	188	}
	189
	190	err = clk_prepare_enable(mdp->clk_mm);
	191	if (err < 0) {
	192	dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
	193	clk_disable_unprepare(mdp->clk_main);
	194	return;
	195	}
	196
	197	rate = clk_get_rate(mdp->clk_main);
	198	con0 = readl(mdp->base + mdp->data->con0);
	199	con1 = readl(mdp->base + mdp->data->con1);
0b5ef342	200	pwm_en = readl(mdp->base + DISP_PWM_EN);
0b5ef342	201	state->enabled = !!(pwm_en & mdp->data->enable_mask);
3f2b1673 JS	202	clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
	203	period = FIELD_GET(PWM_PERIOD_MASK, con1);
	204	/*
	205	* period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
	206	* so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
	207	*/
	208	state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
	209	high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
	210	state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
	211	rate);
	212	state->polarity = PWM_POLARITY_NORMAL;
	213	clk_disable_unprepare(mdp->clk_mm);
	214	clk_disable_unprepare(mdp->clk_main);
	215	}
	216
7e3b7dc7	217	static const struct pwm_ops mtk_disp_pwm_ops = {
888a623d	218	.apply = mtk_disp_pwm_apply,
3f2b1673	219	.get_state = mtk_disp_pwm_get_state,
7e3b7dc7 YH	220	.owner = THIS_MODULE,
	221	};
	222
	223	static int mtk_disp_pwm_probe(struct platform_device *pdev)
	224	{
	225	struct mtk_disp_pwm *mdp;
7e3b7dc7 YH	226	int ret;
	227
	228	mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
	229	if (!mdp)
	230	return -ENOMEM;
	231
cd4b45ac WK	232	mdp->data = of_device_get_match_data(&pdev->dev);
cd4b45ac WK	233
6e0301e7	234	mdp->base = devm_platform_ioremap_resource(pdev, 0);
7e3b7dc7 YH	235	if (IS_ERR(mdp->base))
	236	return PTR_ERR(mdp->base);
	237
	238	mdp->clk_main = devm_clk_get(&pdev->dev, "main");
	239	if (IS_ERR(mdp->clk_main))
	240	return PTR_ERR(mdp->clk_main);
	241
	242	mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
	243	if (IS_ERR(mdp->clk_mm))
	244	return PTR_ERR(mdp->clk_mm);
	245
7e3b7dc7 YH	246	mdp->chip.dev = &pdev->dev;
7e3b7dc7 YH	247	mdp->chip.ops = &mtk_disp_pwm_ops;
7e3b7dc7 YH	248	mdp->chip.npwm = 1;
	249
	250	ret = pwmchip_add(&mdp->chip);
	251	if (ret < 0) {
d7a4e582 JS	252	dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
d7a4e582 JS	253	return ret;
7e3b7dc7 YH	254	}
	255
	256	platform_set_drvdata(pdev, mdp);
	257
	258	return 0;
7e3b7dc7 YH	259	}
	260
	261	static int mtk_disp_pwm_remove(struct platform_device *pdev)
	262	{
	263	struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
7e3b7dc7	264
9b7b5736	265	pwmchip_remove(&mdp->chip);
7e3b7dc7	266
9b7b5736	267	return 0;
7e3b7dc7 YH	268	}
7e3b7dc7 YH	269
cd4b45ac WK	270	static const struct mtk_pwm_data mt2701_pwm_data = {
	271	.enable_mask = BIT(16),
	272	.con0 = 0xa8,
	273	.con0_sel = 0x2,
	274	.con1 = 0xac,
	275	.has_commit = false,
	276	.bls_debug = 0xb0,
	277	.bls_debug_mask = 0x3,
	278	};
	279
	280	static const struct mtk_pwm_data mt8173_pwm_data = {
	281	.enable_mask = BIT(0),
	282	.con0 = 0x10,
	283	.con0_sel = 0x0,
	284	.con1 = 0x14,
	285	.has_commit = true,
	286	.commit = 0x8,
	287	.commit_mask = 0x1,
	288	};
	289
a87b4061 JS	290	static const struct mtk_pwm_data mt8183_pwm_data = {
	291	.enable_mask = BIT(0),
	292	.con0 = 0x18,
	293	.con0_sel = 0x0,
	294	.con1 = 0x1c,
	295	.has_commit = false,
	296	.bls_debug = 0x80,
	297	.bls_debug_mask = 0x3,
	298	};
	299
7e3b7dc7	300	static const struct of_device_id mtk_disp_pwm_of_match[] = {
cd4b45ac WK	301	{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
	302	{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
	303	{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
a87b4061	304	{ .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
7e3b7dc7 YH	305	{ }
	306	};
	307	MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
	308
	309	static struct platform_driver mtk_disp_pwm_driver = {
	310	.driver = {
	311	.name = "mediatek-disp-pwm",
	312	.of_match_table = mtk_disp_pwm_of_match,
	313	},
	314	.probe = mtk_disp_pwm_probe,
	315	.remove = mtk_disp_pwm_remove,
	316	};
	317	module_platform_driver(mtk_disp_pwm_driver);
	318
	319	MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
	320	MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
	321	MODULE_LICENSE("GPL v2");