[linux-block.git] / drivers / pwm / pwm-mtk-disp.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * MediaTek display pulse-width-modulation controller driver.
 * Copyright (c) 2015 MediaTek Inc.
 * Author: YH Huang <yh.huang@mediatek.com>
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

#define DISP_PWM_EN		0x00

#define PWM_CLKDIV_SHIFT	16
#define PWM_CLKDIV_MAX		0x3ff
#define PWM_CLKDIV_MASK		(PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)

#define PWM_PERIOD_BIT_WIDTH	12
#define PWM_PERIOD_MASK		((1 << PWM_PERIOD_BIT_WIDTH) - 1)

#define PWM_HIGH_WIDTH_SHIFT	16
#define PWM_HIGH_WIDTH_MASK	(0x1fff << PWM_HIGH_WIDTH_SHIFT)

struct mtk_pwm_data {
	u32 enable_mask;
	unsigned int con0;
	u32 con0_sel;
	unsigned int con1;

	bool has_commit;
	unsigned int commit;
	unsigned int commit_mask;

	unsigned int bls_debug;
	u32 bls_debug_mask;
};

struct mtk_disp_pwm {
	const struct mtk_pwm_data *data;
	struct clk *clk_main;
	struct clk *clk_mm;
	void __iomem *base;
	bool enabled;
};

static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
				     u32 mask, u32 data)
{
	void __iomem *address = mdp->base + offset;
	u32 value;

	value = readl(address);
	value &= ~mask;
	value |= data;
	writel(value, address);
}

static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      const struct pwm_state *state)
{
	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	u32 clk_div, period, high_width, value;
	u64 div, rate;
	int err;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled && mdp->enabled) {
		mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN,
					 mdp->data->enable_mask, 0x0);
		clk_disable_unprepare(mdp->clk_mm);
		clk_disable_unprepare(mdp->clk_main);

		mdp->enabled = false;
		return 0;
	}

	if (!mdp->enabled) {
		err = clk_prepare_enable(mdp->clk_main);
		if (err < 0) {
			dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n",
				ERR_PTR(err));
			return err;
		}

		err = clk_prepare_enable(mdp->clk_mm);
		if (err < 0) {
			dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n",
				ERR_PTR(err));
			clk_disable_unprepare(mdp->clk_main);
			return err;
		}
	}

	/*
	 * Find period, high_width and clk_div to suit duty_ns and period_ns.
	 * Calculate proper div value to keep period value in the bound.
	 *
	 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
	 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
	 *
	 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
	 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
	 */
	rate = clk_get_rate(mdp->clk_main);
	clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
			  PWM_PERIOD_BIT_WIDTH;
	if (clk_div > PWM_CLKDIV_MAX) {
		if (!mdp->enabled) {
			clk_disable_unprepare(mdp->clk_mm);
			clk_disable_unprepare(mdp->clk_main);
		}
		return -EINVAL;
	}

	div = NSEC_PER_SEC * (clk_div + 1);
	period = mul_u64_u64_div_u64(state->period, rate, div);
	if (period > 0)
		period--;

	high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
	value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);

	if (mdp->data->bls_debug && !mdp->data->has_commit) {
		/*
		 * For MT2701, disable double buffer before writing register
		 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
		 */
		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
					 mdp->data->bls_debug_mask,
					 mdp->data->bls_debug_mask);
		mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
					 mdp->data->con0_sel,
					 mdp->data->con0_sel);
	}

	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
				 PWM_CLKDIV_MASK,
				 clk_div << PWM_CLKDIV_SHIFT);
	mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
				 PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
				 value);

	if (mdp->data->has_commit) {
		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
					 mdp->data->commit_mask,
					 mdp->data->commit_mask);
		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
					 mdp->data->commit_mask,
					 0x0);
	}

	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
				 mdp->data->enable_mask);
	mdp->enabled = true;

	return 0;
}

static int mtk_disp_pwm_get_state(struct pwm_chip *chip,
				  struct pwm_device *pwm,
				  struct pwm_state *state)
{
	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	u64 rate, period, high_width;
	u32 clk_div, pwm_en, con0, con1;
	int err;

	err = clk_prepare_enable(mdp->clk_main);
	if (err < 0) {
		dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
		return err;
	}

	err = clk_prepare_enable(mdp->clk_mm);
	if (err < 0) {
		dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
		clk_disable_unprepare(mdp->clk_main);
		return err;
	}

	/*
	 * Apply DISP_PWM_DEBUG settings to choose whether to enable or disable
	 * registers double buffer and manual commit to working register before
	 * performing any read/write operation
	 */
	if (mdp->data->bls_debug)
		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
					 mdp->data->bls_debug_mask,
					 mdp->data->bls_debug_mask);

	rate = clk_get_rate(mdp->clk_main);
	con0 = readl(mdp->base + mdp->data->con0);
	con1 = readl(mdp->base + mdp->data->con1);
	pwm_en = readl(mdp->base + DISP_PWM_EN);
	state->enabled = !!(pwm_en & mdp->data->enable_mask);
	clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
	period = FIELD_GET(PWM_PERIOD_MASK, con1);
	/*
	 * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
	 * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
	 */
	state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
	high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
	state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
					       rate);
	state->polarity = PWM_POLARITY_NORMAL;
	clk_disable_unprepare(mdp->clk_mm);
	clk_disable_unprepare(mdp->clk_main);

	return 0;
}

static const struct pwm_ops mtk_disp_pwm_ops = {
	.apply = mtk_disp_pwm_apply,
	.get_state = mtk_disp_pwm_get_state,
};

static int mtk_disp_pwm_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	struct mtk_disp_pwm *mdp;
	int ret;

	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*mdp));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	mdp = to_mtk_disp_pwm(chip);

	mdp->data = of_device_get_match_data(&pdev->dev);

	mdp->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mdp->base))
		return PTR_ERR(mdp->base);

	mdp->clk_main = devm_clk_get(&pdev->dev, "main");
	if (IS_ERR(mdp->clk_main))
		return dev_err_probe(&pdev->dev, PTR_ERR(mdp->clk_main),
				     "Failed to get main clock\n");

	mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
	if (IS_ERR(mdp->clk_mm))
		return dev_err_probe(&pdev->dev, PTR_ERR(mdp->clk_mm),
				     "Failed to get mm clock\n");

	chip->ops = &mtk_disp_pwm_ops;

	ret = devm_pwmchip_add(&pdev->dev, chip);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");

	return 0;
}

static const struct mtk_pwm_data mt2701_pwm_data = {
	.enable_mask = BIT(16),
	.con0 = 0xa8,
	.con0_sel = 0x2,
	.con1 = 0xac,
	.has_commit = false,
	.bls_debug = 0xb0,
	.bls_debug_mask = 0x3,
};

static const struct mtk_pwm_data mt8173_pwm_data = {
	.enable_mask = BIT(0),
	.con0 = 0x10,
	.con0_sel = 0x0,
	.con1 = 0x14,
	.has_commit = true,
	.commit = 0x8,
	.commit_mask = 0x1,
};

static const struct mtk_pwm_data mt8183_pwm_data = {
	.enable_mask = BIT(0),
	.con0 = 0x18,
	.con0_sel = 0x0,
	.con1 = 0x1c,
	.has_commit = false,
	.bls_debug = 0x80,
	.bls_debug_mask = 0x3,
};

static const struct of_device_id mtk_disp_pwm_of_match[] = {
	{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
	{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
	{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
	{ .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
	{ }
};
MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);

static struct platform_driver mtk_disp_pwm_driver = {
	.driver = {
		.name = "mediatek-disp-pwm",
		.of_match_table = mtk_disp_pwm_of_match,
	},
	.probe = mtk_disp_pwm_probe,
};
module_platform_driver(mtk_disp_pwm_driver);

MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
7e3b7dc7 YH	2	/*
	3	* MediaTek display pulse-width-modulation controller driver.
	4	* Copyright (c) 2015 MediaTek Inc.
	5	* Author: YH Huang <yh.huang@mediatek.com>
7e3b7dc7 YH	6	*/
7e3b7dc7 YH	7
3f2b1673	8	#include <linux/bitfield.h>
7e3b7dc7 YH	9	#include <linux/clk.h>
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/pwm.h>
	16	#include <linux/slab.h>
	17
	18	#define DISP_PWM_EN 0x00
7e3b7dc7	19
7e3b7dc7 YH	20	#define PWM_CLKDIV_SHIFT 16
	21	#define PWM_CLKDIV_MAX 0x3ff
	22	#define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
	23
7e3b7dc7 YH	24	#define PWM_PERIOD_BIT_WIDTH 12
	25	#define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
	26
	27	#define PWM_HIGH_WIDTH_SHIFT 16
	28	#define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
	29
cd4b45ac WK	30	struct mtk_pwm_data {
	31	u32 enable_mask;
	32	unsigned int con0;
	33	u32 con0_sel;
	34	unsigned int con1;
	35
	36	bool has_commit;
	37	unsigned int commit;
	38	unsigned int commit_mask;
	39
	40	unsigned int bls_debug;
	41	u32 bls_debug_mask;
	42	};
	43
7e3b7dc7	44	struct mtk_disp_pwm {
cd4b45ac	45	const struct mtk_pwm_data *data;
7e3b7dc7 YH	46	struct clk *clk_main;
	47	struct clk *clk_mm;
	48	void __iomem *base;
888a623d	49	bool enabled;
7e3b7dc7 YH	50	};
	51
	52	static inline struct mtk_disp_pwm to_mtk_disp_pwm(struct pwm_chip chip)
	53	{
ad082882	54	return pwmchip_get_drvdata(chip);
7e3b7dc7 YH	55	}
	56
	57	static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
	58	u32 mask, u32 data)
	59	{
	60	void __iomem *address = mdp->base + offset;
	61	u32 value;
	62
	63	value = readl(address);
	64	value &= ~mask;
	65	value \|= data;
	66	writel(value, address);
	67	}
	68
888a623d JS	69	static int mtk_disp_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
888a623d JS	70	const struct pwm_state *state)
7e3b7dc7 YH	71	{
	72	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	73	u32 clk_div, period, high_width, value;
	74	u64 div, rate;
	75	int err;
	76
888a623d JS	77	if (state->polarity != PWM_POLARITY_NORMAL)
	78	return -EINVAL;
	79
bc13d60e SL	80	if (!state->enabled && mdp->enabled) {
	81	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN,
	82	mdp->data->enable_mask, 0x0);
	83	clk_disable_unprepare(mdp->clk_mm);
	84	clk_disable_unprepare(mdp->clk_main);
888a623d JS	85
	86	mdp->enabled = false;
	87	return 0;
d7a4e582 JS	88	}
d7a4e582 JS	89
888a623d JS	90	if (!mdp->enabled) {
	91	err = clk_prepare_enable(mdp->clk_main);
	92	if (err < 0) {
f580fa6c	93	dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n",
888a623d JS	94	ERR_PTR(err));
	95	return err;
	96	}
	97
	98	err = clk_prepare_enable(mdp->clk_mm);
	99	if (err < 0) {
f580fa6c	100	dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n",
888a623d JS	101	ERR_PTR(err));
	102	clk_disable_unprepare(mdp->clk_main);
	103	return err;
	104	}
d7a4e582 JS	105	}
d7a4e582 JS	106
7e3b7dc7 YH	107	/*
	108	* Find period, high_width and clk_div to suit duty_ns and period_ns.
	109	* Calculate proper div value to keep period value in the bound.
	110	*
	111	* period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
	112	* duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
	113	*
	114	* period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
	115	* high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
	116	*/
	117	rate = clk_get_rate(mdp->clk_main);
331e049d	118	clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
7e3b7dc7	119	PWM_PERIOD_BIT_WIDTH;
d7a4e582	120	if (clk_div > PWM_CLKDIV_MAX) {
888a623d JS	121	if (!mdp->enabled) {
	122	clk_disable_unprepare(mdp->clk_mm);
	123	clk_disable_unprepare(mdp->clk_main);
	124	}
7e3b7dc7	125	return -EINVAL;
d7a4e582	126	}
7e3b7dc7 YH	127
7e3b7dc7 YH	128	div = NSEC_PER_SEC * (clk_div + 1);
331e049d	129	period = mul_u64_u64_div_u64(state->period, rate, div);
7e3b7dc7 YH	130	if (period > 0)
	131	period--;
	132
331e049d	133	high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
7e3b7dc7 YH	134	value = period \| (high_width << PWM_HIGH_WIDTH_SHIFT);
7e3b7dc7 YH	135
36dd7f53 ADR	136	if (mdp->data->bls_debug && !mdp->data->has_commit) {
	137	/*
	138	* For MT2701, disable double buffer before writing register
	139	* and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
	140	*/
	141	mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
	142	mdp->data->bls_debug_mask,
	143	mdp->data->bls_debug_mask);
	144	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
	145	mdp->data->con0_sel,
	146	mdp->data->con0_sel);
	147	}
	148
cd4b45ac WK	149	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
cd4b45ac WK	150	PWM_CLKDIV_MASK,
7e3b7dc7	151	clk_div << PWM_CLKDIV_SHIFT);
cd4b45ac WK	152	mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
	153	PWM_PERIOD_MASK \| PWM_HIGH_WIDTH_MASK,
	154	value);
	155
	156	if (mdp->data->has_commit) {
	157	mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
	158	mdp->data->commit_mask,
	159	mdp->data->commit_mask);
	160	mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
	161	mdp->data->commit_mask,
	162	0x0);
	163	}
7e3b7dc7	164
cd4b45ac WK	165	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
cd4b45ac WK	166	mdp->data->enable_mask);
888a623d	167	mdp->enabled = true;
7e3b7dc7 YH	168
	169	return 0;
	170	}
	171
6c452cff UKK	172	static int mtk_disp_pwm_get_state(struct pwm_chip *chip,
	173	struct pwm_device *pwm,
	174	struct pwm_state *state)
3f2b1673 JS	175	{
	176	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	177	u64 rate, period, high_width;
0b5ef342	178	u32 clk_div, pwm_en, con0, con1;
3f2b1673 JS	179	int err;
	180
	181	err = clk_prepare_enable(mdp->clk_main);
	182	if (err < 0) {
f580fa6c	183	dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
2f47786c	184	return err;
3f2b1673 JS	185	}
	186
	187	err = clk_prepare_enable(mdp->clk_mm);
	188	if (err < 0) {
f580fa6c	189	dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
3f2b1673	190	clk_disable_unprepare(mdp->clk_main);
2f47786c	191	return err;
3f2b1673 JS	192	}
3f2b1673 JS	193
b16c3101 ADR	194	/*
	195	* Apply DISP_PWM_DEBUG settings to choose whether to enable or disable
	196	* registers double buffer and manual commit to working register before
	197	* performing any read/write operation
	198	*/
	199	if (mdp->data->bls_debug)
	200	mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
	201	mdp->data->bls_debug_mask,
	202	mdp->data->bls_debug_mask);
	203
3f2b1673 JS	204	rate = clk_get_rate(mdp->clk_main);
	205	con0 = readl(mdp->base + mdp->data->con0);
	206	con1 = readl(mdp->base + mdp->data->con1);
0b5ef342	207	pwm_en = readl(mdp->base + DISP_PWM_EN);
0b5ef342	208	state->enabled = !!(pwm_en & mdp->data->enable_mask);
3f2b1673 JS	209	clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
	210	period = FIELD_GET(PWM_PERIOD_MASK, con1);
	211	/*
	212	* period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
	213	* so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
	214	*/
	215	state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
	216	high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
	217	state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
	218	rate);
	219	state->polarity = PWM_POLARITY_NORMAL;
	220	clk_disable_unprepare(mdp->clk_mm);
	221	clk_disable_unprepare(mdp->clk_main);
6c452cff UKK	222
6c452cff UKK	223	return 0;
3f2b1673 JS	224	}
3f2b1673 JS	225
7e3b7dc7	226	static const struct pwm_ops mtk_disp_pwm_ops = {
888a623d	227	.apply = mtk_disp_pwm_apply,
3f2b1673	228	.get_state = mtk_disp_pwm_get_state,
7e3b7dc7 YH	229	};
	230
	231	static int mtk_disp_pwm_probe(struct platform_device *pdev)
	232	{
ad082882	233	struct pwm_chip *chip;
7e3b7dc7	234	struct mtk_disp_pwm *mdp;
7e3b7dc7 YH	235	int ret;
7e3b7dc7 YH	236
ad082882 UKK	237	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*mdp));
	238	if (IS_ERR(chip))
	239	return PTR_ERR(chip);
	240	mdp = to_mtk_disp_pwm(chip);
7e3b7dc7	241
cd4b45ac WK	242	mdp->data = of_device_get_match_data(&pdev->dev);
cd4b45ac WK	243
6e0301e7	244	mdp->base = devm_platform_ioremap_resource(pdev, 0);
7e3b7dc7 YH	245	if (IS_ERR(mdp->base))
	246	return PTR_ERR(mdp->base);
	247
	248	mdp->clk_main = devm_clk_get(&pdev->dev, "main");
	249	if (IS_ERR(mdp->clk_main))
05c9b6f8 UKK	250	return dev_err_probe(&pdev->dev, PTR_ERR(mdp->clk_main),
05c9b6f8 UKK	251	"Failed to get main clock\n");
7e3b7dc7 YH	252
	253	mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
	254	if (IS_ERR(mdp->clk_mm))
05c9b6f8 UKK	255	return dev_err_probe(&pdev->dev, PTR_ERR(mdp->clk_mm),
05c9b6f8 UKK	256	"Failed to get mm clock\n");
7e3b7dc7	257
ad082882	258	chip->ops = &mtk_disp_pwm_ops;
7e3b7dc7	259
ad082882	260	ret = devm_pwmchip_add(&pdev->dev, chip);
05c9b6f8 UKK	261	if (ret < 0)
05c9b6f8 UKK	262	return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
7e3b7dc7 YH	263
7e3b7dc7 YH	264	return 0;
7e3b7dc7 YH	265	}
7e3b7dc7 YH	266
cd4b45ac WK	267	static const struct mtk_pwm_data mt2701_pwm_data = {
	268	.enable_mask = BIT(16),
	269	.con0 = 0xa8,
	270	.con0_sel = 0x2,
	271	.con1 = 0xac,
	272	.has_commit = false,
	273	.bls_debug = 0xb0,
	274	.bls_debug_mask = 0x3,
	275	};
	276
	277	static const struct mtk_pwm_data mt8173_pwm_data = {
	278	.enable_mask = BIT(0),
	279	.con0 = 0x10,
	280	.con0_sel = 0x0,
	281	.con1 = 0x14,
	282	.has_commit = true,
	283	.commit = 0x8,
	284	.commit_mask = 0x1,
	285	};
	286
a87b4061 JS	287	static const struct mtk_pwm_data mt8183_pwm_data = {
	288	.enable_mask = BIT(0),
	289	.con0 = 0x18,
	290	.con0_sel = 0x0,
	291	.con1 = 0x1c,
	292	.has_commit = false,
	293	.bls_debug = 0x80,
	294	.bls_debug_mask = 0x3,
	295	};
	296
7e3b7dc7	297	static const struct of_device_id mtk_disp_pwm_of_match[] = {
cd4b45ac WK	298	{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
	299	{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
	300	{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
a87b4061	301	{ .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
7e3b7dc7 YH	302	{ }
	303	};
	304	MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
	305
	306	static struct platform_driver mtk_disp_pwm_driver = {
	307	.driver = {
	308	.name = "mediatek-disp-pwm",
	309	.of_match_table = mtk_disp_pwm_of_match,
	310	},
	311	.probe = mtk_disp_pwm_probe,
7e3b7dc7 YH	312	};
	313	module_platform_driver(mtk_disp_pwm_driver);
	314
	315	MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
	316	MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
	317	MODULE_LICENSE("GPL v2");