[linux-block.git] / drivers / pwm / pwm-meson.c

// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
 * PWM controller driver for Amlogic Meson SoCs.
 *
 * This PWM is only a set of Gates, Dividers and Counters:
 * PWM output is achieved by calculating a clock that permits calculating
 * two periods (low and high). The counter then has to be set to switch after
 * N cycles for the first half period.
 * The hardware has no "polarity" setting. This driver reverses the period
 * cycles (the low length is inverted with the high length) for
 * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
 * from the hardware.
 * Setting the duty cycle will disable and re-enable the PWM output.
 * Disabling the PWM stops the output immediately (without waiting for the
 * current period to complete first).
 *
 * The public S912 (GXM) datasheet contains some documentation for this PWM
 * controller starting on page 543:
 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
 * An updated version of this IP block is found in S922X (G12B) SoCs. The
 * datasheet contains the description for this IP block revision starting at
 * page 1084:
 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
 *
 * Copyright (c) 2016 BayLibre, SAS.
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 * Copyright (C) 2014 Amlogic, Inc.
 */

#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define REG_PWM_A		0x0
#define REG_PWM_B		0x4
#define PWM_LOW_MASK		GENMASK(15, 0)
#define PWM_HIGH_MASK		GENMASK(31, 16)

#define REG_MISC_AB		0x8
#define MISC_B_CLK_EN		BIT(23)
#define MISC_A_CLK_EN		BIT(15)
#define MISC_CLK_DIV_MASK	0x7f
#define MISC_B_CLK_DIV_SHIFT	16
#define MISC_A_CLK_DIV_SHIFT	8
#define MISC_B_CLK_SEL_SHIFT	6
#define MISC_A_CLK_SEL_SHIFT	4
#define MISC_CLK_SEL_MASK	0x3
#define MISC_B_EN		BIT(1)
#define MISC_A_EN		BIT(0)

#define MESON_NUM_PWMS		2

static struct meson_pwm_channel_data {
	u8		reg_offset;
	u8		clk_sel_shift;
	u8		clk_div_shift;
	u32		clk_en_mask;
	u32		pwm_en_mask;
} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
	{
		.reg_offset	= REG_PWM_A,
		.clk_sel_shift	= MISC_A_CLK_SEL_SHIFT,
		.clk_div_shift	= MISC_A_CLK_DIV_SHIFT,
		.clk_en_mask	= MISC_A_CLK_EN,
		.pwm_en_mask	= MISC_A_EN,
	},
	{
		.reg_offset	= REG_PWM_B,
		.clk_sel_shift	= MISC_B_CLK_SEL_SHIFT,
		.clk_div_shift	= MISC_B_CLK_DIV_SHIFT,
		.clk_en_mask	= MISC_B_CLK_EN,
		.pwm_en_mask	= MISC_B_EN,
	}
};

struct meson_pwm_channel {
	unsigned int hi;
	unsigned int lo;
	u8 pre_div;

	struct clk *clk_parent;
	struct clk_mux mux;
	struct clk *clk;
};

struct meson_pwm_data {
	const char * const *parent_names;
	unsigned int num_parents;
};

struct meson_pwm {
	struct pwm_chip chip;
	const struct meson_pwm_data *data;
	struct meson_pwm_channel channels[MESON_NUM_PWMS];
	void __iomem *base;
	/*
	 * Protects register (write) access to the REG_MISC_AB register
	 * that is shared between the two PWMs.
	 */
	spinlock_t lock;
};

static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct meson_pwm, chip);
}

static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct meson_pwm *meson = to_meson_pwm(chip);
	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
	struct device *dev = chip->dev;
	int err;

	if (channel->clk_parent) {
		err = clk_set_parent(channel->clk, channel->clk_parent);
		if (err < 0) {
			dev_err(dev, "failed to set parent %s for %s: %d\n",
				__clk_get_name(channel->clk_parent),
				__clk_get_name(channel->clk), err);
			return err;
		}
	}

	err = clk_prepare_enable(channel->clk);
	if (err < 0) {
		dev_err(dev, "failed to enable clock %s: %d\n",
			__clk_get_name(channel->clk), err);
		return err;
	}

	return pwm_set_chip_data(pwm, channel);
}

static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);

	clk_disable_unprepare(channel->clk);
}

static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
			  const struct pwm_state *state)
{
	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
	unsigned int duty, period, pre_div, cnt, duty_cnt;
	unsigned long fin_freq;

	duty = state->duty_cycle;
	period = state->period;

	if (state->polarity == PWM_POLARITY_INVERSED)
		duty = period - duty;

	fin_freq = clk_get_rate(channel->clk);
	if (fin_freq == 0) {
		dev_err(meson->chip.dev, "invalid source clock frequency\n");
		return -EINVAL;
	}

	dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);

	pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
	if (pre_div > MISC_CLK_DIV_MASK) {
		dev_err(meson->chip.dev, "unable to get period pre_div\n");
		return -EINVAL;
	}

	cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
	if (cnt > 0xffff) {
		dev_err(meson->chip.dev, "unable to get period cnt\n");
		return -EINVAL;
	}

	dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
		pre_div, cnt);

	if (duty == period) {
		channel->pre_div = pre_div;
		channel->hi = cnt;
		channel->lo = 0;
	} else if (duty == 0) {
		channel->pre_div = pre_div;
		channel->hi = 0;
		channel->lo = cnt;
	} else {
		/* Then check is we can have the duty with the same pre_div */
		duty_cnt = div64_u64(fin_freq * (u64)duty,
				     NSEC_PER_SEC * (pre_div + 1));
		if (duty_cnt > 0xffff) {
			dev_err(meson->chip.dev, "unable to get duty cycle\n");
			return -EINVAL;
		}

		dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
			duty, pre_div, duty_cnt);

		channel->pre_div = pre_div;
		channel->hi = duty_cnt;
		channel->lo = cnt - duty_cnt;
	}

	return 0;
}

static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
{
	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
	struct meson_pwm_channel_data *channel_data;
	unsigned long flags;
	u32 value;

	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];

	spin_lock_irqsave(&meson->lock, flags);

	value = readl(meson->base + REG_MISC_AB);
	value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
	value |= channel->pre_div << channel_data->clk_div_shift;
	value |= channel_data->clk_en_mask;
	writel(value, meson->base + REG_MISC_AB);

	value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
		FIELD_PREP(PWM_LOW_MASK, channel->lo);
	writel(value, meson->base + channel_data->reg_offset);

	value = readl(meson->base + REG_MISC_AB);
	value |= channel_data->pwm_en_mask;
	writel(value, meson->base + REG_MISC_AB);

	spin_unlock_irqrestore(&meson->lock, flags);
}

static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
{
	unsigned long flags;
	u32 value;

	spin_lock_irqsave(&meson->lock, flags);

	value = readl(meson->base + REG_MISC_AB);
	value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
	writel(value, meson->base + REG_MISC_AB);

	spin_unlock_irqrestore(&meson->lock, flags);
}

static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
	struct meson_pwm *meson = to_meson_pwm(chip);
	int err = 0;

	if (!state)
		return -EINVAL;

	if (!state->enabled) {
		if (state->polarity == PWM_POLARITY_INVERSED) {
			/*
			 * This IP block revision doesn't have an "always high"
			 * setting which we can use for "inverted disabled".
			 * Instead we achieve this using the same settings
			 * that we use a pre_div of 0 (to get the shortest
			 * possible duration for one "count") and
			 * "period == duty_cycle". This results in a signal
			 * which is LOW for one "count", while being HIGH for
			 * the rest of the (so the signal is HIGH for slightly
			 * less than 100% of the period, but this is the best
			 * we can achieve).
			 */
			channel->pre_div = 0;
			channel->hi = ~0;
			channel->lo = 0;

			meson_pwm_enable(meson, pwm);
		} else {
			meson_pwm_disable(meson, pwm);
		}
	} else {
		err = meson_pwm_calc(meson, pwm, state);
		if (err < 0)
			return err;

		meson_pwm_enable(meson, pwm);
	}

	return 0;
}

static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
					struct pwm_device *pwm, u32 cnt)
{
	struct meson_pwm *meson = to_meson_pwm(chip);
	struct meson_pwm_channel *channel;
	unsigned long fin_freq;
	u32 fin_ns;

	/* to_meson_pwm() can only be used after .get_state() is called */
	channel = &meson->channels[pwm->hwpwm];

	fin_freq = clk_get_rate(channel->clk);
	if (fin_freq == 0)
		return 0;

	fin_ns = div_u64(NSEC_PER_SEC, fin_freq);

	return cnt * fin_ns * (channel->pre_div + 1);
}

static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				struct pwm_state *state)
{
	struct meson_pwm *meson = to_meson_pwm(chip);
	struct meson_pwm_channel_data *channel_data;
	struct meson_pwm_channel *channel;
	u32 value, tmp;

	if (!state)
		return;

	channel = &meson->channels[pwm->hwpwm];
	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];

	value = readl(meson->base + REG_MISC_AB);

	tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
	state->enabled = (value & tmp) == tmp;

	tmp = value >> channel_data->clk_div_shift;
	channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);

	value = readl(meson->base + channel_data->reg_offset);

	channel->lo = FIELD_GET(PWM_LOW_MASK, value);
	channel->hi = FIELD_GET(PWM_HIGH_MASK, value);

	if (channel->lo == 0) {
		state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
		state->duty_cycle = state->period;
	} else if (channel->lo >= channel->hi) {
		state->period = meson_pwm_cnt_to_ns(chip, pwm,
						    channel->lo + channel->hi);
		state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
							channel->hi);
	} else {
		state->period = 0;
		state->duty_cycle = 0;
	}
}

static const struct pwm_ops meson_pwm_ops = {
	.request = meson_pwm_request,
	.free = meson_pwm_free,
	.apply = meson_pwm_apply,
	.get_state = meson_pwm_get_state,
	.owner = THIS_MODULE,
};

static const char * const pwm_meson8b_parent_names[] = {
	"xtal", "vid_pll", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_meson8b_data = {
	.parent_names = pwm_meson8b_parent_names,
	.num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
};

static const char * const pwm_gxbb_parent_names[] = {
	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_gxbb_data = {
	.parent_names = pwm_gxbb_parent_names,
	.num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
};

/*
 * Only the 2 first inputs of the GXBB AO PWMs are valid
 * The last 2 are grounded
 */
static const char * const pwm_gxbb_ao_parent_names[] = {
	"xtal", "clk81"
};

static const struct meson_pwm_data pwm_gxbb_ao_data = {
	.parent_names = pwm_gxbb_ao_parent_names,
	.num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
};

static const char * const pwm_axg_ee_parent_names[] = {
	"xtal", "fclk_div5", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_axg_ee_data = {
	.parent_names = pwm_axg_ee_parent_names,
	.num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
};

static const char * const pwm_axg_ao_parent_names[] = {
	"aoclk81", "xtal", "fclk_div4", "fclk_div5"
};

static const struct meson_pwm_data pwm_axg_ao_data = {
	.parent_names = pwm_axg_ao_parent_names,
	.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
};

static const char * const pwm_g12a_ao_ab_parent_names[] = {
	"xtal", "aoclk81", "fclk_div4", "fclk_div5"
};

static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
	.parent_names = pwm_g12a_ao_ab_parent_names,
	.num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
};

static const char * const pwm_g12a_ao_cd_parent_names[] = {
	"xtal", "aoclk81",
};

static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
	.parent_names = pwm_g12a_ao_cd_parent_names,
	.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
};

static const char * const pwm_g12a_ee_parent_names[] = {
	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_g12a_ee_data = {
	.parent_names = pwm_g12a_ee_parent_names,
	.num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
};

static const struct of_device_id meson_pwm_matches[] = {
	{
		.compatible = "amlogic,meson8b-pwm",
		.data = &pwm_meson8b_data
	},
	{
		.compatible = "amlogic,meson-gxbb-pwm",
		.data = &pwm_gxbb_data
	},
	{
		.compatible = "amlogic,meson-gxbb-ao-pwm",
		.data = &pwm_gxbb_ao_data
	},
	{
		.compatible = "amlogic,meson-axg-ee-pwm",
		.data = &pwm_axg_ee_data
	},
	{
		.compatible = "amlogic,meson-axg-ao-pwm",
		.data = &pwm_axg_ao_data
	},
	{
		.compatible = "amlogic,meson-g12a-ee-pwm",
		.data = &pwm_g12a_ee_data
	},
	{
		.compatible = "amlogic,meson-g12a-ao-pwm-ab",
		.data = &pwm_g12a_ao_ab_data
	},
	{
		.compatible = "amlogic,meson-g12a-ao-pwm-cd",
		.data = &pwm_g12a_ao_cd_data
	},
	{},
};
MODULE_DEVICE_TABLE(of, meson_pwm_matches);

static int meson_pwm_init_channels(struct meson_pwm *meson)
{
	struct device *dev = meson->chip.dev;
	struct clk_init_data init;
	unsigned int i;
	char name[255];
	int err;

	for (i = 0; i < meson->chip.npwm; i++) {
		struct meson_pwm_channel *channel = &meson->channels[i];

		snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);

		init.name = name;
		init.ops = &clk_mux_ops;
		init.flags = 0;
		init.parent_names = meson->data->parent_names;
		init.num_parents = meson->data->num_parents;

		channel->mux.reg = meson->base + REG_MISC_AB;
		channel->mux.shift =
				meson_pwm_per_channel_data[i].clk_sel_shift;
		channel->mux.mask = MISC_CLK_SEL_MASK;
		channel->mux.flags = 0;
		channel->mux.lock = &meson->lock;
		channel->mux.table = NULL;
		channel->mux.hw.init = &init;

		channel->clk = devm_clk_register(dev, &channel->mux.hw);
		if (IS_ERR(channel->clk)) {
			err = PTR_ERR(channel->clk);
			dev_err(dev, "failed to register %s: %d\n", name, err);
			return err;
		}

		snprintf(name, sizeof(name), "clkin%u", i);

		channel->clk_parent = devm_clk_get_optional(dev, name);
		if (IS_ERR(channel->clk_parent))
			return PTR_ERR(channel->clk_parent);
	}

	return 0;
}

static int meson_pwm_probe(struct platform_device *pdev)
{
	struct meson_pwm *meson;
	int err;

	meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
	if (!meson)
		return -ENOMEM;

	meson->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(meson->base))
		return PTR_ERR(meson->base);

	spin_lock_init(&meson->lock);
	meson->chip.dev = &pdev->dev;
	meson->chip.ops = &meson_pwm_ops;
	meson->chip.npwm = MESON_NUM_PWMS;

	meson->data = of_device_get_match_data(&pdev->dev);

	err = meson_pwm_init_channels(meson);
	if (err < 0)
		return err;

	err = devm_pwmchip_add(&pdev->dev, &meson->chip);
	if (err < 0) {
		dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
		return err;
	}

	return 0;
}

static struct platform_driver meson_pwm_driver = {
	.driver = {
		.name = "meson-pwm",
		.of_match_table = meson_pwm_matches,
	},
	.probe = meson_pwm_probe,
};
module_platform_driver(meson_pwm_driver);

MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_LICENSE("Dual BSD/GPL");
Commit	Line	Data
1cdb4413	1	// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
211ed630	2	/*
4ae42ce7 MB	3	* PWM controller driver for Amlogic Meson SoCs.
	4	*
	5	* This PWM is only a set of Gates, Dividers and Counters:
	6	* PWM output is achieved by calculating a clock that permits calculating
	7	* two periods (low and high). The counter then has to be set to switch after
	8	* N cycles for the first half period.
	9	* The hardware has no "polarity" setting. This driver reverses the period
	10	* cycles (the low length is inverted with the high length) for
	11	* PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
	12	* from the hardware.
	13	* Setting the duty cycle will disable and re-enable the PWM output.
	14	* Disabling the PWM stops the output immediately (without waiting for the
	15	* current period to complete first).
	16	*
	17	* The public S912 (GXM) datasheet contains some documentation for this PWM
	18	* controller starting on page 543:
	19	* https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
	20	* An updated version of this IP block is found in S922X (G12B) SoCs. The
	21	* datasheet contains the description for this IP block revision starting at
	22	* page 1084:
	23	* https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
	24	*
211ed630 NA	25	* Copyright (c) 2016 BayLibre, SAS.
	26	* Author: Neil Armstrong <narmstrong@baylibre.com>
	27	* Copyright (C) 2014 Amlogic, Inc.
211ed630 NA	28	*/
211ed630 NA	29
181164b6 MB	30	#include <linux/bitfield.h>
181164b6 MB	31	#include <linux/bits.h>
211ed630 NA	32	#include <linux/clk.h>
	33	#include <linux/clk-provider.h>
	34	#include <linux/err.h>
	35	#include <linux/io.h>
	36	#include <linux/kernel.h>
fb2081e8	37	#include <linux/math64.h>
211ed630 NA	38	#include <linux/module.h>
	39	#include <linux/of.h>
	40	#include <linux/of_device.h>
	41	#include <linux/platform_device.h>
	42	#include <linux/pwm.h>
	43	#include <linux/slab.h>
	44	#include <linux/spinlock.h>
	45
	46	#define REG_PWM_A 0x0
	47	#define REG_PWM_B 0x4
181164b6 MB	48	#define PWM_LOW_MASK GENMASK(15, 0)
181164b6 MB	49	#define PWM_HIGH_MASK GENMASK(31, 16)
211ed630 NA	50
	51	#define REG_MISC_AB 0x8
	52	#define MISC_B_CLK_EN BIT(23)
	53	#define MISC_A_CLK_EN BIT(15)
	54	#define MISC_CLK_DIV_MASK 0x7f
	55	#define MISC_B_CLK_DIV_SHIFT 16
	56	#define MISC_A_CLK_DIV_SHIFT 8
	57	#define MISC_B_CLK_SEL_SHIFT 6
	58	#define MISC_A_CLK_SEL_SHIFT 4
33cefd84	59	#define MISC_CLK_SEL_MASK 0x3
211ed630 NA	60	#define MISC_B_EN BIT(1)
	61	#define MISC_A_EN BIT(0)
	62
a50a49a4 MB	63	#define MESON_NUM_PWMS 2
a50a49a4 MB	64
8bbf3164 MB	65	static struct meson_pwm_channel_data {
	66	u8 reg_offset;
	67	u8 clk_sel_shift;
	68	u8 clk_div_shift;
	69	u32 clk_en_mask;
	70	u32 pwm_en_mask;
	71	} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
	72	{
	73	.reg_offset = REG_PWM_A,
	74	.clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
	75	.clk_div_shift = MISC_A_CLK_DIV_SHIFT,
	76	.clk_en_mask = MISC_A_CLK_EN,
	77	.pwm_en_mask = MISC_A_EN,
	78	},
	79	{
	80	.reg_offset = REG_PWM_B,
	81	.clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
	82	.clk_div_shift = MISC_B_CLK_DIV_SHIFT,
	83	.clk_en_mask = MISC_B_CLK_EN,
	84	.pwm_en_mask = MISC_B_EN,
	85	}
211ed630 NA	86	};
	87
	88	struct meson_pwm_channel {
	89	unsigned int hi;
	90	unsigned int lo;
	91	u8 pre_div;
	92
211ed630 NA	93	struct clk *clk_parent;
	94	struct clk_mux mux;
	95	struct clk *clk;
	96	};
	97
	98	struct meson_pwm_data {
	99	const char * const *parent_names;
d396b20a	100	unsigned int num_parents;
211ed630 NA	101	};
	102
	103	struct meson_pwm {
	104	struct pwm_chip chip;
	105	const struct meson_pwm_data *data;
a50a49a4	106	struct meson_pwm_channel channels[MESON_NUM_PWMS];
211ed630	107	void __iomem *base;
f173747f MB	108	/*
	109	* Protects register (write) access to the REG_MISC_AB register
	110	* that is shared between the two PWMs.
	111	*/
211ed630 NA	112	spinlock_t lock;
	113	};
	114
	115	static inline struct meson_pwm to_meson_pwm(struct pwm_chip chip)
	116	{
	117	return container_of(chip, struct meson_pwm, chip);
	118	}
	119
	120	static int meson_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	121	{
1064c6ba	122	struct meson_pwm *meson = to_meson_pwm(chip);
37349609	123	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
211ed630 NA	124	struct device *dev = chip->dev;
	125	int err;
	126
211ed630 NA	127	if (channel->clk_parent) {
	128	err = clk_set_parent(channel->clk, channel->clk_parent);
	129	if (err < 0) {
	130	dev_err(dev, "failed to set parent %s for %s: %d\n",
	131	__clk_get_name(channel->clk_parent),
	132	__clk_get_name(channel->clk), err);
b33d232e	133	return err;
211ed630 NA	134	}
	135	}
	136
	137	err = clk_prepare_enable(channel->clk);
	138	if (err < 0) {
	139	dev_err(dev, "failed to enable clock %s: %d\n",
	140	__clk_get_name(channel->clk), err);
	141	return err;
	142	}
	143
1064c6ba	144	return pwm_set_chip_data(pwm, channel);
211ed630 NA	145	}
	146
	147	static void meson_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	148	{
	149	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
	150
cb971fdb	151	clk_disable_unprepare(channel->clk);
211ed630 NA	152	}
211ed630 NA	153
7e032162	154	static int meson_pwm_calc(struct meson_pwm meson, struct pwm_device pwm,
71523d18	155	const struct pwm_state *state)
211ed630	156	{
7e032162	157	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
b79c3670	158	unsigned int duty, period, pre_div, cnt, duty_cnt;
437fb760	159	unsigned long fin_freq;
211ed630	160
b79c3670 MB	161	duty = state->duty_cycle;
	162	period = state->period;
	163
	164	if (state->polarity == PWM_POLARITY_INVERSED)
211ed630 NA	165	duty = period - duty;
211ed630 NA	166
211ed630 NA	167	fin_freq = clk_get_rate(channel->clk);
	168	if (fin_freq == 0) {
	169	dev_err(meson->chip.dev, "invalid source clock frequency\n");
	170	return -EINVAL;
	171	}
	172
	173	dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
211ed630	174
fb2081e8	175	pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
51496e44	176	if (pre_div > MISC_CLK_DIV_MASK) {
211ed630 NA	177	dev_err(meson->chip.dev, "unable to get period pre_div\n");
	178	return -EINVAL;
	179	}
	180
fb2081e8 MB	181	cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
	182	if (cnt > 0xffff) {
	183	dev_err(meson->chip.dev, "unable to get period cnt\n");
	184	return -EINVAL;
	185	}
	186
211ed630 NA	187	dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
	188	pre_div, cnt);
	189
	190	if (duty == period) {
	191	channel->pre_div = pre_div;
	192	channel->hi = cnt;
	193	channel->lo = 0;
	194	} else if (duty == 0) {
	195	channel->pre_div = pre_div;
	196	channel->hi = 0;
	197	channel->lo = cnt;
	198	} else {
	199	/* Then check is we can have the duty with the same pre_div */
fb2081e8 MB	200	duty_cnt = div64_u64(fin_freq * (u64)duty,
fb2081e8 MB	201	NSEC_PER_SEC * (pre_div + 1));
211ed630 NA	202	if (duty_cnt > 0xffff) {
	203	dev_err(meson->chip.dev, "unable to get duty cycle\n");
	204	return -EINVAL;
	205	}
	206
	207	dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
	208	duty, pre_div, duty_cnt);
	209
	210	channel->pre_div = pre_div;
	211	channel->hi = duty_cnt;
	212	channel->lo = cnt - duty_cnt;
	213	}
	214
	215	return 0;
	216	}
	217
084f1376	218	static void meson_pwm_enable(struct meson_pwm meson, struct pwm_device pwm)
211ed630	219	{
084f1376	220	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
8bbf3164	221	struct meson_pwm_channel_data *channel_data;
f173747f	222	unsigned long flags;
8bbf3164	223	u32 value;
211ed630	224
8bbf3164	225	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
211ed630	226
f173747f MB	227	spin_lock_irqsave(&meson->lock, flags);
f173747f MB	228
211ed630	229	value = readl(meson->base + REG_MISC_AB);
8bbf3164 MB	230	value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
	231	value \|= channel->pre_div << channel_data->clk_div_shift;
	232	value \|= channel_data->clk_en_mask;
211ed630 NA	233	writel(value, meson->base + REG_MISC_AB);
211ed630 NA	234
181164b6 MB	235	value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) \|
181164b6 MB	236	FIELD_PREP(PWM_LOW_MASK, channel->lo);
8bbf3164	237	writel(value, meson->base + channel_data->reg_offset);
211ed630 NA	238
211ed630 NA	239	value = readl(meson->base + REG_MISC_AB);
8bbf3164	240	value \|= channel_data->pwm_en_mask;
211ed630	241	writel(value, meson->base + REG_MISC_AB);
f173747f MB	242
f173747f MB	243	spin_unlock_irqrestore(&meson->lock, flags);
211ed630 NA	244	}
211ed630 NA	245
084f1376	246	static void meson_pwm_disable(struct meson_pwm meson, struct pwm_device pwm)
211ed630	247	{
f173747f	248	unsigned long flags;
8bbf3164	249	u32 value;
211ed630	250
f173747f MB	251	spin_lock_irqsave(&meson->lock, flags);
f173747f MB	252
211ed630	253	value = readl(meson->base + REG_MISC_AB);
8bbf3164	254	value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
211ed630	255	writel(value, meson->base + REG_MISC_AB);
f173747f MB	256
f173747f MB	257	spin_unlock_irqrestore(&meson->lock, flags);
211ed630 NA	258	}
	259
	260	static int meson_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	261	const struct pwm_state *state)
211ed630	262	{
7341c785	263	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
211ed630	264	struct meson_pwm *meson = to_meson_pwm(chip);
211ed630 NA	265	int err = 0;
	266
	267	if (!state)
	268	return -EINVAL;
	269
211ed630	270	if (!state->enabled) {
7341c785 MB	271	if (state->polarity == PWM_POLARITY_INVERSED) {
	272	/*
	273	* This IP block revision doesn't have an "always high"
	274	* setting which we can use for "inverted disabled".
	275	* Instead we achieve this using the same settings
	276	* that we use a pre_div of 0 (to get the shortest
	277	* possible duration for one "count") and
	278	* "period == duty_cycle". This results in a signal
	279	* which is LOW for one "count", while being HIGH for
	280	* the rest of the (so the signal is HIGH for slightly
	281	* less than 100% of the period, but this is the best
	282	* we can achieve).
	283	*/
	284	channel->pre_div = 0;
	285	channel->hi = ~0;
	286	channel->lo = 0;
	287
	288	meson_pwm_enable(meson, pwm);
	289	} else {
	290	meson_pwm_disable(meson, pwm);
	291	}
d6885b3e	292	} else {
7e032162	293	err = meson_pwm_calc(meson, pwm, state);
211ed630	294	if (err < 0)
f173747f	295	return err;
211ed630	296
084f1376	297	meson_pwm_enable(meson, pwm);
211ed630 NA	298	}
211ed630 NA	299
f173747f	300	return 0;
211ed630 NA	301	}
211ed630 NA	302
c375bcba MB	303	static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
	304	struct pwm_device *pwm, u32 cnt)
	305	{
	306	struct meson_pwm *meson = to_meson_pwm(chip);
	307	struct meson_pwm_channel *channel;
	308	unsigned long fin_freq;
	309	u32 fin_ns;
	310
	311	/* to_meson_pwm() can only be used after .get_state() is called */
	312	channel = &meson->channels[pwm->hwpwm];
	313
	314	fin_freq = clk_get_rate(channel->clk);
	315	if (fin_freq == 0)
	316	return 0;
	317
	318	fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
	319
	320	return cnt * fin_ns * (channel->pre_div + 1);
	321	}
	322
211ed630 NA	323	static void meson_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
	324	struct pwm_state *state)
	325	{
	326	struct meson_pwm *meson = to_meson_pwm(chip);
c375bcba MB	327	struct meson_pwm_channel_data *channel_data;
	328	struct meson_pwm_channel *channel;
	329	u32 value, tmp;
211ed630 NA	330
	331	if (!state)
	332	return;
	333
c375bcba MB	334	channel = &meson->channels[pwm->hwpwm];
c375bcba MB	335	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
211ed630 NA	336
211ed630 NA	337	value = readl(meson->base + REG_MISC_AB);
c375bcba MB	338
	339	tmp = channel_data->pwm_en_mask \| channel_data->clk_en_mask;
	340	state->enabled = (value & tmp) == tmp;
	341
	342	tmp = value >> channel_data->clk_div_shift;
	343	channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
	344
	345	value = readl(meson->base + channel_data->reg_offset);
	346
	347	channel->lo = FIELD_GET(PWM_LOW_MASK, value);
	348	channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
	349
	350	if (channel->lo == 0) {
	351	state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
	352	state->duty_cycle = state->period;
	353	} else if (channel->lo >= channel->hi) {
	354	state->period = meson_pwm_cnt_to_ns(chip, pwm,
	355	channel->lo + channel->hi);
	356	state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
	357	channel->hi);
	358	} else {
	359	state->period = 0;
	360	state->duty_cycle = 0;
	361	}
211ed630 NA	362	}
	363
	364	static const struct pwm_ops meson_pwm_ops = {
	365	.request = meson_pwm_request,
	366	.free = meson_pwm_free,
	367	.apply = meson_pwm_apply,
	368	.get_state = meson_pwm_get_state,
	369	.owner = THIS_MODULE,
	370	};
	371
	372	static const char * const pwm_meson8b_parent_names[] = {
	373	"xtal", "vid_pll", "fclk_div4", "fclk_div3"
	374	};
	375
	376	static const struct meson_pwm_data pwm_meson8b_data = {
	377	.parent_names = pwm_meson8b_parent_names,
d396b20a	378	.num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
211ed630 NA	379	};
	380
	381	static const char * const pwm_gxbb_parent_names[] = {
	382	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
	383	};
	384
	385	static const struct meson_pwm_data pwm_gxbb_data = {
	386	.parent_names = pwm_gxbb_parent_names,
d396b20a JB	387	.num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
	388	};
	389
	390	/*
	391	* Only the 2 first inputs of the GXBB AO PWMs are valid
	392	* The last 2 are grounded
	393	*/
	394	static const char * const pwm_gxbb_ao_parent_names[] = {
	395	"xtal", "clk81"
	396	};
	397
	398	static const struct meson_pwm_data pwm_gxbb_ao_data = {
	399	.parent_names = pwm_gxbb_ao_parent_names,
	400	.num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
211ed630 NA	401	};
211ed630 NA	402
bccaa3f9 JH	403	static const char * const pwm_axg_ee_parent_names[] = {
	404	"xtal", "fclk_div5", "fclk_div4", "fclk_div3"
	405	};
	406
	407	static const struct meson_pwm_data pwm_axg_ee_data = {
	408	.parent_names = pwm_axg_ee_parent_names,
	409	.num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
	410	};
	411
	412	static const char * const pwm_axg_ao_parent_names[] = {
	413	"aoclk81", "xtal", "fclk_div4", "fclk_div5"
	414	};
	415
	416	static const struct meson_pwm_data pwm_axg_ao_data = {
	417	.parent_names = pwm_axg_ao_parent_names,
	418	.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
	419	};
	420
9bce02ef NA	421	static const char * const pwm_g12a_ao_ab_parent_names[] = {
	422	"xtal", "aoclk81", "fclk_div4", "fclk_div5"
	423	};
	424
	425	static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
	426	.parent_names = pwm_g12a_ao_ab_parent_names,
	427	.num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
	428	};
	429
f41efceb	430	static const char * const pwm_g12a_ao_cd_parent_names[] = {
9bce02ef	431	"xtal", "aoclk81",
f41efceb NA	432	};
	433
	434	static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
	435	.parent_names = pwm_g12a_ao_cd_parent_names,
	436	.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
	437	};
	438
	439	static const char * const pwm_g12a_ee_parent_names[] = {
	440	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
	441	};
	442
	443	static const struct meson_pwm_data pwm_g12a_ee_data = {
	444	.parent_names = pwm_g12a_ee_parent_names,
	445	.num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
	446	};
	447
211ed630	448	static const struct of_device_id meson_pwm_matches[] = {
d396b20a JB	449	{
	450	.compatible = "amlogic,meson8b-pwm",
	451	.data = &pwm_meson8b_data
	452	},
	453	{
	454	.compatible = "amlogic,meson-gxbb-pwm",
	455	.data = &pwm_gxbb_data
	456	},
	457	{
	458	.compatible = "amlogic,meson-gxbb-ao-pwm",
	459	.data = &pwm_gxbb_ao_data
	460	},
bccaa3f9 JH	461	{
	462	.compatible = "amlogic,meson-axg-ee-pwm",
	463	.data = &pwm_axg_ee_data
	464	},
	465	{
	466	.compatible = "amlogic,meson-axg-ao-pwm",
	467	.data = &pwm_axg_ao_data
	468	},
f41efceb NA	469	{
	470	.compatible = "amlogic,meson-g12a-ee-pwm",
	471	.data = &pwm_g12a_ee_data
	472	},
	473	{
	474	.compatible = "amlogic,meson-g12a-ao-pwm-ab",
9bce02ef	475	.data = &pwm_g12a_ao_ab_data
f41efceb NA	476	},
	477	{
	478	.compatible = "amlogic,meson-g12a-ao-pwm-cd",
	479	.data = &pwm_g12a_ao_cd_data
	480	},
211ed630 NA	481	{},
	482	};
	483	MODULE_DEVICE_TABLE(of, meson_pwm_matches);
	484
a50a49a4	485	static int meson_pwm_init_channels(struct meson_pwm *meson)
211ed630 NA	486	{
211ed630 NA	487	struct device *dev = meson->chip.dev;
211ed630 NA	488	struct clk_init_data init;
	489	unsigned int i;
	490	char name[255];
	491	int err;
	492
	493	for (i = 0; i < meson->chip.npwm; i++) {
a50a49a4	494	struct meson_pwm_channel *channel = &meson->channels[i];
211ed630	495
b96e9eb6	496	snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
211ed630 NA	497
	498	init.name = name;
	499	init.ops = &clk_mux_ops;
90b6c5c7	500	init.flags = 0;
211ed630	501	init.parent_names = meson->data->parent_names;
d396b20a	502	init.num_parents = meson->data->num_parents;
211ed630 NA	503
211ed630 NA	504	channel->mux.reg = meson->base + REG_MISC_AB;
8bbf3164 MB	505	channel->mux.shift =
8bbf3164 MB	506	meson_pwm_per_channel_data[i].clk_sel_shift;
33cefd84	507	channel->mux.mask = MISC_CLK_SEL_MASK;
211ed630 NA	508	channel->mux.flags = 0;
	509	channel->mux.lock = &meson->lock;
	510	channel->mux.table = NULL;
	511	channel->mux.hw.init = &init;
	512
	513	channel->clk = devm_clk_register(dev, &channel->mux.hw);
	514	if (IS_ERR(channel->clk)) {
	515	err = PTR_ERR(channel->clk);
	516	dev_err(dev, "failed to register %s: %d\n", name, err);
	517	return err;
	518	}
	519
	520	snprintf(name, sizeof(name), "clkin%u", i);
	521
ba4004c7 MB	522	channel->clk_parent = devm_clk_get_optional(dev, name);
	523	if (IS_ERR(channel->clk_parent))
	524	return PTR_ERR(channel->clk_parent);
211ed630 NA	525	}
	526
	527	return 0;
	528	}
	529
211ed630 NA	530	static int meson_pwm_probe(struct platform_device *pdev)
211ed630 NA	531	{
211ed630	532	struct meson_pwm *meson;
211ed630 NA	533	int err;
	534
	535	meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
	536	if (!meson)
	537	return -ENOMEM;
	538
17076b10	539	meson->base = devm_platform_ioremap_resource(pdev, 0);
211ed630 NA	540	if (IS_ERR(meson->base))
	541	return PTR_ERR(meson->base);
	542
c6999956	543	spin_lock_init(&meson->lock);
211ed630 NA	544	meson->chip.dev = &pdev->dev;
211ed630 NA	545	meson->chip.ops = &meson_pwm_ops;
a50a49a4	546	meson->chip.npwm = MESON_NUM_PWMS;
211ed630 NA	547
211ed630 NA	548	meson->data = of_device_get_match_data(&pdev->dev);
211ed630	549
a50a49a4	550	err = meson_pwm_init_channels(meson);
211ed630 NA	551	if (err < 0)
	552	return err;
	553
f41227eb	554	err = devm_pwmchip_add(&pdev->dev, &meson->chip);
211ed630 NA	555	if (err < 0) {
	556	dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
	557	return err;
	558	}
	559
211ed630 NA	560	return 0;
	561	}
	562
211ed630 NA	563	static struct platform_driver meson_pwm_driver = {
	564	.driver = {
	565	.name = "meson-pwm",
	566	.of_match_table = meson_pwm_matches,
	567	},
	568	.probe = meson_pwm_probe,
211ed630 NA	569	};
	570	module_platform_driver(meson_pwm_driver);
	571
211ed630 NA	572	MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
	573	MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
	574	MODULE_LICENSE("Dual BSD/GPL");