[linux-block.git] / drivers / pwm / pwm-meson.c

// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
 * Copyright (c) 2016 BayLibre, SAS.
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 * Copyright (C) 2014 Amlogic, Inc.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define REG_PWM_A		0x0
#define REG_PWM_B		0x4
#define PWM_HIGH_SHIFT		16

#define REG_MISC_AB		0x8
#define MISC_B_CLK_EN		BIT(23)
#define MISC_A_CLK_EN		BIT(15)
#define MISC_CLK_DIV_MASK	0x7f
#define MISC_B_CLK_DIV_SHIFT	16
#define MISC_A_CLK_DIV_SHIFT	8
#define MISC_B_CLK_SEL_SHIFT	6
#define MISC_A_CLK_SEL_SHIFT	4
#define MISC_CLK_SEL_WIDTH	2
#define MISC_B_EN		BIT(1)
#define MISC_A_EN		BIT(0)

static const unsigned int mux_reg_shifts[] = {
	MISC_A_CLK_SEL_SHIFT,
	MISC_B_CLK_SEL_SHIFT
};

struct meson_pwm_channel {
	unsigned int hi;
	unsigned int lo;
	u8 pre_div;

	struct pwm_state state;

	struct clk *clk_parent;
	struct clk_mux mux;
	struct clk *clk;
};

struct meson_pwm_data {
	const char * const *parent_names;
	unsigned int num_parents;
};

struct meson_pwm {
	struct pwm_chip chip;
	const struct meson_pwm_data *data;
	void __iomem *base;
	u8 inverter_mask;
	/*
	 * Protects register (write) access to the REG_MISC_AB register
	 * that is shared between the two PWMs.
	 */
	spinlock_t lock;
};

static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct meson_pwm, chip);
}

static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
	struct device *dev = chip->dev;
	int err;

	if (!channel)
		return -ENODEV;

	if (channel->clk_parent) {
		err = clk_set_parent(channel->clk, channel->clk_parent);
		if (err < 0) {
			dev_err(dev, "failed to set parent %s for %s: %d\n",
				__clk_get_name(channel->clk_parent),
				__clk_get_name(channel->clk), err);
				return err;
		}
	}

	err = clk_prepare_enable(channel->clk);
	if (err < 0) {
		dev_err(dev, "failed to enable clock %s: %d\n",
			__clk_get_name(channel->clk), err);
		return err;
	}

	chip->ops->get_state(chip, pwm, &channel->state);

	return 0;
}

static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);

	if (channel)
		clk_disable_unprepare(channel->clk);
}

static int meson_pwm_calc(struct meson_pwm *meson,
			  struct meson_pwm_channel *channel, unsigned int id,
			  unsigned int duty, unsigned int period)
{
	unsigned int pre_div, cnt, duty_cnt;
	unsigned long fin_freq = -1;
	u64 fin_ps;

	if (~(meson->inverter_mask >> id) & 0x1)
		duty = period - duty;

	if (period == channel->state.period &&
	    duty == channel->state.duty_cycle)
		return 0;

	fin_freq = clk_get_rate(channel->clk);
	if (fin_freq == 0) {
		dev_err(meson->chip.dev, "invalid source clock frequency\n");
		return -EINVAL;
	}

	dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
	fin_ps = (u64)NSEC_PER_SEC * 1000;
	do_div(fin_ps, fin_freq);

	/* Calc pre_div with the period */
	for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
		cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
					    fin_ps * (pre_div + 1));
		dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
			fin_ps, pre_div, cnt);
		if (cnt <= 0xffff)
			break;
	}

	if (pre_div > MISC_CLK_DIV_MASK) {
		dev_err(meson->chip.dev, "unable to get period pre_div\n");
		return -EINVAL;
	}

	dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
		pre_div, cnt);

	if (duty == period) {
		channel->pre_div = pre_div;
		channel->hi = cnt;
		channel->lo = 0;
	} else if (duty == 0) {
		channel->pre_div = pre_div;
		channel->hi = 0;
		channel->lo = cnt;
	} else {
		/* Then check is we can have the duty with the same pre_div */
		duty_cnt = DIV_ROUND_CLOSEST_ULL((u64)duty * 1000,
						 fin_ps * (pre_div + 1));
		if (duty_cnt > 0xffff) {
			dev_err(meson->chip.dev, "unable to get duty cycle\n");
			return -EINVAL;
		}

		dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
			duty, pre_div, duty_cnt);

		channel->pre_div = pre_div;
		channel->hi = duty_cnt;
		channel->lo = cnt - duty_cnt;
	}

	return 0;
}

static void meson_pwm_enable(struct meson_pwm *meson,
			     struct meson_pwm_channel *channel,
			     unsigned int id)
{
	u32 value, clk_shift, clk_enable, enable;
	unsigned int offset;
	unsigned long flags;

	switch (id) {
	case 0:
		clk_shift = MISC_A_CLK_DIV_SHIFT;
		clk_enable = MISC_A_CLK_EN;
		enable = MISC_A_EN;
		offset = REG_PWM_A;
		break;

	case 1:
		clk_shift = MISC_B_CLK_DIV_SHIFT;
		clk_enable = MISC_B_CLK_EN;
		enable = MISC_B_EN;
		offset = REG_PWM_B;
		break;

	default:
		return;
	}

	spin_lock_irqsave(&meson->lock, flags);

	value = readl(meson->base + REG_MISC_AB);
	value &= ~(MISC_CLK_DIV_MASK << clk_shift);
	value |= channel->pre_div << clk_shift;
	value |= clk_enable;
	writel(value, meson->base + REG_MISC_AB);

	value = (channel->hi << PWM_HIGH_SHIFT) | channel->lo;
	writel(value, meson->base + offset);

	value = readl(meson->base + REG_MISC_AB);
	value |= enable;
	writel(value, meson->base + REG_MISC_AB);

	spin_unlock_irqrestore(&meson->lock, flags);
}

static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id)
{
	u32 value, enable;
	unsigned long flags;

	switch (id) {
	case 0:
		enable = MISC_A_EN;
		break;

	case 1:
		enable = MISC_B_EN;
		break;

	default:
		return;
	}

	spin_lock_irqsave(&meson->lock, flags);

	value = readl(meson->base + REG_MISC_AB);
	value &= ~enable;
	writel(value, meson->base + REG_MISC_AB);

	spin_unlock_irqrestore(&meson->lock, flags);
}

static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   struct pwm_state *state)
{
	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
	struct meson_pwm *meson = to_meson_pwm(chip);
	int err = 0;

	if (!state)
		return -EINVAL;

	if (!state->enabled) {
		meson_pwm_disable(meson, pwm->hwpwm);
		channel->state.enabled = false;

		return 0;
	}

	if (state->period != channel->state.period ||
	    state->duty_cycle != channel->state.duty_cycle ||
	    state->polarity != channel->state.polarity) {
		if (state->polarity != channel->state.polarity) {
			if (state->polarity == PWM_POLARITY_NORMAL)
				meson->inverter_mask |= BIT(pwm->hwpwm);
			else
				meson->inverter_mask &= ~BIT(pwm->hwpwm);
		}

		err = meson_pwm_calc(meson, channel, pwm->hwpwm,
				     state->duty_cycle, state->period);
		if (err < 0)
			return err;

		channel->state.polarity = state->polarity;
		channel->state.period = state->period;
		channel->state.duty_cycle = state->duty_cycle;
	}

	if (state->enabled && !channel->state.enabled) {
		meson_pwm_enable(meson, channel, pwm->hwpwm);
		channel->state.enabled = true;
	}

	return 0;
}

static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				struct pwm_state *state)
{
	struct meson_pwm *meson = to_meson_pwm(chip);
	u32 value, mask;

	if (!state)
		return;

	switch (pwm->hwpwm) {
	case 0:
		mask = MISC_A_EN;
		break;

	case 1:
		mask = MISC_B_EN;
		break;

	default:
		return;
	}

	value = readl(meson->base + REG_MISC_AB);
	state->enabled = (value & mask) != 0;
}

static const struct pwm_ops meson_pwm_ops = {
	.request = meson_pwm_request,
	.free = meson_pwm_free,
	.apply = meson_pwm_apply,
	.get_state = meson_pwm_get_state,
	.owner = THIS_MODULE,
};

static const char * const pwm_meson8b_parent_names[] = {
	"xtal", "vid_pll", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_meson8b_data = {
	.parent_names = pwm_meson8b_parent_names,
	.num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
};

static const char * const pwm_gxbb_parent_names[] = {
	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_gxbb_data = {
	.parent_names = pwm_gxbb_parent_names,
	.num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
};

/*
 * Only the 2 first inputs of the GXBB AO PWMs are valid
 * The last 2 are grounded
 */
static const char * const pwm_gxbb_ao_parent_names[] = {
	"xtal", "clk81"
};

static const struct meson_pwm_data pwm_gxbb_ao_data = {
	.parent_names = pwm_gxbb_ao_parent_names,
	.num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
};

static const char * const pwm_axg_ee_parent_names[] = {
	"xtal", "fclk_div5", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_axg_ee_data = {
	.parent_names = pwm_axg_ee_parent_names,
	.num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
};

static const char * const pwm_axg_ao_parent_names[] = {
	"aoclk81", "xtal", "fclk_div4", "fclk_div5"
};

static const struct meson_pwm_data pwm_axg_ao_data = {
	.parent_names = pwm_axg_ao_parent_names,
	.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
};

static const char * const pwm_g12a_ao_ab_parent_names[] = {
	"xtal", "aoclk81", "fclk_div4", "fclk_div5"
};

static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
	.parent_names = pwm_g12a_ao_ab_parent_names,
	.num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
};

static const char * const pwm_g12a_ao_cd_parent_names[] = {
	"xtal", "aoclk81",
};

static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
	.parent_names = pwm_g12a_ao_cd_parent_names,
	.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
};

static const char * const pwm_g12a_ee_parent_names[] = {
	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_g12a_ee_data = {
	.parent_names = pwm_g12a_ee_parent_names,
	.num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
};

static const struct of_device_id meson_pwm_matches[] = {
	{
		.compatible = "amlogic,meson8b-pwm",
		.data = &pwm_meson8b_data
	},
	{
		.compatible = "amlogic,meson-gxbb-pwm",
		.data = &pwm_gxbb_data
	},
	{
		.compatible = "amlogic,meson-gxbb-ao-pwm",
		.data = &pwm_gxbb_ao_data
	},
	{
		.compatible = "amlogic,meson-axg-ee-pwm",
		.data = &pwm_axg_ee_data
	},
	{
		.compatible = "amlogic,meson-axg-ao-pwm",
		.data = &pwm_axg_ao_data
	},
	{
		.compatible = "amlogic,meson-g12a-ee-pwm",
		.data = &pwm_g12a_ee_data
	},
	{
		.compatible = "amlogic,meson-g12a-ao-pwm-ab",
		.data = &pwm_g12a_ao_ab_data
	},
	{
		.compatible = "amlogic,meson-g12a-ao-pwm-cd",
		.data = &pwm_g12a_ao_cd_data
	},
	{},
};
MODULE_DEVICE_TABLE(of, meson_pwm_matches);

static int meson_pwm_init_channels(struct meson_pwm *meson,
				   struct meson_pwm_channel *channels)
{
	struct device *dev = meson->chip.dev;
	struct clk_init_data init;
	unsigned int i;
	char name[255];
	int err;

	for (i = 0; i < meson->chip.npwm; i++) {
		struct meson_pwm_channel *channel = &channels[i];

		snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);

		init.name = name;
		init.ops = &clk_mux_ops;
		init.flags = 0;
		init.parent_names = meson->data->parent_names;
		init.num_parents = meson->data->num_parents;

		channel->mux.reg = meson->base + REG_MISC_AB;
		channel->mux.shift = mux_reg_shifts[i];
		channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1;
		channel->mux.flags = 0;
		channel->mux.lock = &meson->lock;
		channel->mux.table = NULL;
		channel->mux.hw.init = &init;

		channel->clk = devm_clk_register(dev, &channel->mux.hw);
		if (IS_ERR(channel->clk)) {
			err = PTR_ERR(channel->clk);
			dev_err(dev, "failed to register %s: %d\n", name, err);
			return err;
		}

		snprintf(name, sizeof(name), "clkin%u", i);

		channel->clk_parent = devm_clk_get(dev, name);
		if (IS_ERR(channel->clk_parent)) {
			err = PTR_ERR(channel->clk_parent);
			if (err == -EPROBE_DEFER)
				return err;

			channel->clk_parent = NULL;
		}
	}

	return 0;
}

static void meson_pwm_add_channels(struct meson_pwm *meson,
				   struct meson_pwm_channel *channels)
{
	unsigned int i;

	for (i = 0; i < meson->chip.npwm; i++)
		pwm_set_chip_data(&meson->chip.pwms[i], &channels[i]);
}

static int meson_pwm_probe(struct platform_device *pdev)
{
	struct meson_pwm_channel *channels;
	struct meson_pwm *meson;
	struct resource *regs;
	int err;

	meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
	if (!meson)
		return -ENOMEM;

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	meson->base = devm_ioremap_resource(&pdev->dev, regs);
	if (IS_ERR(meson->base))
		return PTR_ERR(meson->base);

	spin_lock_init(&meson->lock);
	meson->chip.dev = &pdev->dev;
	meson->chip.ops = &meson_pwm_ops;
	meson->chip.base = -1;
	meson->chip.npwm = 2;
	meson->chip.of_xlate = of_pwm_xlate_with_flags;
	meson->chip.of_pwm_n_cells = 3;

	meson->data = of_device_get_match_data(&pdev->dev);
	meson->inverter_mask = BIT(meson->chip.npwm) - 1;

	channels = devm_kcalloc(&pdev->dev, meson->chip.npwm,
				sizeof(*channels), GFP_KERNEL);
	if (!channels)
		return -ENOMEM;

	err = meson_pwm_init_channels(meson, channels);
	if (err < 0)
		return err;

	err = pwmchip_add(&meson->chip);
	if (err < 0) {
		dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
		return err;
	}

	meson_pwm_add_channels(meson, channels);

	platform_set_drvdata(pdev, meson);

	return 0;
}

static int meson_pwm_remove(struct platform_device *pdev)
{
	struct meson_pwm *meson = platform_get_drvdata(pdev);

	return pwmchip_remove(&meson->chip);
}

static struct platform_driver meson_pwm_driver = {
	.driver = {
		.name = "meson-pwm",
		.of_match_table = meson_pwm_matches,
	},
	.probe = meson_pwm_probe,
	.remove = meson_pwm_remove,
};
module_platform_driver(meson_pwm_driver);

MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_LICENSE("Dual BSD/GPL");
Commit	Line	Data
1cdb4413	1	// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
211ed630	2	/*
211ed630 NA	3	* Copyright (c) 2016 BayLibre, SAS.
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	* Copyright (C) 2014 Amlogic, Inc.
211ed630 NA	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/clk-provider.h>
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
	15	#include <linux/of_device.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/pwm.h>
	18	#include <linux/slab.h>
	19	#include <linux/spinlock.h>
	20
	21	#define REG_PWM_A 0x0
	22	#define REG_PWM_B 0x4
	23	#define PWM_HIGH_SHIFT 16
	24
	25	#define REG_MISC_AB 0x8
	26	#define MISC_B_CLK_EN BIT(23)
	27	#define MISC_A_CLK_EN BIT(15)
	28	#define MISC_CLK_DIV_MASK 0x7f
	29	#define MISC_B_CLK_DIV_SHIFT 16
	30	#define MISC_A_CLK_DIV_SHIFT 8
	31	#define MISC_B_CLK_SEL_SHIFT 6
	32	#define MISC_A_CLK_SEL_SHIFT 4
	33	#define MISC_CLK_SEL_WIDTH 2
	34	#define MISC_B_EN BIT(1)
	35	#define MISC_A_EN BIT(0)
	36
	37	static const unsigned int mux_reg_shifts[] = {
	38	MISC_A_CLK_SEL_SHIFT,
	39	MISC_B_CLK_SEL_SHIFT
	40	};
	41
	42	struct meson_pwm_channel {
	43	unsigned int hi;
	44	unsigned int lo;
	45	u8 pre_div;
	46
	47	struct pwm_state state;
	48
	49	struct clk *clk_parent;
	50	struct clk_mux mux;
	51	struct clk *clk;
	52	};
	53
	54	struct meson_pwm_data {
	55	const char * const *parent_names;
d396b20a	56	unsigned int num_parents;
211ed630 NA	57	};
	58
	59	struct meson_pwm {
	60	struct pwm_chip chip;
	61	const struct meson_pwm_data *data;
	62	void __iomem *base;
	63	u8 inverter_mask;
f173747f MB	64	/*
	65	* Protects register (write) access to the REG_MISC_AB register
	66	* that is shared between the two PWMs.
	67	*/
211ed630 NA	68	spinlock_t lock;
	69	};
	70
	71	static inline struct meson_pwm to_meson_pwm(struct pwm_chip chip)
	72	{
	73	return container_of(chip, struct meson_pwm, chip);
	74	}
	75
	76	static int meson_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	77	{
	78	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
	79	struct device *dev = chip->dev;
	80	int err;
	81
	82	if (!channel)
	83	return -ENODEV;
	84
	85	if (channel->clk_parent) {
	86	err = clk_set_parent(channel->clk, channel->clk_parent);
	87	if (err < 0) {
	88	dev_err(dev, "failed to set parent %s for %s: %d\n",
	89	__clk_get_name(channel->clk_parent),
	90	__clk_get_name(channel->clk), err);
	91	return err;
	92	}
	93	}
	94
	95	err = clk_prepare_enable(channel->clk);
	96	if (err < 0) {
	97	dev_err(dev, "failed to enable clock %s: %d\n",
	98	__clk_get_name(channel->clk), err);
	99	return err;
	100	}
	101
	102	chip->ops->get_state(chip, pwm, &channel->state);
	103
	104	return 0;
	105	}
	106
	107	static void meson_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	108	{
	109	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
	110
	111	if (channel)
	112	clk_disable_unprepare(channel->clk);
	113	}
	114
	115	static int meson_pwm_calc(struct meson_pwm *meson,
	116	struct meson_pwm_channel *channel, unsigned int id,
	117	unsigned int duty, unsigned int period)
	118	{
	119	unsigned int pre_div, cnt, duty_cnt;
fd7b2be8 JB	120	unsigned long fin_freq = -1;
fd7b2be8 JB	121	u64 fin_ps;
211ed630 NA	122
	123	if (~(meson->inverter_mask >> id) & 0x1)
	124	duty = period - duty;
	125
	126	if (period == channel->state.period &&
	127	duty == channel->state.duty_cycle)
	128	return 0;
	129
	130	fin_freq = clk_get_rate(channel->clk);
	131	if (fin_freq == 0) {
	132	dev_err(meson->chip.dev, "invalid source clock frequency\n");
	133	return -EINVAL;
	134	}
	135
	136	dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
fd7b2be8 JB	137	fin_ps = (u64)NSEC_PER_SEC * 1000;
fd7b2be8 JB	138	do_div(fin_ps, fin_freq);
211ed630 NA	139
211ed630 NA	140	/* Calc pre_div with the period */
51496e44	141	for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
fd7b2be8 JB	142	cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
	143	fin_ps * (pre_div + 1));
	144	dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
	145	fin_ps, pre_div, cnt);
211ed630 NA	146	if (cnt <= 0xffff)
	147	break;
	148	}
	149
51496e44	150	if (pre_div > MISC_CLK_DIV_MASK) {
211ed630 NA	151	dev_err(meson->chip.dev, "unable to get period pre_div\n");
	152	return -EINVAL;
	153	}
	154
	155	dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
	156	pre_div, cnt);
	157
	158	if (duty == period) {
	159	channel->pre_div = pre_div;
	160	channel->hi = cnt;
	161	channel->lo = 0;
	162	} else if (duty == 0) {
	163	channel->pre_div = pre_div;
	164	channel->hi = 0;
	165	channel->lo = cnt;
	166	} else {
	167	/* Then check is we can have the duty with the same pre_div */
fd7b2be8 JB	168	duty_cnt = DIV_ROUND_CLOSEST_ULL((u64)duty * 1000,
fd7b2be8 JB	169	fin_ps * (pre_div + 1));
211ed630 NA	170	if (duty_cnt > 0xffff) {
	171	dev_err(meson->chip.dev, "unable to get duty cycle\n");
	172	return -EINVAL;
	173	}
	174
	175	dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
	176	duty, pre_div, duty_cnt);
	177
	178	channel->pre_div = pre_div;
	179	channel->hi = duty_cnt;
	180	channel->lo = cnt - duty_cnt;
	181	}
	182
	183	return 0;
	184	}
	185
	186	static void meson_pwm_enable(struct meson_pwm *meson,
	187	struct meson_pwm_channel *channel,
	188	unsigned int id)
	189	{
	190	u32 value, clk_shift, clk_enable, enable;
	191	unsigned int offset;
f173747f	192	unsigned long flags;
211ed630 NA	193
	194	switch (id) {
	195	case 0:
	196	clk_shift = MISC_A_CLK_DIV_SHIFT;
	197	clk_enable = MISC_A_CLK_EN;
	198	enable = MISC_A_EN;
	199	offset = REG_PWM_A;
	200	break;
	201
	202	case 1:
	203	clk_shift = MISC_B_CLK_DIV_SHIFT;
	204	clk_enable = MISC_B_CLK_EN;
	205	enable = MISC_B_EN;
	206	offset = REG_PWM_B;
	207	break;
2fbc487d AB	208
	209	default:
	210	return;
211ed630 NA	211	}
211ed630 NA	212
f173747f MB	213	spin_lock_irqsave(&meson->lock, flags);
f173747f MB	214
211ed630 NA	215	value = readl(meson->base + REG_MISC_AB);
	216	value &= ~(MISC_CLK_DIV_MASK << clk_shift);
	217	value \|= channel->pre_div << clk_shift;
	218	value \|= clk_enable;
	219	writel(value, meson->base + REG_MISC_AB);
	220
	221	value = (channel->hi << PWM_HIGH_SHIFT) \| channel->lo;
	222	writel(value, meson->base + offset);
	223
	224	value = readl(meson->base + REG_MISC_AB);
	225	value \|= enable;
	226	writel(value, meson->base + REG_MISC_AB);
f173747f MB	227
f173747f MB	228	spin_unlock_irqrestore(&meson->lock, flags);
211ed630 NA	229	}
	230
	231	static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id)
	232	{
	233	u32 value, enable;
f173747f	234	unsigned long flags;
211ed630 NA	235
	236	switch (id) {
	237	case 0:
	238	enable = MISC_A_EN;
	239	break;
	240
	241	case 1:
	242	enable = MISC_B_EN;
	243	break;
2fbc487d AB	244
	245	default:
	246	return;
211ed630 NA	247	}
211ed630 NA	248
f173747f MB	249	spin_lock_irqsave(&meson->lock, flags);
f173747f MB	250
211ed630 NA	251	value = readl(meson->base + REG_MISC_AB);
	252	value &= ~enable;
	253	writel(value, meson->base + REG_MISC_AB);
f173747f MB	254
f173747f MB	255	spin_unlock_irqrestore(&meson->lock, flags);
211ed630 NA	256	}
	257
	258	static int meson_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	259	struct pwm_state *state)
	260	{
	261	struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
	262	struct meson_pwm *meson = to_meson_pwm(chip);
211ed630 NA	263	int err = 0;
	264
	265	if (!state)
	266	return -EINVAL;
	267
211ed630 NA	268	if (!state->enabled) {
	269	meson_pwm_disable(meson, pwm->hwpwm);
	270	channel->state.enabled = false;
	271
f173747f	272	return 0;
211ed630 NA	273	}
	274
	275	if (state->period != channel->state.period \|\|
	276	state->duty_cycle != channel->state.duty_cycle \|\|
	277	state->polarity != channel->state.polarity) {
211ed630 NA	278	if (state->polarity != channel->state.polarity) {
	279	if (state->polarity == PWM_POLARITY_NORMAL)
	280	meson->inverter_mask \|= BIT(pwm->hwpwm);
	281	else
	282	meson->inverter_mask &= ~BIT(pwm->hwpwm);
	283	}
	284
	285	err = meson_pwm_calc(meson, channel, pwm->hwpwm,
	286	state->duty_cycle, state->period);
	287	if (err < 0)
f173747f	288	return err;
211ed630 NA	289
	290	channel->state.polarity = state->polarity;
	291	channel->state.period = state->period;
	292	channel->state.duty_cycle = state->duty_cycle;
	293	}
	294
	295	if (state->enabled && !channel->state.enabled) {
	296	meson_pwm_enable(meson, channel, pwm->hwpwm);
	297	channel->state.enabled = true;
	298	}
	299
f173747f	300	return 0;
211ed630 NA	301	}
	302
	303	static void meson_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
	304	struct pwm_state *state)
	305	{
	306	struct meson_pwm *meson = to_meson_pwm(chip);
	307	u32 value, mask;
	308
	309	if (!state)
	310	return;
	311
	312	switch (pwm->hwpwm) {
	313	case 0:
	314	mask = MISC_A_EN;
	315	break;
	316
	317	case 1:
	318	mask = MISC_B_EN;
	319	break;
2fbc487d AB	320
	321	default:
	322	return;
211ed630 NA	323	}
	324
	325	value = readl(meson->base + REG_MISC_AB);
	326	state->enabled = (value & mask) != 0;
	327	}
	328
	329	static const struct pwm_ops meson_pwm_ops = {
	330	.request = meson_pwm_request,
	331	.free = meson_pwm_free,
	332	.apply = meson_pwm_apply,
	333	.get_state = meson_pwm_get_state,
	334	.owner = THIS_MODULE,
	335	};
	336
	337	static const char * const pwm_meson8b_parent_names[] = {
	338	"xtal", "vid_pll", "fclk_div4", "fclk_div3"
	339	};
	340
	341	static const struct meson_pwm_data pwm_meson8b_data = {
	342	.parent_names = pwm_meson8b_parent_names,
d396b20a	343	.num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
211ed630 NA	344	};
	345
	346	static const char * const pwm_gxbb_parent_names[] = {
	347	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
	348	};
	349
	350	static const struct meson_pwm_data pwm_gxbb_data = {
	351	.parent_names = pwm_gxbb_parent_names,
d396b20a JB	352	.num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
	353	};
	354
	355	/*
	356	* Only the 2 first inputs of the GXBB AO PWMs are valid
	357	* The last 2 are grounded
	358	*/
	359	static const char * const pwm_gxbb_ao_parent_names[] = {
	360	"xtal", "clk81"
	361	};
	362
	363	static const struct meson_pwm_data pwm_gxbb_ao_data = {
	364	.parent_names = pwm_gxbb_ao_parent_names,
	365	.num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
211ed630 NA	366	};
211ed630 NA	367
bccaa3f9 JH	368	static const char * const pwm_axg_ee_parent_names[] = {
	369	"xtal", "fclk_div5", "fclk_div4", "fclk_div3"
	370	};
	371
	372	static const struct meson_pwm_data pwm_axg_ee_data = {
	373	.parent_names = pwm_axg_ee_parent_names,
	374	.num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
	375	};
	376
	377	static const char * const pwm_axg_ao_parent_names[] = {
	378	"aoclk81", "xtal", "fclk_div4", "fclk_div5"
	379	};
	380
	381	static const struct meson_pwm_data pwm_axg_ao_data = {
	382	.parent_names = pwm_axg_ao_parent_names,
	383	.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
	384	};
	385
9bce02ef NA	386	static const char * const pwm_g12a_ao_ab_parent_names[] = {
	387	"xtal", "aoclk81", "fclk_div4", "fclk_div5"
	388	};
	389
	390	static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
	391	.parent_names = pwm_g12a_ao_ab_parent_names,
	392	.num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
	393	};
	394
f41efceb	395	static const char * const pwm_g12a_ao_cd_parent_names[] = {
9bce02ef	396	"xtal", "aoclk81",
f41efceb NA	397	};
	398
	399	static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
	400	.parent_names = pwm_g12a_ao_cd_parent_names,
	401	.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
	402	};
	403
	404	static const char * const pwm_g12a_ee_parent_names[] = {
	405	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
	406	};
	407
	408	static const struct meson_pwm_data pwm_g12a_ee_data = {
	409	.parent_names = pwm_g12a_ee_parent_names,
	410	.num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
	411	};
	412
211ed630	413	static const struct of_device_id meson_pwm_matches[] = {
d396b20a JB	414	{
	415	.compatible = "amlogic,meson8b-pwm",
	416	.data = &pwm_meson8b_data
	417	},
	418	{
	419	.compatible = "amlogic,meson-gxbb-pwm",
	420	.data = &pwm_gxbb_data
	421	},
	422	{
	423	.compatible = "amlogic,meson-gxbb-ao-pwm",
	424	.data = &pwm_gxbb_ao_data
	425	},
bccaa3f9 JH	426	{
	427	.compatible = "amlogic,meson-axg-ee-pwm",
	428	.data = &pwm_axg_ee_data
	429	},
	430	{
	431	.compatible = "amlogic,meson-axg-ao-pwm",
	432	.data = &pwm_axg_ao_data
	433	},
f41efceb NA	434	{
	435	.compatible = "amlogic,meson-g12a-ee-pwm",
	436	.data = &pwm_g12a_ee_data
	437	},
	438	{
	439	.compatible = "amlogic,meson-g12a-ao-pwm-ab",
9bce02ef	440	.data = &pwm_g12a_ao_ab_data
f41efceb NA	441	},
	442	{
	443	.compatible = "amlogic,meson-g12a-ao-pwm-cd",
	444	.data = &pwm_g12a_ao_cd_data
	445	},
211ed630 NA	446	{},
	447	};
	448	MODULE_DEVICE_TABLE(of, meson_pwm_matches);
	449
	450	static int meson_pwm_init_channels(struct meson_pwm *meson,
	451	struct meson_pwm_channel *channels)
	452	{
	453	struct device *dev = meson->chip.dev;
211ed630 NA	454	struct clk_init_data init;
	455	unsigned int i;
	456	char name[255];
	457	int err;
	458
	459	for (i = 0; i < meson->chip.npwm; i++) {
	460	struct meson_pwm_channel *channel = &channels[i];
	461
b96e9eb6	462	snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
211ed630 NA	463
	464	init.name = name;
	465	init.ops = &clk_mux_ops;
90b6c5c7	466	init.flags = 0;
211ed630	467	init.parent_names = meson->data->parent_names;
d396b20a	468	init.num_parents = meson->data->num_parents;
211ed630 NA	469
	470	channel->mux.reg = meson->base + REG_MISC_AB;
	471	channel->mux.shift = mux_reg_shifts[i];
	472	channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1;
	473	channel->mux.flags = 0;
	474	channel->mux.lock = &meson->lock;
	475	channel->mux.table = NULL;
	476	channel->mux.hw.init = &init;
	477
	478	channel->clk = devm_clk_register(dev, &channel->mux.hw);
	479	if (IS_ERR(channel->clk)) {
	480	err = PTR_ERR(channel->clk);
	481	dev_err(dev, "failed to register %s: %d\n", name, err);
	482	return err;
	483	}
	484
	485	snprintf(name, sizeof(name), "clkin%u", i);
	486
	487	channel->clk_parent = devm_clk_get(dev, name);
	488	if (IS_ERR(channel->clk_parent)) {
	489	err = PTR_ERR(channel->clk_parent);
	490	if (err == -EPROBE_DEFER)
	491	return err;
	492
	493	channel->clk_parent = NULL;
	494	}
	495	}
	496
	497	return 0;
	498	}
	499
	500	static void meson_pwm_add_channels(struct meson_pwm *meson,
	501	struct meson_pwm_channel *channels)
	502	{
	503	unsigned int i;
	504
	505	for (i = 0; i < meson->chip.npwm; i++)
	506	pwm_set_chip_data(&meson->chip.pwms[i], &channels[i]);
	507	}
	508
	509	static int meson_pwm_probe(struct platform_device *pdev)
	510	{
	511	struct meson_pwm_channel *channels;
	512	struct meson_pwm *meson;
	513	struct resource *regs;
	514	int err;
	515
	516	meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
	517	if (!meson)
	518	return -ENOMEM;
	519
	520	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	521	meson->base = devm_ioremap_resource(&pdev->dev, regs);
	522	if (IS_ERR(meson->base))
	523	return PTR_ERR(meson->base);
	524
c6999956	525	spin_lock_init(&meson->lock);
211ed630 NA	526	meson->chip.dev = &pdev->dev;
	527	meson->chip.ops = &meson_pwm_ops;
	528	meson->chip.base = -1;
	529	meson->chip.npwm = 2;
	530	meson->chip.of_xlate = of_pwm_xlate_with_flags;
	531	meson->chip.of_pwm_n_cells = 3;
	532
	533	meson->data = of_device_get_match_data(&pdev->dev);
	534	meson->inverter_mask = BIT(meson->chip.npwm) - 1;
	535
735596ca MB	536	channels = devm_kcalloc(&pdev->dev, meson->chip.npwm,
735596ca MB	537	sizeof(*channels), GFP_KERNEL);
211ed630 NA	538	if (!channels)
	539	return -ENOMEM;
	540
	541	err = meson_pwm_init_channels(meson, channels);
	542	if (err < 0)
	543	return err;
	544
	545	err = pwmchip_add(&meson->chip);
	546	if (err < 0) {
	547	dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
	548	return err;
	549	}
	550
	551	meson_pwm_add_channels(meson, channels);
	552
	553	platform_set_drvdata(pdev, meson);
	554
	555	return 0;
	556	}
	557
	558	static int meson_pwm_remove(struct platform_device *pdev)
	559	{
	560	struct meson_pwm *meson = platform_get_drvdata(pdev);
	561
	562	return pwmchip_remove(&meson->chip);
	563	}
	564
	565	static struct platform_driver meson_pwm_driver = {
	566	.driver = {
	567	.name = "meson-pwm",
	568	.of_match_table = meson_pwm_matches,
	569	},
	570	.probe = meson_pwm_probe,
	571	.remove = meson_pwm_remove,
	572	};
	573	module_platform_driver(meson_pwm_driver);
	574
211ed630 NA	575	MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
	576	MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
	577	MODULE_LICENSE("Dual BSD/GPL");