Commit | Line | Data |
---|---|---|
1cdb4413 | 1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
211ed630 | 2 | /* |
4ae42ce7 MB |
3 | * PWM controller driver for Amlogic Meson SoCs. |
4 | * | |
5 | * This PWM is only a set of Gates, Dividers and Counters: | |
6 | * PWM output is achieved by calculating a clock that permits calculating | |
7 | * two periods (low and high). The counter then has to be set to switch after | |
8 | * N cycles for the first half period. | |
9 | * The hardware has no "polarity" setting. This driver reverses the period | |
10 | * cycles (the low length is inverted with the high length) for | |
11 | * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity | |
12 | * from the hardware. | |
13 | * Setting the duty cycle will disable and re-enable the PWM output. | |
14 | * Disabling the PWM stops the output immediately (without waiting for the | |
15 | * current period to complete first). | |
16 | * | |
17 | * The public S912 (GXM) datasheet contains some documentation for this PWM | |
18 | * controller starting on page 543: | |
19 | * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf | |
20 | * An updated version of this IP block is found in S922X (G12B) SoCs. The | |
21 | * datasheet contains the description for this IP block revision starting at | |
22 | * page 1084: | |
23 | * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf | |
24 | * | |
211ed630 NA |
25 | * Copyright (c) 2016 BayLibre, SAS. |
26 | * Author: Neil Armstrong <narmstrong@baylibre.com> | |
27 | * Copyright (C) 2014 Amlogic, Inc. | |
211ed630 NA |
28 | */ |
29 | ||
181164b6 MB |
30 | #include <linux/bitfield.h> |
31 | #include <linux/bits.h> | |
211ed630 NA |
32 | #include <linux/clk.h> |
33 | #include <linux/clk-provider.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/kernel.h> | |
fb2081e8 | 37 | #include <linux/math64.h> |
211ed630 NA |
38 | #include <linux/module.h> |
39 | #include <linux/of.h> | |
211ed630 NA |
40 | #include <linux/platform_device.h> |
41 | #include <linux/pwm.h> | |
42 | #include <linux/slab.h> | |
43 | #include <linux/spinlock.h> | |
44 | ||
45 | #define REG_PWM_A 0x0 | |
46 | #define REG_PWM_B 0x4 | |
181164b6 MB |
47 | #define PWM_LOW_MASK GENMASK(15, 0) |
48 | #define PWM_HIGH_MASK GENMASK(31, 16) | |
211ed630 NA |
49 | |
50 | #define REG_MISC_AB 0x8 | |
329db102 HK |
51 | #define MISC_B_CLK_EN_SHIFT 23 |
52 | #define MISC_A_CLK_EN_SHIFT 15 | |
53 | #define MISC_CLK_DIV_WIDTH 7 | |
211ed630 NA |
54 | #define MISC_B_CLK_DIV_SHIFT 16 |
55 | #define MISC_A_CLK_DIV_SHIFT 8 | |
56 | #define MISC_B_CLK_SEL_SHIFT 6 | |
57 | #define MISC_A_CLK_SEL_SHIFT 4 | |
33cefd84 | 58 | #define MISC_CLK_SEL_MASK 0x3 |
211ed630 NA |
59 | #define MISC_B_EN BIT(1) |
60 | #define MISC_A_EN BIT(0) | |
61 | ||
a50a49a4 | 62 | #define MESON_NUM_PWMS 2 |
f2cea1dc | 63 | #define MESON_NUM_MUX_PARENTS 4 |
a50a49a4 | 64 | |
8bbf3164 MB |
65 | static struct meson_pwm_channel_data { |
66 | u8 reg_offset; | |
67 | u8 clk_sel_shift; | |
68 | u8 clk_div_shift; | |
329db102 | 69 | u8 clk_en_shift; |
8bbf3164 MB |
70 | u32 pwm_en_mask; |
71 | } meson_pwm_per_channel_data[MESON_NUM_PWMS] = { | |
72 | { | |
73 | .reg_offset = REG_PWM_A, | |
74 | .clk_sel_shift = MISC_A_CLK_SEL_SHIFT, | |
75 | .clk_div_shift = MISC_A_CLK_DIV_SHIFT, | |
329db102 | 76 | .clk_en_shift = MISC_A_CLK_EN_SHIFT, |
8bbf3164 MB |
77 | .pwm_en_mask = MISC_A_EN, |
78 | }, | |
79 | { | |
80 | .reg_offset = REG_PWM_B, | |
81 | .clk_sel_shift = MISC_B_CLK_SEL_SHIFT, | |
82 | .clk_div_shift = MISC_B_CLK_DIV_SHIFT, | |
329db102 | 83 | .clk_en_shift = MISC_B_CLK_EN_SHIFT, |
8bbf3164 MB |
84 | .pwm_en_mask = MISC_B_EN, |
85 | } | |
211ed630 NA |
86 | }; |
87 | ||
88 | struct meson_pwm_channel { | |
329db102 | 89 | unsigned long rate; |
211ed630 NA |
90 | unsigned int hi; |
91 | unsigned int lo; | |
211ed630 | 92 | |
211ed630 | 93 | struct clk_mux mux; |
329db102 HK |
94 | struct clk_divider div; |
95 | struct clk_gate gate; | |
211ed630 NA |
96 | struct clk *clk; |
97 | }; | |
98 | ||
99 | struct meson_pwm_data { | |
f2cea1dc | 100 | const char *const parent_names[MESON_NUM_MUX_PARENTS]; |
1031c2b4 | 101 | int (*channels_init)(struct pwm_chip *chip); |
211ed630 NA |
102 | }; |
103 | ||
104 | struct meson_pwm { | |
211ed630 | 105 | const struct meson_pwm_data *data; |
a50a49a4 | 106 | struct meson_pwm_channel channels[MESON_NUM_PWMS]; |
211ed630 | 107 | void __iomem *base; |
f173747f MB |
108 | /* |
109 | * Protects register (write) access to the REG_MISC_AB register | |
110 | * that is shared between the two PWMs. | |
111 | */ | |
211ed630 NA |
112 | spinlock_t lock; |
113 | }; | |
114 | ||
115 | static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip) | |
116 | { | |
28ecf9bd | 117 | return pwmchip_get_drvdata(chip); |
211ed630 NA |
118 | } |
119 | ||
120 | static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) | |
121 | { | |
1064c6ba | 122 | struct meson_pwm *meson = to_meson_pwm(chip); |
37349609 | 123 | struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; |
e369035a | 124 | struct device *dev = pwmchip_parent(chip); |
211ed630 NA |
125 | int err; |
126 | ||
211ed630 NA |
127 | err = clk_prepare_enable(channel->clk); |
128 | if (err < 0) { | |
129 | dev_err(dev, "failed to enable clock %s: %d\n", | |
130 | __clk_get_name(channel->clk), err); | |
131 | return err; | |
132 | } | |
133 | ||
5f97f18f | 134 | return 0; |
211ed630 NA |
135 | } |
136 | ||
137 | static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
138 | { | |
5f97f18f UKK |
139 | struct meson_pwm *meson = to_meson_pwm(chip); |
140 | struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; | |
211ed630 | 141 | |
cb971fdb | 142 | clk_disable_unprepare(channel->clk); |
211ed630 NA |
143 | } |
144 | ||
b647dcfd | 145 | static int meson_pwm_calc(struct pwm_chip *chip, struct pwm_device *pwm, |
71523d18 | 146 | const struct pwm_state *state) |
211ed630 | 147 | { |
b647dcfd | 148 | struct meson_pwm *meson = to_meson_pwm(chip); |
5f97f18f | 149 | struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; |
329db102 | 150 | unsigned int cnt, duty_cnt; |
437fb760 | 151 | unsigned long fin_freq; |
329db102 | 152 | u64 duty, period, freq; |
211ed630 | 153 | |
b79c3670 MB |
154 | duty = state->duty_cycle; |
155 | period = state->period; | |
156 | ||
8caa81eb UKK |
157 | /* |
158 | * Note this is wrong. The result is an output wave that isn't really | |
159 | * inverted and so is wrongly identified by .get_state as normal. | |
160 | * Fixing this needs some care however as some machines might rely on | |
161 | * this. | |
162 | */ | |
b79c3670 | 163 | if (state->polarity == PWM_POLARITY_INVERSED) |
211ed630 NA |
164 | duty = period - duty; |
165 | ||
329db102 HK |
166 | freq = div64_u64(NSEC_PER_SEC * 0xffffULL, period); |
167 | if (freq > ULONG_MAX) | |
168 | freq = ULONG_MAX; | |
169 | ||
170 | fin_freq = clk_round_rate(channel->clk, freq); | |
211ed630 | 171 | if (fin_freq == 0) { |
e369035a | 172 | dev_err(pwmchip_parent(chip), "invalid source clock frequency\n"); |
211ed630 NA |
173 | return -EINVAL; |
174 | } | |
175 | ||
e369035a | 176 | dev_dbg(pwmchip_parent(chip), "fin_freq: %lu Hz\n", fin_freq); |
211ed630 | 177 | |
329db102 | 178 | cnt = div_u64(fin_freq * period, NSEC_PER_SEC); |
fb2081e8 | 179 | if (cnt > 0xffff) { |
e369035a | 180 | dev_err(pwmchip_parent(chip), "unable to get period cnt\n"); |
fb2081e8 MB |
181 | return -EINVAL; |
182 | } | |
183 | ||
e369035a | 184 | dev_dbg(pwmchip_parent(chip), "period=%llu cnt=%u\n", period, cnt); |
211ed630 NA |
185 | |
186 | if (duty == period) { | |
211ed630 NA |
187 | channel->hi = cnt; |
188 | channel->lo = 0; | |
189 | } else if (duty == 0) { | |
211ed630 NA |
190 | channel->hi = 0; |
191 | channel->lo = cnt; | |
192 | } else { | |
329db102 | 193 | duty_cnt = div_u64(fin_freq * duty, NSEC_PER_SEC); |
211ed630 | 194 | |
e369035a | 195 | dev_dbg(pwmchip_parent(chip), "duty=%llu duty_cnt=%u\n", duty, duty_cnt); |
211ed630 | 196 | |
211ed630 NA |
197 | channel->hi = duty_cnt; |
198 | channel->lo = cnt - duty_cnt; | |
199 | } | |
200 | ||
329db102 HK |
201 | channel->rate = fin_freq; |
202 | ||
211ed630 NA |
203 | return 0; |
204 | } | |
205 | ||
b647dcfd | 206 | static void meson_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
211ed630 | 207 | { |
b647dcfd | 208 | struct meson_pwm *meson = to_meson_pwm(chip); |
5f97f18f | 209 | struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; |
8bbf3164 | 210 | struct meson_pwm_channel_data *channel_data; |
f173747f | 211 | unsigned long flags; |
8bbf3164 | 212 | u32 value; |
329db102 | 213 | int err; |
211ed630 | 214 | |
8bbf3164 | 215 | channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; |
211ed630 | 216 | |
329db102 HK |
217 | err = clk_set_rate(channel->clk, channel->rate); |
218 | if (err) | |
e369035a | 219 | dev_err(pwmchip_parent(chip), "setting clock rate failed\n"); |
f173747f | 220 | |
329db102 | 221 | spin_lock_irqsave(&meson->lock, flags); |
211ed630 | 222 | |
181164b6 MB |
223 | value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) | |
224 | FIELD_PREP(PWM_LOW_MASK, channel->lo); | |
8bbf3164 | 225 | writel(value, meson->base + channel_data->reg_offset); |
211ed630 NA |
226 | |
227 | value = readl(meson->base + REG_MISC_AB); | |
8bbf3164 | 228 | value |= channel_data->pwm_en_mask; |
211ed630 | 229 | writel(value, meson->base + REG_MISC_AB); |
f173747f MB |
230 | |
231 | spin_unlock_irqrestore(&meson->lock, flags); | |
211ed630 NA |
232 | } |
233 | ||
b647dcfd | 234 | static void meson_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
211ed630 | 235 | { |
b647dcfd | 236 | struct meson_pwm *meson = to_meson_pwm(chip); |
f173747f | 237 | unsigned long flags; |
8bbf3164 | 238 | u32 value; |
211ed630 | 239 | |
f173747f MB |
240 | spin_lock_irqsave(&meson->lock, flags); |
241 | ||
211ed630 | 242 | value = readl(meson->base + REG_MISC_AB); |
8bbf3164 | 243 | value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask; |
211ed630 | 244 | writel(value, meson->base + REG_MISC_AB); |
f173747f MB |
245 | |
246 | spin_unlock_irqrestore(&meson->lock, flags); | |
211ed630 NA |
247 | } |
248 | ||
249 | static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, | |
71523d18 | 250 | const struct pwm_state *state) |
211ed630 | 251 | { |
211ed630 | 252 | struct meson_pwm *meson = to_meson_pwm(chip); |
5f97f18f | 253 | struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; |
211ed630 NA |
254 | int err = 0; |
255 | ||
211ed630 | 256 | if (!state->enabled) { |
7341c785 MB |
257 | if (state->polarity == PWM_POLARITY_INVERSED) { |
258 | /* | |
259 | * This IP block revision doesn't have an "always high" | |
260 | * setting which we can use for "inverted disabled". | |
329db102 HK |
261 | * Instead we achieve this by setting mux parent with |
262 | * highest rate and minimum divider value, resulting | |
263 | * in the shortest possible duration for one "count" | |
264 | * and "period == duty_cycle". This results in a signal | |
7341c785 MB |
265 | * which is LOW for one "count", while being HIGH for |
266 | * the rest of the (so the signal is HIGH for slightly | |
267 | * less than 100% of the period, but this is the best | |
268 | * we can achieve). | |
269 | */ | |
329db102 | 270 | channel->rate = ULONG_MAX; |
7341c785 MB |
271 | channel->hi = ~0; |
272 | channel->lo = 0; | |
273 | ||
b647dcfd | 274 | meson_pwm_enable(chip, pwm); |
7341c785 | 275 | } else { |
b647dcfd | 276 | meson_pwm_disable(chip, pwm); |
7341c785 | 277 | } |
d6885b3e | 278 | } else { |
b647dcfd | 279 | err = meson_pwm_calc(chip, pwm, state); |
211ed630 | 280 | if (err < 0) |
f173747f | 281 | return err; |
211ed630 | 282 | |
b647dcfd | 283 | meson_pwm_enable(chip, pwm); |
211ed630 NA |
284 | } |
285 | ||
f173747f | 286 | return 0; |
211ed630 NA |
287 | } |
288 | ||
329db102 HK |
289 | static u64 meson_pwm_cnt_to_ns(struct pwm_chip *chip, struct pwm_device *pwm, |
290 | u32 cnt) | |
c375bcba MB |
291 | { |
292 | struct meson_pwm *meson = to_meson_pwm(chip); | |
293 | struct meson_pwm_channel *channel; | |
294 | unsigned long fin_freq; | |
c375bcba MB |
295 | |
296 | /* to_meson_pwm() can only be used after .get_state() is called */ | |
297 | channel = &meson->channels[pwm->hwpwm]; | |
298 | ||
299 | fin_freq = clk_get_rate(channel->clk); | |
300 | if (fin_freq == 0) | |
301 | return 0; | |
302 | ||
329db102 | 303 | return div64_ul(NSEC_PER_SEC * (u64)cnt, fin_freq); |
c375bcba MB |
304 | } |
305 | ||
6c452cff UKK |
306 | static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, |
307 | struct pwm_state *state) | |
211ed630 NA |
308 | { |
309 | struct meson_pwm *meson = to_meson_pwm(chip); | |
c375bcba MB |
310 | struct meson_pwm_channel_data *channel_data; |
311 | struct meson_pwm_channel *channel; | |
329db102 | 312 | u32 value; |
211ed630 NA |
313 | |
314 | if (!state) | |
6c452cff | 315 | return 0; |
211ed630 | 316 | |
c375bcba MB |
317 | channel = &meson->channels[pwm->hwpwm]; |
318 | channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; | |
211ed630 NA |
319 | |
320 | value = readl(meson->base + REG_MISC_AB); | |
329db102 | 321 | state->enabled = value & channel_data->pwm_en_mask; |
c375bcba MB |
322 | |
323 | value = readl(meson->base + channel_data->reg_offset); | |
c375bcba MB |
324 | channel->lo = FIELD_GET(PWM_LOW_MASK, value); |
325 | channel->hi = FIELD_GET(PWM_HIGH_MASK, value); | |
326 | ||
6b9352f3 HK |
327 | state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi); |
328 | state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi); | |
6c452cff | 329 | |
8caa81eb UKK |
330 | state->polarity = PWM_POLARITY_NORMAL; |
331 | ||
6c452cff | 332 | return 0; |
211ed630 NA |
333 | } |
334 | ||
335 | static const struct pwm_ops meson_pwm_ops = { | |
336 | .request = meson_pwm_request, | |
337 | .free = meson_pwm_free, | |
338 | .apply = meson_pwm_apply, | |
339 | .get_state = meson_pwm_get_state, | |
211ed630 NA |
340 | }; |
341 | ||
1031c2b4 JB |
342 | static int meson_pwm_init_clocks_meson8b(struct pwm_chip *chip, |
343 | struct clk_parent_data *mux_parent_data) | |
211ed630 | 344 | { |
b647dcfd | 345 | struct meson_pwm *meson = to_meson_pwm(chip); |
e369035a | 346 | struct device *dev = pwmchip_parent(chip); |
211ed630 NA |
347 | unsigned int i; |
348 | char name[255]; | |
349 | int err; | |
350 | ||
1031c2b4 | 351 | for (i = 0; i < MESON_NUM_PWMS; i++) { |
a50a49a4 | 352 | struct meson_pwm_channel *channel = &meson->channels[i]; |
329db102 | 353 | struct clk_parent_data div_parent = {}, gate_parent = {}; |
ed733003 | 354 | struct clk_init_data init = {}; |
211ed630 | 355 | |
b96e9eb6 | 356 | snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); |
211ed630 NA |
357 | |
358 | init.name = name; | |
359 | init.ops = &clk_mux_ops; | |
90b6c5c7 | 360 | init.flags = 0; |
ed733003 | 361 | init.parent_data = mux_parent_data; |
f2cea1dc | 362 | init.num_parents = MESON_NUM_MUX_PARENTS; |
211ed630 NA |
363 | |
364 | channel->mux.reg = meson->base + REG_MISC_AB; | |
8bbf3164 MB |
365 | channel->mux.shift = |
366 | meson_pwm_per_channel_data[i].clk_sel_shift; | |
33cefd84 | 367 | channel->mux.mask = MISC_CLK_SEL_MASK; |
211ed630 NA |
368 | channel->mux.flags = 0; |
369 | channel->mux.lock = &meson->lock; | |
370 | channel->mux.table = NULL; | |
371 | channel->mux.hw.init = &init; | |
372 | ||
329db102 | 373 | err = devm_clk_hw_register(dev, &channel->mux.hw); |
b41ccc3b UKK |
374 | if (err) |
375 | return dev_err_probe(dev, err, | |
376 | "failed to register %s\n", name); | |
329db102 HK |
377 | |
378 | snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i); | |
379 | ||
380 | init.name = name; | |
381 | init.ops = &clk_divider_ops; | |
382 | init.flags = CLK_SET_RATE_PARENT; | |
383 | div_parent.index = -1; | |
384 | div_parent.hw = &channel->mux.hw; | |
385 | init.parent_data = &div_parent; | |
386 | init.num_parents = 1; | |
387 | ||
388 | channel->div.reg = meson->base + REG_MISC_AB; | |
389 | channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift; | |
390 | channel->div.width = MISC_CLK_DIV_WIDTH; | |
391 | channel->div.hw.init = &init; | |
392 | channel->div.flags = 0; | |
393 | channel->div.lock = &meson->lock; | |
394 | ||
395 | err = devm_clk_hw_register(dev, &channel->div.hw); | |
b41ccc3b UKK |
396 | if (err) |
397 | return dev_err_probe(dev, err, | |
398 | "failed to register %s\n", name); | |
211ed630 | 399 | |
329db102 | 400 | snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i); |
211ed630 | 401 | |
329db102 HK |
402 | init.name = name; |
403 | init.ops = &clk_gate_ops; | |
404 | init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; | |
405 | gate_parent.index = -1; | |
406 | gate_parent.hw = &channel->div.hw; | |
407 | init.parent_data = &gate_parent; | |
408 | init.num_parents = 1; | |
409 | ||
410 | channel->gate.reg = meson->base + REG_MISC_AB; | |
411 | channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift; | |
412 | channel->gate.hw.init = &init; | |
413 | channel->gate.flags = 0; | |
414 | channel->gate.lock = &meson->lock; | |
415 | ||
416 | err = devm_clk_hw_register(dev, &channel->gate.hw); | |
b41ccc3b UKK |
417 | if (err) |
418 | return dev_err_probe(dev, err, "failed to register %s\n", name); | |
329db102 HK |
419 | |
420 | channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL); | |
b41ccc3b UKK |
421 | if (IS_ERR(channel->clk)) |
422 | return dev_err_probe(dev, PTR_ERR(channel->clk), | |
423 | "failed to register %s\n", name); | |
211ed630 NA |
424 | } |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
1031c2b4 JB |
429 | static int meson_pwm_init_channels_meson8b_legacy(struct pwm_chip *chip) |
430 | { | |
431 | struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; | |
432 | struct meson_pwm *meson = to_meson_pwm(chip); | |
433 | int i; | |
434 | ||
435 | dev_warn_once(pwmchip_parent(chip), | |
436 | "using obsolete compatible, please consider updating dt\n"); | |
437 | ||
438 | for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) { | |
439 | mux_parent_data[i].index = -1; | |
440 | mux_parent_data[i].name = meson->data->parent_names[i]; | |
441 | } | |
442 | ||
443 | return meson_pwm_init_clocks_meson8b(chip, mux_parent_data); | |
444 | } | |
445 | ||
446 | static int meson_pwm_init_channels_meson8b_v2(struct pwm_chip *chip) | |
447 | { | |
448 | struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; | |
449 | int i; | |
450 | ||
451 | /* | |
452 | * NOTE: Instead of relying on the hard coded names in the driver | |
453 | * as the legacy version, this relies on DT to provide the list of | |
454 | * clocks. | |
455 | * For once, using input numbers actually makes more sense than names. | |
456 | * Also DT requires clock-names to be explicitly ordered, so there is | |
457 | * no point bothering with clock names in this case. | |
458 | */ | |
459 | for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) | |
460 | mux_parent_data[i].index = i; | |
461 | ||
462 | return meson_pwm_init_clocks_meson8b(chip, mux_parent_data); | |
463 | } | |
464 | ||
465 | static const struct meson_pwm_data pwm_meson8b_data = { | |
466 | .parent_names = { "xtal", NULL, "fclk_div4", "fclk_div3" }, | |
467 | .channels_init = meson_pwm_init_channels_meson8b_legacy, | |
468 | }; | |
469 | ||
470 | /* | |
471 | * Only the 2 first inputs of the GXBB AO PWMs are valid | |
472 | * The last 2 are grounded | |
473 | */ | |
474 | static const struct meson_pwm_data pwm_gxbb_ao_data = { | |
475 | .parent_names = { "xtal", "clk81", NULL, NULL }, | |
476 | .channels_init = meson_pwm_init_channels_meson8b_legacy, | |
477 | }; | |
478 | ||
479 | static const struct meson_pwm_data pwm_axg_ee_data = { | |
480 | .parent_names = { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" }, | |
481 | .channels_init = meson_pwm_init_channels_meson8b_legacy, | |
482 | }; | |
483 | ||
484 | static const struct meson_pwm_data pwm_axg_ao_data = { | |
485 | .parent_names = { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" }, | |
486 | .channels_init = meson_pwm_init_channels_meson8b_legacy, | |
487 | }; | |
488 | ||
489 | static const struct meson_pwm_data pwm_g12a_ao_ab_data = { | |
490 | .parent_names = { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" }, | |
491 | .channels_init = meson_pwm_init_channels_meson8b_legacy, | |
492 | }; | |
493 | ||
494 | static const struct meson_pwm_data pwm_g12a_ao_cd_data = { | |
495 | .parent_names = { "xtal", "g12a_ao_clk81", NULL, NULL }, | |
496 | .channels_init = meson_pwm_init_channels_meson8b_legacy, | |
497 | }; | |
498 | ||
499 | static const struct meson_pwm_data pwm_meson8_v2_data = { | |
500 | .channels_init = meson_pwm_init_channels_meson8b_v2, | |
501 | }; | |
502 | ||
503 | static const struct of_device_id meson_pwm_matches[] = { | |
504 | { | |
505 | .compatible = "amlogic,meson8-pwm-v2", | |
506 | .data = &pwm_meson8_v2_data | |
507 | }, | |
508 | /* The following compatibles are obsolete */ | |
509 | { | |
510 | .compatible = "amlogic,meson8b-pwm", | |
511 | .data = &pwm_meson8b_data | |
512 | }, | |
513 | { | |
514 | .compatible = "amlogic,meson-gxbb-pwm", | |
515 | .data = &pwm_meson8b_data | |
516 | }, | |
517 | { | |
518 | .compatible = "amlogic,meson-gxbb-ao-pwm", | |
519 | .data = &pwm_gxbb_ao_data | |
520 | }, | |
521 | { | |
522 | .compatible = "amlogic,meson-axg-ee-pwm", | |
523 | .data = &pwm_axg_ee_data | |
524 | }, | |
525 | { | |
526 | .compatible = "amlogic,meson-axg-ao-pwm", | |
527 | .data = &pwm_axg_ao_data | |
528 | }, | |
529 | { | |
530 | .compatible = "amlogic,meson-g12a-ee-pwm", | |
531 | .data = &pwm_meson8b_data | |
532 | }, | |
533 | { | |
534 | .compatible = "amlogic,meson-g12a-ao-pwm-ab", | |
535 | .data = &pwm_g12a_ao_ab_data | |
536 | }, | |
537 | { | |
538 | .compatible = "amlogic,meson-g12a-ao-pwm-cd", | |
539 | .data = &pwm_g12a_ao_cd_data | |
540 | }, | |
541 | {}, | |
542 | }; | |
543 | MODULE_DEVICE_TABLE(of, meson_pwm_matches); | |
544 | ||
211ed630 NA |
545 | static int meson_pwm_probe(struct platform_device *pdev) |
546 | { | |
28ecf9bd | 547 | struct pwm_chip *chip; |
211ed630 | 548 | struct meson_pwm *meson; |
211ed630 NA |
549 | int err; |
550 | ||
28ecf9bd UKK |
551 | chip = devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson)); |
552 | if (IS_ERR(chip)) | |
553 | return PTR_ERR(chip); | |
554 | meson = to_meson_pwm(chip); | |
211ed630 | 555 | |
17076b10 | 556 | meson->base = devm_platform_ioremap_resource(pdev, 0); |
211ed630 NA |
557 | if (IS_ERR(meson->base)) |
558 | return PTR_ERR(meson->base); | |
559 | ||
c6999956 | 560 | spin_lock_init(&meson->lock); |
28ecf9bd | 561 | chip->ops = &meson_pwm_ops; |
211ed630 NA |
562 | |
563 | meson->data = of_device_get_match_data(&pdev->dev); | |
211ed630 | 564 | |
1031c2b4 | 565 | err = meson->data->channels_init(chip); |
211ed630 NA |
566 | if (err < 0) |
567 | return err; | |
568 | ||
28ecf9bd | 569 | err = devm_pwmchip_add(&pdev->dev, chip); |
b41ccc3b UKK |
570 | if (err < 0) |
571 | return dev_err_probe(&pdev->dev, err, | |
572 | "failed to register PWM chip\n"); | |
211ed630 | 573 | |
211ed630 NA |
574 | return 0; |
575 | } | |
576 | ||
211ed630 NA |
577 | static struct platform_driver meson_pwm_driver = { |
578 | .driver = { | |
579 | .name = "meson-pwm", | |
580 | .of_match_table = meson_pwm_matches, | |
581 | }, | |
582 | .probe = meson_pwm_probe, | |
211ed630 NA |
583 | }; |
584 | module_platform_driver(meson_pwm_driver); | |
585 | ||
211ed630 NA |
586 | MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver"); |
587 | MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); | |
588 | MODULE_LICENSE("Dual BSD/GPL"); |