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1cdb4413 | 1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
211ed630 | 2 | /* |
4ae42ce7 MB |
3 | * PWM controller driver for Amlogic Meson SoCs. |
4 | * | |
5 | * This PWM is only a set of Gates, Dividers and Counters: | |
6 | * PWM output is achieved by calculating a clock that permits calculating | |
7 | * two periods (low and high). The counter then has to be set to switch after | |
8 | * N cycles for the first half period. | |
9 | * The hardware has no "polarity" setting. This driver reverses the period | |
10 | * cycles (the low length is inverted with the high length) for | |
11 | * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity | |
12 | * from the hardware. | |
13 | * Setting the duty cycle will disable and re-enable the PWM output. | |
14 | * Disabling the PWM stops the output immediately (without waiting for the | |
15 | * current period to complete first). | |
16 | * | |
17 | * The public S912 (GXM) datasheet contains some documentation for this PWM | |
18 | * controller starting on page 543: | |
19 | * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf | |
20 | * An updated version of this IP block is found in S922X (G12B) SoCs. The | |
21 | * datasheet contains the description for this IP block revision starting at | |
22 | * page 1084: | |
23 | * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf | |
24 | * | |
211ed630 NA |
25 | * Copyright (c) 2016 BayLibre, SAS. |
26 | * Author: Neil Armstrong <narmstrong@baylibre.com> | |
27 | * Copyright (C) 2014 Amlogic, Inc. | |
211ed630 NA |
28 | */ |
29 | ||
181164b6 MB |
30 | #include <linux/bitfield.h> |
31 | #include <linux/bits.h> | |
211ed630 NA |
32 | #include <linux/clk.h> |
33 | #include <linux/clk-provider.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/kernel.h> | |
fb2081e8 | 37 | #include <linux/math64.h> |
211ed630 NA |
38 | #include <linux/module.h> |
39 | #include <linux/of.h> | |
40 | #include <linux/of_device.h> | |
41 | #include <linux/platform_device.h> | |
42 | #include <linux/pwm.h> | |
43 | #include <linux/slab.h> | |
44 | #include <linux/spinlock.h> | |
45 | ||
46 | #define REG_PWM_A 0x0 | |
47 | #define REG_PWM_B 0x4 | |
181164b6 MB |
48 | #define PWM_LOW_MASK GENMASK(15, 0) |
49 | #define PWM_HIGH_MASK GENMASK(31, 16) | |
211ed630 NA |
50 | |
51 | #define REG_MISC_AB 0x8 | |
52 | #define MISC_B_CLK_EN BIT(23) | |
53 | #define MISC_A_CLK_EN BIT(15) | |
54 | #define MISC_CLK_DIV_MASK 0x7f | |
55 | #define MISC_B_CLK_DIV_SHIFT 16 | |
56 | #define MISC_A_CLK_DIV_SHIFT 8 | |
57 | #define MISC_B_CLK_SEL_SHIFT 6 | |
58 | #define MISC_A_CLK_SEL_SHIFT 4 | |
33cefd84 | 59 | #define MISC_CLK_SEL_MASK 0x3 |
211ed630 NA |
60 | #define MISC_B_EN BIT(1) |
61 | #define MISC_A_EN BIT(0) | |
62 | ||
a50a49a4 MB |
63 | #define MESON_NUM_PWMS 2 |
64 | ||
8bbf3164 MB |
65 | static struct meson_pwm_channel_data { |
66 | u8 reg_offset; | |
67 | u8 clk_sel_shift; | |
68 | u8 clk_div_shift; | |
69 | u32 clk_en_mask; | |
70 | u32 pwm_en_mask; | |
71 | } meson_pwm_per_channel_data[MESON_NUM_PWMS] = { | |
72 | { | |
73 | .reg_offset = REG_PWM_A, | |
74 | .clk_sel_shift = MISC_A_CLK_SEL_SHIFT, | |
75 | .clk_div_shift = MISC_A_CLK_DIV_SHIFT, | |
76 | .clk_en_mask = MISC_A_CLK_EN, | |
77 | .pwm_en_mask = MISC_A_EN, | |
78 | }, | |
79 | { | |
80 | .reg_offset = REG_PWM_B, | |
81 | .clk_sel_shift = MISC_B_CLK_SEL_SHIFT, | |
82 | .clk_div_shift = MISC_B_CLK_DIV_SHIFT, | |
83 | .clk_en_mask = MISC_B_CLK_EN, | |
84 | .pwm_en_mask = MISC_B_EN, | |
85 | } | |
211ed630 NA |
86 | }; |
87 | ||
88 | struct meson_pwm_channel { | |
89 | unsigned int hi; | |
90 | unsigned int lo; | |
91 | u8 pre_div; | |
92 | ||
211ed630 NA |
93 | struct clk *clk_parent; |
94 | struct clk_mux mux; | |
95 | struct clk *clk; | |
96 | }; | |
97 | ||
98 | struct meson_pwm_data { | |
99 | const char * const *parent_names; | |
d396b20a | 100 | unsigned int num_parents; |
211ed630 NA |
101 | }; |
102 | ||
103 | struct meson_pwm { | |
104 | struct pwm_chip chip; | |
105 | const struct meson_pwm_data *data; | |
a50a49a4 | 106 | struct meson_pwm_channel channels[MESON_NUM_PWMS]; |
211ed630 | 107 | void __iomem *base; |
f173747f MB |
108 | /* |
109 | * Protects register (write) access to the REG_MISC_AB register | |
110 | * that is shared between the two PWMs. | |
111 | */ | |
211ed630 NA |
112 | spinlock_t lock; |
113 | }; | |
114 | ||
115 | static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip) | |
116 | { | |
117 | return container_of(chip, struct meson_pwm, chip); | |
118 | } | |
119 | ||
120 | static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) | |
121 | { | |
1064c6ba MB |
122 | struct meson_pwm *meson = to_meson_pwm(chip); |
123 | struct meson_pwm_channel *channel; | |
211ed630 NA |
124 | struct device *dev = chip->dev; |
125 | int err; | |
126 | ||
1064c6ba MB |
127 | channel = pwm_get_chip_data(pwm); |
128 | if (channel) | |
129 | return 0; | |
130 | ||
131 | channel = &meson->channels[pwm->hwpwm]; | |
211ed630 NA |
132 | |
133 | if (channel->clk_parent) { | |
134 | err = clk_set_parent(channel->clk, channel->clk_parent); | |
135 | if (err < 0) { | |
136 | dev_err(dev, "failed to set parent %s for %s: %d\n", | |
137 | __clk_get_name(channel->clk_parent), | |
138 | __clk_get_name(channel->clk), err); | |
b33d232e | 139 | return err; |
211ed630 NA |
140 | } |
141 | } | |
142 | ||
143 | err = clk_prepare_enable(channel->clk); | |
144 | if (err < 0) { | |
145 | dev_err(dev, "failed to enable clock %s: %d\n", | |
146 | __clk_get_name(channel->clk), err); | |
147 | return err; | |
148 | } | |
149 | ||
1064c6ba | 150 | return pwm_set_chip_data(pwm, channel); |
211ed630 NA |
151 | } |
152 | ||
153 | static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
154 | { | |
155 | struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); | |
156 | ||
157 | if (channel) | |
158 | clk_disable_unprepare(channel->clk); | |
159 | } | |
160 | ||
7e032162 | 161 | static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, |
71523d18 | 162 | const struct pwm_state *state) |
211ed630 | 163 | { |
7e032162 | 164 | struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); |
b79c3670 | 165 | unsigned int duty, period, pre_div, cnt, duty_cnt; |
437fb760 | 166 | unsigned long fin_freq; |
211ed630 | 167 | |
b79c3670 MB |
168 | duty = state->duty_cycle; |
169 | period = state->period; | |
170 | ||
171 | if (state->polarity == PWM_POLARITY_INVERSED) | |
211ed630 NA |
172 | duty = period - duty; |
173 | ||
211ed630 NA |
174 | fin_freq = clk_get_rate(channel->clk); |
175 | if (fin_freq == 0) { | |
176 | dev_err(meson->chip.dev, "invalid source clock frequency\n"); | |
177 | return -EINVAL; | |
178 | } | |
179 | ||
180 | dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); | |
211ed630 | 181 | |
fb2081e8 | 182 | pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL); |
51496e44 | 183 | if (pre_div > MISC_CLK_DIV_MASK) { |
211ed630 NA |
184 | dev_err(meson->chip.dev, "unable to get period pre_div\n"); |
185 | return -EINVAL; | |
186 | } | |
187 | ||
fb2081e8 MB |
188 | cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1)); |
189 | if (cnt > 0xffff) { | |
190 | dev_err(meson->chip.dev, "unable to get period cnt\n"); | |
191 | return -EINVAL; | |
192 | } | |
193 | ||
211ed630 NA |
194 | dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period, |
195 | pre_div, cnt); | |
196 | ||
197 | if (duty == period) { | |
198 | channel->pre_div = pre_div; | |
199 | channel->hi = cnt; | |
200 | channel->lo = 0; | |
201 | } else if (duty == 0) { | |
202 | channel->pre_div = pre_div; | |
203 | channel->hi = 0; | |
204 | channel->lo = cnt; | |
205 | } else { | |
206 | /* Then check is we can have the duty with the same pre_div */ | |
fb2081e8 MB |
207 | duty_cnt = div64_u64(fin_freq * (u64)duty, |
208 | NSEC_PER_SEC * (pre_div + 1)); | |
211ed630 NA |
209 | if (duty_cnt > 0xffff) { |
210 | dev_err(meson->chip.dev, "unable to get duty cycle\n"); | |
211 | return -EINVAL; | |
212 | } | |
213 | ||
214 | dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n", | |
215 | duty, pre_div, duty_cnt); | |
216 | ||
217 | channel->pre_div = pre_div; | |
218 | channel->hi = duty_cnt; | |
219 | channel->lo = cnt - duty_cnt; | |
220 | } | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
084f1376 | 225 | static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm) |
211ed630 | 226 | { |
084f1376 | 227 | struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); |
8bbf3164 | 228 | struct meson_pwm_channel_data *channel_data; |
f173747f | 229 | unsigned long flags; |
8bbf3164 | 230 | u32 value; |
211ed630 | 231 | |
8bbf3164 | 232 | channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; |
211ed630 | 233 | |
f173747f MB |
234 | spin_lock_irqsave(&meson->lock, flags); |
235 | ||
211ed630 | 236 | value = readl(meson->base + REG_MISC_AB); |
8bbf3164 MB |
237 | value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift); |
238 | value |= channel->pre_div << channel_data->clk_div_shift; | |
239 | value |= channel_data->clk_en_mask; | |
211ed630 NA |
240 | writel(value, meson->base + REG_MISC_AB); |
241 | ||
181164b6 MB |
242 | value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) | |
243 | FIELD_PREP(PWM_LOW_MASK, channel->lo); | |
8bbf3164 | 244 | writel(value, meson->base + channel_data->reg_offset); |
211ed630 NA |
245 | |
246 | value = readl(meson->base + REG_MISC_AB); | |
8bbf3164 | 247 | value |= channel_data->pwm_en_mask; |
211ed630 | 248 | writel(value, meson->base + REG_MISC_AB); |
f173747f MB |
249 | |
250 | spin_unlock_irqrestore(&meson->lock, flags); | |
211ed630 NA |
251 | } |
252 | ||
084f1376 | 253 | static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm) |
211ed630 | 254 | { |
f173747f | 255 | unsigned long flags; |
8bbf3164 | 256 | u32 value; |
211ed630 | 257 | |
f173747f MB |
258 | spin_lock_irqsave(&meson->lock, flags); |
259 | ||
211ed630 | 260 | value = readl(meson->base + REG_MISC_AB); |
8bbf3164 | 261 | value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask; |
211ed630 | 262 | writel(value, meson->base + REG_MISC_AB); |
f173747f MB |
263 | |
264 | spin_unlock_irqrestore(&meson->lock, flags); | |
211ed630 NA |
265 | } |
266 | ||
267 | static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, | |
71523d18 | 268 | const struct pwm_state *state) |
211ed630 | 269 | { |
7341c785 | 270 | struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); |
211ed630 | 271 | struct meson_pwm *meson = to_meson_pwm(chip); |
211ed630 NA |
272 | int err = 0; |
273 | ||
274 | if (!state) | |
275 | return -EINVAL; | |
276 | ||
211ed630 | 277 | if (!state->enabled) { |
7341c785 MB |
278 | if (state->polarity == PWM_POLARITY_INVERSED) { |
279 | /* | |
280 | * This IP block revision doesn't have an "always high" | |
281 | * setting which we can use for "inverted disabled". | |
282 | * Instead we achieve this using the same settings | |
283 | * that we use a pre_div of 0 (to get the shortest | |
284 | * possible duration for one "count") and | |
285 | * "period == duty_cycle". This results in a signal | |
286 | * which is LOW for one "count", while being HIGH for | |
287 | * the rest of the (so the signal is HIGH for slightly | |
288 | * less than 100% of the period, but this is the best | |
289 | * we can achieve). | |
290 | */ | |
291 | channel->pre_div = 0; | |
292 | channel->hi = ~0; | |
293 | channel->lo = 0; | |
294 | ||
295 | meson_pwm_enable(meson, pwm); | |
296 | } else { | |
297 | meson_pwm_disable(meson, pwm); | |
298 | } | |
d6885b3e | 299 | } else { |
7e032162 | 300 | err = meson_pwm_calc(meson, pwm, state); |
211ed630 | 301 | if (err < 0) |
f173747f | 302 | return err; |
211ed630 | 303 | |
084f1376 | 304 | meson_pwm_enable(meson, pwm); |
211ed630 NA |
305 | } |
306 | ||
f173747f | 307 | return 0; |
211ed630 NA |
308 | } |
309 | ||
c375bcba MB |
310 | static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip, |
311 | struct pwm_device *pwm, u32 cnt) | |
312 | { | |
313 | struct meson_pwm *meson = to_meson_pwm(chip); | |
314 | struct meson_pwm_channel *channel; | |
315 | unsigned long fin_freq; | |
316 | u32 fin_ns; | |
317 | ||
318 | /* to_meson_pwm() can only be used after .get_state() is called */ | |
319 | channel = &meson->channels[pwm->hwpwm]; | |
320 | ||
321 | fin_freq = clk_get_rate(channel->clk); | |
322 | if (fin_freq == 0) | |
323 | return 0; | |
324 | ||
325 | fin_ns = div_u64(NSEC_PER_SEC, fin_freq); | |
326 | ||
327 | return cnt * fin_ns * (channel->pre_div + 1); | |
328 | } | |
329 | ||
211ed630 NA |
330 | static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, |
331 | struct pwm_state *state) | |
332 | { | |
333 | struct meson_pwm *meson = to_meson_pwm(chip); | |
c375bcba MB |
334 | struct meson_pwm_channel_data *channel_data; |
335 | struct meson_pwm_channel *channel; | |
336 | u32 value, tmp; | |
211ed630 NA |
337 | |
338 | if (!state) | |
339 | return; | |
340 | ||
c375bcba MB |
341 | channel = &meson->channels[pwm->hwpwm]; |
342 | channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; | |
211ed630 NA |
343 | |
344 | value = readl(meson->base + REG_MISC_AB); | |
c375bcba MB |
345 | |
346 | tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask; | |
347 | state->enabled = (value & tmp) == tmp; | |
348 | ||
349 | tmp = value >> channel_data->clk_div_shift; | |
350 | channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp); | |
351 | ||
352 | value = readl(meson->base + channel_data->reg_offset); | |
353 | ||
354 | channel->lo = FIELD_GET(PWM_LOW_MASK, value); | |
355 | channel->hi = FIELD_GET(PWM_HIGH_MASK, value); | |
356 | ||
357 | if (channel->lo == 0) { | |
358 | state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi); | |
359 | state->duty_cycle = state->period; | |
360 | } else if (channel->lo >= channel->hi) { | |
361 | state->period = meson_pwm_cnt_to_ns(chip, pwm, | |
362 | channel->lo + channel->hi); | |
363 | state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, | |
364 | channel->hi); | |
365 | } else { | |
366 | state->period = 0; | |
367 | state->duty_cycle = 0; | |
368 | } | |
211ed630 NA |
369 | } |
370 | ||
371 | static const struct pwm_ops meson_pwm_ops = { | |
372 | .request = meson_pwm_request, | |
373 | .free = meson_pwm_free, | |
374 | .apply = meson_pwm_apply, | |
375 | .get_state = meson_pwm_get_state, | |
376 | .owner = THIS_MODULE, | |
377 | }; | |
378 | ||
379 | static const char * const pwm_meson8b_parent_names[] = { | |
380 | "xtal", "vid_pll", "fclk_div4", "fclk_div3" | |
381 | }; | |
382 | ||
383 | static const struct meson_pwm_data pwm_meson8b_data = { | |
384 | .parent_names = pwm_meson8b_parent_names, | |
d396b20a | 385 | .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names), |
211ed630 NA |
386 | }; |
387 | ||
388 | static const char * const pwm_gxbb_parent_names[] = { | |
389 | "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" | |
390 | }; | |
391 | ||
392 | static const struct meson_pwm_data pwm_gxbb_data = { | |
393 | .parent_names = pwm_gxbb_parent_names, | |
d396b20a JB |
394 | .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names), |
395 | }; | |
396 | ||
397 | /* | |
398 | * Only the 2 first inputs of the GXBB AO PWMs are valid | |
399 | * The last 2 are grounded | |
400 | */ | |
401 | static const char * const pwm_gxbb_ao_parent_names[] = { | |
402 | "xtal", "clk81" | |
403 | }; | |
404 | ||
405 | static const struct meson_pwm_data pwm_gxbb_ao_data = { | |
406 | .parent_names = pwm_gxbb_ao_parent_names, | |
407 | .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), | |
211ed630 NA |
408 | }; |
409 | ||
bccaa3f9 JH |
410 | static const char * const pwm_axg_ee_parent_names[] = { |
411 | "xtal", "fclk_div5", "fclk_div4", "fclk_div3" | |
412 | }; | |
413 | ||
414 | static const struct meson_pwm_data pwm_axg_ee_data = { | |
415 | .parent_names = pwm_axg_ee_parent_names, | |
416 | .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), | |
417 | }; | |
418 | ||
419 | static const char * const pwm_axg_ao_parent_names[] = { | |
420 | "aoclk81", "xtal", "fclk_div4", "fclk_div5" | |
421 | }; | |
422 | ||
423 | static const struct meson_pwm_data pwm_axg_ao_data = { | |
424 | .parent_names = pwm_axg_ao_parent_names, | |
425 | .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), | |
426 | }; | |
427 | ||
9bce02ef NA |
428 | static const char * const pwm_g12a_ao_ab_parent_names[] = { |
429 | "xtal", "aoclk81", "fclk_div4", "fclk_div5" | |
430 | }; | |
431 | ||
432 | static const struct meson_pwm_data pwm_g12a_ao_ab_data = { | |
433 | .parent_names = pwm_g12a_ao_ab_parent_names, | |
434 | .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names), | |
435 | }; | |
436 | ||
f41efceb | 437 | static const char * const pwm_g12a_ao_cd_parent_names[] = { |
9bce02ef | 438 | "xtal", "aoclk81", |
f41efceb NA |
439 | }; |
440 | ||
441 | static const struct meson_pwm_data pwm_g12a_ao_cd_data = { | |
442 | .parent_names = pwm_g12a_ao_cd_parent_names, | |
443 | .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), | |
444 | }; | |
445 | ||
446 | static const char * const pwm_g12a_ee_parent_names[] = { | |
447 | "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" | |
448 | }; | |
449 | ||
450 | static const struct meson_pwm_data pwm_g12a_ee_data = { | |
451 | .parent_names = pwm_g12a_ee_parent_names, | |
452 | .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names), | |
453 | }; | |
454 | ||
211ed630 | 455 | static const struct of_device_id meson_pwm_matches[] = { |
d396b20a JB |
456 | { |
457 | .compatible = "amlogic,meson8b-pwm", | |
458 | .data = &pwm_meson8b_data | |
459 | }, | |
460 | { | |
461 | .compatible = "amlogic,meson-gxbb-pwm", | |
462 | .data = &pwm_gxbb_data | |
463 | }, | |
464 | { | |
465 | .compatible = "amlogic,meson-gxbb-ao-pwm", | |
466 | .data = &pwm_gxbb_ao_data | |
467 | }, | |
bccaa3f9 JH |
468 | { |
469 | .compatible = "amlogic,meson-axg-ee-pwm", | |
470 | .data = &pwm_axg_ee_data | |
471 | }, | |
472 | { | |
473 | .compatible = "amlogic,meson-axg-ao-pwm", | |
474 | .data = &pwm_axg_ao_data | |
475 | }, | |
f41efceb NA |
476 | { |
477 | .compatible = "amlogic,meson-g12a-ee-pwm", | |
478 | .data = &pwm_g12a_ee_data | |
479 | }, | |
480 | { | |
481 | .compatible = "amlogic,meson-g12a-ao-pwm-ab", | |
9bce02ef | 482 | .data = &pwm_g12a_ao_ab_data |
f41efceb NA |
483 | }, |
484 | { | |
485 | .compatible = "amlogic,meson-g12a-ao-pwm-cd", | |
486 | .data = &pwm_g12a_ao_cd_data | |
487 | }, | |
211ed630 NA |
488 | {}, |
489 | }; | |
490 | MODULE_DEVICE_TABLE(of, meson_pwm_matches); | |
491 | ||
a50a49a4 | 492 | static int meson_pwm_init_channels(struct meson_pwm *meson) |
211ed630 NA |
493 | { |
494 | struct device *dev = meson->chip.dev; | |
211ed630 NA |
495 | struct clk_init_data init; |
496 | unsigned int i; | |
497 | char name[255]; | |
498 | int err; | |
499 | ||
500 | for (i = 0; i < meson->chip.npwm; i++) { | |
a50a49a4 | 501 | struct meson_pwm_channel *channel = &meson->channels[i]; |
211ed630 | 502 | |
b96e9eb6 | 503 | snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); |
211ed630 NA |
504 | |
505 | init.name = name; | |
506 | init.ops = &clk_mux_ops; | |
90b6c5c7 | 507 | init.flags = 0; |
211ed630 | 508 | init.parent_names = meson->data->parent_names; |
d396b20a | 509 | init.num_parents = meson->data->num_parents; |
211ed630 NA |
510 | |
511 | channel->mux.reg = meson->base + REG_MISC_AB; | |
8bbf3164 MB |
512 | channel->mux.shift = |
513 | meson_pwm_per_channel_data[i].clk_sel_shift; | |
33cefd84 | 514 | channel->mux.mask = MISC_CLK_SEL_MASK; |
211ed630 NA |
515 | channel->mux.flags = 0; |
516 | channel->mux.lock = &meson->lock; | |
517 | channel->mux.table = NULL; | |
518 | channel->mux.hw.init = &init; | |
519 | ||
520 | channel->clk = devm_clk_register(dev, &channel->mux.hw); | |
521 | if (IS_ERR(channel->clk)) { | |
522 | err = PTR_ERR(channel->clk); | |
523 | dev_err(dev, "failed to register %s: %d\n", name, err); | |
524 | return err; | |
525 | } | |
526 | ||
527 | snprintf(name, sizeof(name), "clkin%u", i); | |
528 | ||
ba4004c7 MB |
529 | channel->clk_parent = devm_clk_get_optional(dev, name); |
530 | if (IS_ERR(channel->clk_parent)) | |
531 | return PTR_ERR(channel->clk_parent); | |
211ed630 NA |
532 | } |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
211ed630 NA |
537 | static int meson_pwm_probe(struct platform_device *pdev) |
538 | { | |
211ed630 | 539 | struct meson_pwm *meson; |
211ed630 NA |
540 | int err; |
541 | ||
542 | meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL); | |
543 | if (!meson) | |
544 | return -ENOMEM; | |
545 | ||
17076b10 | 546 | meson->base = devm_platform_ioremap_resource(pdev, 0); |
211ed630 NA |
547 | if (IS_ERR(meson->base)) |
548 | return PTR_ERR(meson->base); | |
549 | ||
c6999956 | 550 | spin_lock_init(&meson->lock); |
211ed630 NA |
551 | meson->chip.dev = &pdev->dev; |
552 | meson->chip.ops = &meson_pwm_ops; | |
a50a49a4 | 553 | meson->chip.npwm = MESON_NUM_PWMS; |
211ed630 NA |
554 | meson->chip.of_xlate = of_pwm_xlate_with_flags; |
555 | meson->chip.of_pwm_n_cells = 3; | |
556 | ||
557 | meson->data = of_device_get_match_data(&pdev->dev); | |
211ed630 | 558 | |
a50a49a4 | 559 | err = meson_pwm_init_channels(meson); |
211ed630 NA |
560 | if (err < 0) |
561 | return err; | |
562 | ||
563 | err = pwmchip_add(&meson->chip); | |
564 | if (err < 0) { | |
565 | dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err); | |
566 | return err; | |
567 | } | |
568 | ||
211ed630 NA |
569 | platform_set_drvdata(pdev, meson); |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
574 | static int meson_pwm_remove(struct platform_device *pdev) | |
575 | { | |
576 | struct meson_pwm *meson = platform_get_drvdata(pdev); | |
577 | ||
578 | return pwmchip_remove(&meson->chip); | |
579 | } | |
580 | ||
581 | static struct platform_driver meson_pwm_driver = { | |
582 | .driver = { | |
583 | .name = "meson-pwm", | |
584 | .of_match_table = meson_pwm_matches, | |
585 | }, | |
586 | .probe = meson_pwm_probe, | |
587 | .remove = meson_pwm_remove, | |
588 | }; | |
589 | module_platform_driver(meson_pwm_driver); | |
590 | ||
211ed630 NA |
591 | MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver"); |
592 | MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); | |
593 | MODULE_LICENSE("Dual BSD/GPL"); |