[linux-2.6-block.git] / drivers / pwm / pwm-mediatek.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MediaTek Pulse Width Modulator driver
 *
 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
 *
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/types.h>

/* PWM registers and bits definitions */
#define PWMCON			0x00
#define PWMHDUR			0x04
#define PWMLDUR			0x08
#define PWMGDUR			0x0c
#define PWMWAVENUM		0x28
#define PWMDWIDTH		0x2c
#define PWM45DWIDTH_FIXUP	0x30
#define PWMTHRES		0x30
#define PWM45THRES_FIXUP	0x34
#define PWM_CK_26M_SEL		0x210

#define PWM_CLK_DIV_MAX		7

struct pwm_mediatek_of_data {
	unsigned int num_pwms;
	bool pwm45_fixup;
	bool has_ck_26m_sel;
	const unsigned int *reg_offset;
};

/**
 * struct pwm_mediatek_chip - struct representing PWM chip
 * @regs: base address of PWM chip
 * @clk_top: the top clock generator
 * @clk_main: the clock used by PWM core
 * @clk_pwms: the clock used by each PWM channel
 * @soc: pointer to chip's platform data
 */
struct pwm_mediatek_chip {
	void __iomem *regs;
	struct clk *clk_top;
	struct clk *clk_main;
	struct clk **clk_pwms;
	const struct pwm_mediatek_of_data *soc;
};

static const unsigned int mtk_pwm_reg_offset_v1[] = {
	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
};

static const unsigned int mtk_pwm_reg_offset_v2[] = {
	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
};

static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
				   struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	int ret;

	ret = clk_prepare_enable(pc->clk_top);
	if (ret < 0)
		return ret;

	ret = clk_prepare_enable(pc->clk_main);
	if (ret < 0)
		goto disable_clk_top;

	ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
	if (ret < 0)
		goto disable_clk_main;

	return 0;

disable_clk_main:
	clk_disable_unprepare(pc->clk_main);
disable_clk_top:
	clk_disable_unprepare(pc->clk_top);

	return ret;
}

static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
				     struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);

	clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
	clk_disable_unprepare(pc->clk_main);
	clk_disable_unprepare(pc->clk_top);
}

static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
				       unsigned int num, unsigned int offset,
				       u32 value)
{
	writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
}

static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
			       int duty_ns, int period_ns)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
	    reg_thres = PWMTHRES;
	unsigned long clk_rate;
	u64 resolution;
	int ret;

	ret = pwm_mediatek_clk_enable(chip, pwm);
	if (ret < 0)
		return ret;

	clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
	if (!clk_rate)
		return -EINVAL;

	/* Make sure we use the bus clock and not the 26MHz clock */
	if (pc->soc->has_ck_26m_sel)
		writel(0, pc->regs + PWM_CK_26M_SEL);

	/* Using resolution in picosecond gets accuracy higher */
	resolution = (u64)NSEC_PER_SEC * 1000;
	do_div(resolution, clk_rate);

	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
	while (cnt_period > 8191) {
		resolution *= 2;
		clkdiv++;
		cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
						   resolution);
	}

	if (clkdiv > PWM_CLK_DIV_MAX) {
		pwm_mediatek_clk_disable(chip, pwm);
		dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns);
		return -EINVAL;
	}

	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
		/*
		 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
		 * from the other PWMs on MT7623.
		 */
		reg_width = PWM45DWIDTH_FIXUP;
		reg_thres = PWM45THRES_FIXUP;
	}

	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);

	pwm_mediatek_clk_disable(chip, pwm);

	return 0;
}

static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 value;
	int ret;

	ret = pwm_mediatek_clk_enable(chip, pwm);
	if (ret < 0)
		return ret;

	value = readl(pc->regs);
	value |= BIT(pwm->hwpwm);
	writel(value, pc->regs);

	return 0;
}

static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 value;

	value = readl(pc->regs);
	value &= ~BIT(pwm->hwpwm);
	writel(value, pc->regs);

	pwm_mediatek_clk_disable(chip, pwm);
}

static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      const struct pwm_state *state)
{
	int err;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (pwm->state.enabled)
			pwm_mediatek_disable(chip, pwm);

		return 0;
	}

	err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!pwm->state.enabled)
		err = pwm_mediatek_enable(chip, pwm);

	return err;
}

static const struct pwm_ops pwm_mediatek_ops = {
	.apply = pwm_mediatek_apply,
};

static int pwm_mediatek_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	struct pwm_mediatek_chip *pc;
	const struct pwm_mediatek_of_data *soc;
	unsigned int i;
	int ret;

	soc = of_device_get_match_data(&pdev->dev);

	chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	pc = to_pwm_mediatek_chip(chip);

	pc->soc = soc;

	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->regs))
		return PTR_ERR(pc->regs);

	pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms,
				    sizeof(*pc->clk_pwms), GFP_KERNEL);
	if (!pc->clk_pwms)
		return -ENOMEM;

	pc->clk_top = devm_clk_get(&pdev->dev, "top");
	if (IS_ERR(pc->clk_top))
		return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
				     "Failed to get top clock\n");

	pc->clk_main = devm_clk_get(&pdev->dev, "main");
	if (IS_ERR(pc->clk_main))
		return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
				     "Failed to get main clock\n");

	for (i = 0; i < soc->num_pwms; i++) {
		char name[8];

		snprintf(name, sizeof(name), "pwm%d", i + 1);

		pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
		if (IS_ERR(pc->clk_pwms[i]))
			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
					     "Failed to get %s clock\n", name);
	}

	chip->ops = &pwm_mediatek_ops;

	ret = devm_pwmchip_add(&pdev->dev, chip);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");

	return 0;
}

static const struct pwm_mediatek_of_data mt2712_pwm_data = {
	.num_pwms = 8,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt6795_pwm_data = {
	.num_pwms = 7,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7622_pwm_data = {
	.num_pwms = 6,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7623_pwm_data = {
	.num_pwms = 5,
	.pwm45_fixup = true,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7628_pwm_data = {
	.num_pwms = 4,
	.pwm45_fixup = true,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7629_pwm_data = {
	.num_pwms = 1,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7981_pwm_data = {
	.num_pwms = 3,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v2,
};

static const struct pwm_mediatek_of_data mt7986_pwm_data = {
	.num_pwms = 2,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7988_pwm_data = {
	.num_pwms = 8,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v2,
};

static const struct pwm_mediatek_of_data mt8183_pwm_data = {
	.num_pwms = 4,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt8365_pwm_data = {
	.num_pwms = 3,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt8516_pwm_data = {
	.num_pwms = 5,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct of_device_id pwm_mediatek_of_match[] = {
	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
	{ .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
	{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
	{ .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
	{ },
};
MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);

static struct platform_driver pwm_mediatek_driver = {
	.driver = {
		.name = "pwm-mediatek",
		.of_match_table = pwm_mediatek_of_match,
	},
	.probe = pwm_mediatek_probe,
};
module_platform_driver(pwm_mediatek_driver);

MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("MediaTek general purpose Pulse Width Modulator driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4bea6dd5	1	// SPDX-License-Identifier: GPL-2.0
caf065f8	2	/*
4bea6dd5	3	* MediaTek Pulse Width Modulator driver
caf065f8 JC	4	*
caf065f8 JC	5	* Copyright (C) 2015 John Crispin <blogic@openwrt.org>
e7c197ec	6	* Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
caf065f8	7	*
caf065f8 JC	8	*/
	9
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/ioport.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/clk.h>
	16	#include <linux/of.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pwm.h>
	19	#include <linux/slab.h>
	20	#include <linux/types.h>
	21
	22	/* PWM registers and bits definitions */
	23	#define PWMCON 0x00
	24	#define PWMHDUR 0x04
	25	#define PWMLDUR 0x08
	26	#define PWMGDUR 0x0c
	27	#define PWMWAVENUM 0x28
	28	#define PWMDWIDTH 0x2c
360cc036	29	#define PWM45DWIDTH_FIXUP 0x30
caf065f8	30	#define PWMTHRES 0x30
360cc036	31	#define PWM45THRES_FIXUP 0x34
0c0ead76	32	#define PWM_CK_26M_SEL 0x210
caf065f8	33
8bdb65dc ZM	34	#define PWM_CLK_DIV_MAX 7
8bdb65dc ZM	35
2503781c	36	struct pwm_mediatek_of_data {
424268c7	37	unsigned int num_pwms;
360cc036	38	bool pwm45_fixup;
0c0ead76	39	bool has_ck_26m_sel;
967da67a	40	const unsigned int *reg_offset;
caf065f8 JC	41	};
	42
	43	/**
2503781c	44	* struct pwm_mediatek_chip - struct representing PWM chip
caf065f8	45	* @regs: base address of PWM chip
efecdeb8 SS	46	* @clk_top: the top clock generator
	47	* @clk_main: the clock used by PWM core
	48	* @clk_pwms: the clock used by each PWM channel
fc810e7c	49	* @soc: pointer to chip's platform data
caf065f8	50	*/
2503781c	51	struct pwm_mediatek_chip {
caf065f8	52	void __iomem *regs;
efecdeb8 SS	53	struct clk *clk_top;
	54	struct clk *clk_main;
	55	struct clk **clk_pwms;
2503781c	56	const struct pwm_mediatek_of_data *soc;
caf065f8 JC	57	};
caf065f8 JC	58
967da67a	59	static const unsigned int mtk_pwm_reg_offset_v1[] = {
424268c7 ZM	60	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
	61	};
	62
967da67a DG	63	static const unsigned int mtk_pwm_reg_offset_v2[] = {
	64	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
	65	};
	66
2503781c SS	67	static inline struct pwm_mediatek_chip *
2503781c SS	68	to_pwm_mediatek_chip(struct pwm_chip *chip)
caf065f8	69	{
1c8090d7	70	return pwmchip_get_drvdata(chip);
caf065f8 JC	71	}
caf065f8 JC	72
2503781c SS	73	static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
2503781c SS	74	struct pwm_device *pwm)
e7c197ec	75	{
2503781c	76	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
e7c197ec ZM	77	int ret;
e7c197ec ZM	78
efecdeb8	79	ret = clk_prepare_enable(pc->clk_top);
e7c197ec ZM	80	if (ret < 0)
	81	return ret;
	82
efecdeb8	83	ret = clk_prepare_enable(pc->clk_main);
e7c197ec ZM	84	if (ret < 0)
	85	goto disable_clk_top;
	86
efecdeb8	87	ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
e7c197ec ZM	88	if (ret < 0)
	89	goto disable_clk_main;
	90
	91	return 0;
	92
	93	disable_clk_main:
efecdeb8	94	clk_disable_unprepare(pc->clk_main);
e7c197ec	95	disable_clk_top:
efecdeb8	96	clk_disable_unprepare(pc->clk_top);
e7c197ec ZM	97
	98	return ret;
	99	}
	100
2503781c SS	101	static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
2503781c SS	102	struct pwm_device *pwm)
e7c197ec	103	{
2503781c	104	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
e7c197ec	105
efecdeb8 SS	106	clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
	107	clk_disable_unprepare(pc->clk_main);
	108	clk_disable_unprepare(pc->clk_top);
e7c197ec ZM	109	}
e7c197ec ZM	110
2503781c SS	111	static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
	112	unsigned int num, unsigned int offset,
	113	u32 value)
caf065f8	114	{
967da67a	115	writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
caf065f8 JC	116	}
caf065f8 JC	117
2503781c SS	118	static int pwm_mediatek_config(struct pwm_chip chip, struct pwm_device pwm,
2503781c SS	119	int duty_ns, int period_ns)
caf065f8	120	{
2503781c	121	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
04c0a4e0	122	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
360cc036	123	reg_thres = PWMTHRES;
7ca59947	124	unsigned long clk_rate;
04c0a4e0	125	u64 resolution;
e7c197ec ZM	126	int ret;
e7c197ec ZM	127
2503781c	128	ret = pwm_mediatek_clk_enable(chip, pwm);
e7c197ec ZM	129	if (ret < 0)
e7c197ec ZM	130	return ret;
caf065f8	131
7ca59947 JP	132	clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
	133	if (!clk_rate)
	134	return -EINVAL;
	135
0c0ead76 FP	136	/* Make sure we use the bus clock and not the 26MHz clock */
	137	if (pc->soc->has_ck_26m_sel)
	138	writel(0, pc->regs + PWM_CK_26M_SEL);
	139
04c0a4e0 SW	140	/* Using resolution in picosecond gets accuracy higher */
04c0a4e0 SW	141	resolution = (u64)NSEC_PER_SEC * 1000;
7ca59947	142	do_div(resolution, clk_rate);
caf065f8	143
04c0a4e0 SW	144	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
04c0a4e0 SW	145	while (cnt_period > 8191) {
caf065f8 JC	146	resolution *= 2;
caf065f8 JC	147	clkdiv++;
04c0a4e0 SW	148	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
04c0a4e0 SW	149	resolution);
caf065f8 JC	150	}
caf065f8 JC	151
8bdb65dc	152	if (clkdiv > PWM_CLK_DIV_MAX) {
2503781c	153	pwm_mediatek_clk_disable(chip, pwm);
f1b1e747	154	dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns);
caf065f8	155	return -EINVAL;
8bdb65dc	156	}
caf065f8	157
360cc036 SW	158	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
	159	/*
	160	* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
	161	* from the other PWMs on MT7623.
	162	*/
	163	reg_width = PWM45DWIDTH_FIXUP;
	164	reg_thres = PWM45THRES_FIXUP;
	165	}
	166
04c0a4e0	167	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
2503781c SS	168	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) \| clkdiv);
	169	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
	170	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
caf065f8	171
2503781c	172	pwm_mediatek_clk_disable(chip, pwm);
e7c197ec	173
caf065f8 JC	174	return 0;
	175	}
	176
2503781c	177	static int pwm_mediatek_enable(struct pwm_chip chip, struct pwm_device pwm)
caf065f8	178	{
2503781c	179	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
caf065f8 JC	180	u32 value;
	181	int ret;
	182
2503781c	183	ret = pwm_mediatek_clk_enable(chip, pwm);
caf065f8 JC	184	if (ret < 0)
	185	return ret;
	186
	187	value = readl(pc->regs);
	188	value \|= BIT(pwm->hwpwm);
	189	writel(value, pc->regs);
	190
	191	return 0;
	192	}
	193
2503781c	194	static void pwm_mediatek_disable(struct pwm_chip chip, struct pwm_device pwm)
caf065f8	195	{
2503781c	196	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
caf065f8 JC	197	u32 value;
	198
	199	value = readl(pc->regs);
	200	value &= ~BIT(pwm->hwpwm);
	201	writel(value, pc->regs);
	202
2503781c	203	pwm_mediatek_clk_disable(chip, pwm);
caf065f8 JC	204	}
caf065f8 JC	205
758de66f UKK	206	static int pwm_mediatek_apply(struct pwm_chip chip, struct pwm_device pwm,
	207	const struct pwm_state *state)
	208	{
	209	int err;
	210
	211	if (state->polarity != PWM_POLARITY_NORMAL)
	212	return -EINVAL;
	213
	214	if (!state->enabled) {
	215	if (pwm->state.enabled)
	216	pwm_mediatek_disable(chip, pwm);
	217
	218	return 0;
	219	}
	220
80943bbd	221	err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period);
758de66f UKK	222	if (err)
	223	return err;
	224
	225	if (!pwm->state.enabled)
	226	err = pwm_mediatek_enable(chip, pwm);
	227
	228	return err;
	229	}
	230
2503781c	231	static const struct pwm_ops pwm_mediatek_ops = {
758de66f	232	.apply = pwm_mediatek_apply,
caf065f8 JC	233	};
caf065f8 JC	234
2503781c	235	static int pwm_mediatek_probe(struct platform_device *pdev)
caf065f8	236	{
1c8090d7	237	struct pwm_chip *chip;
2503781c	238	struct pwm_mediatek_chip *pc;
1c8090d7	239	const struct pwm_mediatek_of_data *soc;
caf065f8 JC	240	unsigned int i;
	241	int ret;
	242
1c8090d7 UKK	243	soc = of_device_get_match_data(&pdev->dev);
	244
	245	chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc));
	246	if (IS_ERR(chip))
	247	return PTR_ERR(chip);
	248	pc = to_pwm_mediatek_chip(chip);
caf065f8	249
1c8090d7	250	pc->soc = soc;
424268c7	251
7681c2bd	252	pc->regs = devm_platform_ioremap_resource(pdev, 0);
caf065f8 JC	253	if (IS_ERR(pc->regs))
	254	return PTR_ERR(pc->regs);
	255
1c8090d7	256	pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms,
efecdeb8 SS	257	sizeof(*pc->clk_pwms), GFP_KERNEL);
	258	if (!pc->clk_pwms)
	259	return -ENOMEM;
	260
	261	pc->clk_top = devm_clk_get(&pdev->dev, "top");
5264e8ca ADR	262	if (IS_ERR(pc->clk_top))
5264e8ca ADR	263	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
4d690e50	264	"Failed to get top clock\n");
efecdeb8 SS	265
efecdeb8 SS	266	pc->clk_main = devm_clk_get(&pdev->dev, "main");
5264e8ca ADR	267	if (IS_ERR(pc->clk_main))
5264e8ca ADR	268	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
4d690e50	269	"Failed to get main clock\n");
efecdeb8	270
1c8090d7	271	for (i = 0; i < soc->num_pwms; i++) {
efecdeb8 SS	272	char name[8];
	273
	274	snprintf(name, sizeof(name), "pwm%d", i + 1);
	275
	276	pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
5264e8ca ADR	277	if (IS_ERR(pc->clk_pwms[i]))
5264e8ca ADR	278	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
4d690e50	279	"Failed to get %s clock\n", name);
caf065f8 JC	280	}
caf065f8 JC	281
1c8090d7	282	chip->ops = &pwm_mediatek_ops;
caf065f8	283
1c8090d7	284	ret = devm_pwmchip_add(&pdev->dev, chip);
5264e8ca ADR	285	if (ret < 0)
5264e8ca ADR	286	return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
caf065f8 JC	287
caf065f8 JC	288	return 0;
caf065f8 JC	289	}
caf065f8 JC	290
2503781c	291	static const struct pwm_mediatek_of_data mt2712_pwm_data = {
424268c7	292	.num_pwms = 8,
360cc036	293	.pwm45_fixup = false,
0c0ead76	294	.has_ck_26m_sel = false,
967da67a	295	.reg_offset = mtk_pwm_reg_offset_v1,
424268c7 ZM	296	};
424268c7 ZM	297
cb696e74 ADR	298	static const struct pwm_mediatek_of_data mt6795_pwm_data = {
	299	.num_pwms = 7,
	300	.pwm45_fixup = false,
	301	.has_ck_26m_sel = false,
967da67a	302	.reg_offset = mtk_pwm_reg_offset_v1,
cb696e74 ADR	303	};
cb696e74 ADR	304
2503781c	305	static const struct pwm_mediatek_of_data mt7622_pwm_data = {
424268c7	306	.num_pwms = 6,
360cc036	307	.pwm45_fixup = false,
aa3c668f	308	.has_ck_26m_sel = true,
967da67a	309	.reg_offset = mtk_pwm_reg_offset_v1,
424268c7 ZM	310	};
424268c7 ZM	311
2503781c	312	static const struct pwm_mediatek_of_data mt7623_pwm_data = {
424268c7	313	.num_pwms = 5,
360cc036	314	.pwm45_fixup = true,
0c0ead76	315	.has_ck_26m_sel = false,
967da67a	316	.reg_offset = mtk_pwm_reg_offset_v1,
8cdc43af JC	317	};
8cdc43af JC	318
2503781c	319	static const struct pwm_mediatek_of_data mt7628_pwm_data = {
8cdc43af JC	320	.num_pwms = 4,
8cdc43af JC	321	.pwm45_fixup = true,
0c0ead76	322	.has_ck_26m_sel = false,
967da67a	323	.reg_offset = mtk_pwm_reg_offset_v1,
424268c7 ZM	324	};
424268c7 ZM	325
715d14da SS	326	static const struct pwm_mediatek_of_data mt7629_pwm_data = {
	327	.num_pwms = 1,
	328	.pwm45_fixup = false,
0c0ead76	329	.has_ck_26m_sel = false,
967da67a	330	.reg_offset = mtk_pwm_reg_offset_v1,
715d14da SS	331	};
715d14da SS	332
967da67a DG	333	static const struct pwm_mediatek_of_data mt7981_pwm_data = {
967da67a DG	334	.num_pwms = 3,
8b2fbaed FP	335	.pwm45_fixup = false,
8b2fbaed FP	336	.has_ck_26m_sel = true,
967da67a	337	.reg_offset = mtk_pwm_reg_offset_v2,
8b2fbaed FP	338	};
8b2fbaed FP	339
967da67a DG	340	static const struct pwm_mediatek_of_data mt7986_pwm_data = {
967da67a DG	341	.num_pwms = 2,
394b5175 FP	342	.pwm45_fixup = false,
394b5175 FP	343	.has_ck_26m_sel = true,
967da67a	344	.reg_offset = mtk_pwm_reg_offset_v1,
394b5175 FP	345	};
394b5175 FP	346
eb58bf4a RM	347	static const struct pwm_mediatek_of_data mt7988_pwm_data = {
	348	.num_pwms = 8,
	349	.pwm45_fixup = false,
	350	.has_ck_26m_sel = false,
	351	.reg_offset = mtk_pwm_reg_offset_v2,
	352	};
	353
967da67a DG	354	static const struct pwm_mediatek_of_data mt8183_pwm_data = {
	355	.num_pwms = 4,
	356	.pwm45_fixup = false,
	357	.has_ck_26m_sel = true,
	358	.reg_offset = mtk_pwm_reg_offset_v1,
	359	};
	360
	361	static const struct pwm_mediatek_of_data mt8365_pwm_data = {
	362	.num_pwms = 3,
241eab76 DG	363	.pwm45_fixup = false,
241eab76 DG	364	.has_ck_26m_sel = true,
967da67a	365	.reg_offset = mtk_pwm_reg_offset_v1,
241eab76 DG	366	};
241eab76 DG	367
2503781c	368	static const struct pwm_mediatek_of_data mt8516_pwm_data = {
8d190728 FP	369	.num_pwms = 5,
8d190728 FP	370	.pwm45_fixup = false,
0c0ead76	371	.has_ck_26m_sel = true,
967da67a	372	.reg_offset = mtk_pwm_reg_offset_v1,
8d190728 FP	373	};
8d190728 FP	374
2503781c	375	static const struct of_device_id pwm_mediatek_of_match[] = {
424268c7	376	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
cb696e74	377	{ .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
424268c7 ZM	378	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
424268c7 ZM	379	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
8cdc43af	380	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
715d14da	381	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
967da67a	382	{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
241eab76	383	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
eb58bf4a	384	{ .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
8b2fbaed	385	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
394b5175	386	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
8d190728	387	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
424268c7	388	{ },
caf065f8	389	};
2503781c	390	MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
caf065f8	391
2503781c	392	static struct platform_driver pwm_mediatek_driver = {
caf065f8	393	.driver = {
2503781c SS	394	.name = "pwm-mediatek",
2503781c SS	395	.of_match_table = pwm_mediatek_of_match,
caf065f8	396	},
2503781c	397	.probe = pwm_mediatek_probe,
caf065f8	398	};
2503781c	399	module_platform_driver(pwm_mediatek_driver);
caf065f8 JC	400
caf065f8 JC	401	MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2c69747c	402	MODULE_DESCRIPTION("MediaTek general purpose Pulse Width Modulator driver");
4bea6dd5	403	MODULE_LICENSE("GPL v2");