[linux-block.git] / drivers / pwm / pwm-mediatek.c

/*
 * Mediatek Pulse Width Modulator driver
 *
 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/types.h>

/* PWM registers and bits definitions */
#define PWMCON			0x00
#define PWMHDUR			0x04
#define PWMLDUR			0x08
#define PWMGDUR			0x0c
#define PWMWAVENUM		0x28
#define PWMDWIDTH		0x2c
#define PWM45DWIDTH_FIXUP	0x30
#define PWMTHRES		0x30
#define PWM45THRES_FIXUP	0x34

#define PWM_CLK_DIV_MAX		7

enum {
	MTK_CLK_MAIN = 0,
	MTK_CLK_TOP,
	MTK_CLK_PWM1,
	MTK_CLK_PWM2,
	MTK_CLK_PWM3,
	MTK_CLK_PWM4,
	MTK_CLK_PWM5,
	MTK_CLK_PWM6,
	MTK_CLK_PWM7,
	MTK_CLK_PWM8,
	MTK_CLK_MAX,
};

static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
	"main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7",
	"pwm8"
};

struct mtk_pwm_platform_data {
	unsigned int num_pwms;
	bool pwm45_fixup;
};

/**
 * struct mtk_pwm_chip - struct representing PWM chip
 * @chip: linux PWM chip representation
 * @regs: base address of PWM chip
 * @clks: list of clocks
 */
struct mtk_pwm_chip {
	struct pwm_chip chip;
	void __iomem *regs;
	struct clk *clks[MTK_CLK_MAX];
	const struct mtk_pwm_platform_data *soc;
};

static const unsigned int mtk_pwm_reg_offset[] = {
	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
};

static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct mtk_pwm_chip, chip);
}

static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
	int ret;

	ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]);
	if (ret < 0)
		return ret;

	ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]);
	if (ret < 0)
		goto disable_clk_top;

	ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
	if (ret < 0)
		goto disable_clk_main;

	return 0;

disable_clk_main:
	clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
disable_clk_top:
	clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);

	return ret;
}

static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);

	clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
	clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
	clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
}

static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
				unsigned int offset)
{
	return readl(chip->regs + mtk_pwm_reg_offset[num] + offset);
}

static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
				  unsigned int num, unsigned int offset,
				  u32 value)
{
	writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset);
}

static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
	struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
	u32 resolution, clkdiv = 0, reg_width = PWMDWIDTH,
	    reg_thres = PWMTHRES;
	int ret;

	ret = mtk_pwm_clk_enable(chip, pwm);
	if (ret < 0)
		return ret;

	resolution = NSEC_PER_SEC / clk_get_rate(clk);

	while (period_ns / resolution > 8191) {
		resolution *= 2;
		clkdiv++;
	}

	if (clkdiv > PWM_CLK_DIV_MAX) {
		mtk_pwm_clk_disable(chip, pwm);
		dev_err(chip->dev, "period %d not supported\n", period_ns);
		return -EINVAL;
	}

	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
		/*
		 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
		 * from the other PWMs on MT7623.
		 */
		reg_width = PWM45DWIDTH_FIXUP;
		reg_thres = PWM45THRES_FIXUP;
	}

	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
	mtk_pwm_writel(pc, pwm->hwpwm, reg_width, period_ns / resolution);
	mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, duty_ns / resolution);

	mtk_pwm_clk_disable(chip, pwm);

	return 0;
}

static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
	u32 value;
	int ret;

	ret = mtk_pwm_clk_enable(chip, pwm);
	if (ret < 0)
		return ret;

	value = readl(pc->regs);
	value |= BIT(pwm->hwpwm);
	writel(value, pc->regs);

	return 0;
}

static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
	u32 value;

	value = readl(pc->regs);
	value &= ~BIT(pwm->hwpwm);
	writel(value, pc->regs);

	mtk_pwm_clk_disable(chip, pwm);
}

static const struct pwm_ops mtk_pwm_ops = {
	.config = mtk_pwm_config,
	.enable = mtk_pwm_enable,
	.disable = mtk_pwm_disable,
	.owner = THIS_MODULE,
};

static int mtk_pwm_probe(struct platform_device *pdev)
{
	const struct mtk_pwm_platform_data *data;
	struct mtk_pwm_chip *pc;
	struct resource *res;
	unsigned int i;
	int ret;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	data = of_device_get_match_data(&pdev->dev);
	if (data == NULL)
		return -EINVAL;
	pc->soc = data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pc->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pc->regs))
		return PTR_ERR(pc->regs);

	for (i = 0; i < data->num_pwms + 2; i++) {
		pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
		if (IS_ERR(pc->clks[i])) {
			dev_err(&pdev->dev, "clock: %s fail: %ld\n",
				mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i]));
			return PTR_ERR(pc->clks[i]);
		}
	}

	platform_set_drvdata(pdev, pc);

	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &mtk_pwm_ops;
	pc->chip.base = -1;
	pc->chip.npwm = data->num_pwms;

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		return ret;
	}

	return 0;
}

static int mtk_pwm_remove(struct platform_device *pdev)
{
	struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);

	return pwmchip_remove(&pc->chip);
}

static const struct mtk_pwm_platform_data mt2712_pwm_data = {
	.num_pwms = 8,
	.pwm45_fixup = false,
};

static const struct mtk_pwm_platform_data mt7622_pwm_data = {
	.num_pwms = 6,
	.pwm45_fixup = false,
};

static const struct mtk_pwm_platform_data mt7623_pwm_data = {
	.num_pwms = 5,
	.pwm45_fixup = true,
};

static const struct of_device_id mtk_pwm_of_match[] = {
	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
	{ },
};
MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);

static struct platform_driver mtk_pwm_driver = {
	.driver = {
		.name = "mtk-pwm",
		.of_match_table = mtk_pwm_of_match,
	},
	.probe = mtk_pwm_probe,
	.remove = mtk_pwm_remove,
};
module_platform_driver(mtk_pwm_driver);

MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
caf065f8 JC	1	/*
	2	* Mediatek Pulse Width Modulator driver
	3	*
	4	* Copyright (C) 2015 John Crispin <blogic@openwrt.org>
e7c197ec	5	* Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
caf065f8 JC	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
	12	#include <linux/err.h>
	13	#include <linux/io.h>
	14	#include <linux/ioport.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/clk.h>
	18	#include <linux/of.h>
424268c7	19	#include <linux/of_device.h>
caf065f8 JC	20	#include <linux/platform_device.h>
	21	#include <linux/pwm.h>
	22	#include <linux/slab.h>
	23	#include <linux/types.h>
	24
	25	/* PWM registers and bits definitions */
	26	#define PWMCON 0x00
	27	#define PWMHDUR 0x04
	28	#define PWMLDUR 0x08
	29	#define PWMGDUR 0x0c
	30	#define PWMWAVENUM 0x28
	31	#define PWMDWIDTH 0x2c
360cc036	32	#define PWM45DWIDTH_FIXUP 0x30
caf065f8	33	#define PWMTHRES 0x30
360cc036	34	#define PWM45THRES_FIXUP 0x34
caf065f8	35
8bdb65dc ZM	36	#define PWM_CLK_DIV_MAX 7
8bdb65dc ZM	37
caf065f8 JC	38	enum {
	39	MTK_CLK_MAIN = 0,
	40	MTK_CLK_TOP,
	41	MTK_CLK_PWM1,
	42	MTK_CLK_PWM2,
	43	MTK_CLK_PWM3,
	44	MTK_CLK_PWM4,
	45	MTK_CLK_PWM5,
424268c7 ZM	46	MTK_CLK_PWM6,
	47	MTK_CLK_PWM7,
	48	MTK_CLK_PWM8,
caf065f8 JC	49	MTK_CLK_MAX,
	50	};
	51
424268c7 ZM	52	static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
	53	"main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7",
	54	"pwm8"
	55	};
	56
	57	struct mtk_pwm_platform_data {
	58	unsigned int num_pwms;
360cc036	59	bool pwm45_fixup;
caf065f8 JC	60	};
	61
	62	/**
	63	* struct mtk_pwm_chip - struct representing PWM chip
	64	* @chip: linux PWM chip representation
	65	* @regs: base address of PWM chip
	66	* @clks: list of clocks
	67	*/
	68	struct mtk_pwm_chip {
	69	struct pwm_chip chip;
	70	void __iomem *regs;
	71	struct clk *clks[MTK_CLK_MAX];
360cc036	72	const struct mtk_pwm_platform_data *soc;
caf065f8 JC	73	};
caf065f8 JC	74
424268c7 ZM	75	static const unsigned int mtk_pwm_reg_offset[] = {
	76	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
	77	};
	78
caf065f8 JC	79	static inline struct mtk_pwm_chip to_mtk_pwm_chip(struct pwm_chip chip)
	80	{
	81	return container_of(chip, struct mtk_pwm_chip, chip);
	82	}
	83
e7c197ec ZM	84	static int mtk_pwm_clk_enable(struct pwm_chip chip, struct pwm_device pwm)
	85	{
	86	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
	87	int ret;
	88
	89	ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]);
	90	if (ret < 0)
	91	return ret;
	92
	93	ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]);
	94	if (ret < 0)
	95	goto disable_clk_top;
	96
	97	ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
	98	if (ret < 0)
	99	goto disable_clk_main;
	100
	101	return 0;
	102
	103	disable_clk_main:
	104	clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
	105	disable_clk_top:
	106	clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
	107
	108	return ret;
	109	}
	110
	111	static void mtk_pwm_clk_disable(struct pwm_chip chip, struct pwm_device pwm)
	112	{
	113	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
	114
	115	clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
	116	clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
	117	clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
	118	}
	119
caf065f8 JC	120	static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
	121	unsigned int offset)
	122	{
424268c7	123	return readl(chip->regs + mtk_pwm_reg_offset[num] + offset);
caf065f8 JC	124	}
	125
	126	static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
	127	unsigned int num, unsigned int offset,
	128	u32 value)
	129	{
424268c7	130	writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset);
caf065f8 JC	131	}
	132
	133	static int mtk_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	134	int duty_ns, int period_ns)
	135	{
	136	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
	137	struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
360cc036 SW	138	u32 resolution, clkdiv = 0, reg_width = PWMDWIDTH,
360cc036 SW	139	reg_thres = PWMTHRES;
e7c197ec ZM	140	int ret;
	141
	142	ret = mtk_pwm_clk_enable(chip, pwm);
	143	if (ret < 0)
	144	return ret;
caf065f8 JC	145
	146	resolution = NSEC_PER_SEC / clk_get_rate(clk);
	147
	148	while (period_ns / resolution > 8191) {
	149	resolution *= 2;
	150	clkdiv++;
	151	}
	152
8bdb65dc ZM	153	if (clkdiv > PWM_CLK_DIV_MAX) {
	154	mtk_pwm_clk_disable(chip, pwm);
	155	dev_err(chip->dev, "period %d not supported\n", period_ns);
caf065f8	156	return -EINVAL;
8bdb65dc	157	}
caf065f8	158
360cc036 SW	159	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
	160	/*
	161	* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
	162	* from the other PWMs on MT7623.
	163	*/
	164	reg_width = PWM45DWIDTH_FIXUP;
	165	reg_thres = PWM45THRES_FIXUP;
	166	}
	167
cd30798a	168	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) \| clkdiv);
360cc036 SW	169	mtk_pwm_writel(pc, pwm->hwpwm, reg_width, period_ns / resolution);
360cc036 SW	170	mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, duty_ns / resolution);
caf065f8	171
e7c197ec ZM	172	mtk_pwm_clk_disable(chip, pwm);
e7c197ec ZM	173
caf065f8 JC	174	return 0;
	175	}
	176
	177	static int mtk_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	178	{
	179	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
	180	u32 value;
	181	int ret;
	182
e7c197ec	183	ret = mtk_pwm_clk_enable(chip, pwm);
caf065f8 JC	184	if (ret < 0)
	185	return ret;
	186
	187	value = readl(pc->regs);
	188	value \|= BIT(pwm->hwpwm);
	189	writel(value, pc->regs);
	190
	191	return 0;
	192	}
	193
	194	static void mtk_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	195	{
	196	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
	197	u32 value;
	198
	199	value = readl(pc->regs);
	200	value &= ~BIT(pwm->hwpwm);
	201	writel(value, pc->regs);
	202
e7c197ec	203	mtk_pwm_clk_disable(chip, pwm);
caf065f8 JC	204	}
	205
	206	static const struct pwm_ops mtk_pwm_ops = {
	207	.config = mtk_pwm_config,
	208	.enable = mtk_pwm_enable,
	209	.disable = mtk_pwm_disable,
	210	.owner = THIS_MODULE,
	211	};
	212
	213	static int mtk_pwm_probe(struct platform_device *pdev)
	214	{
424268c7	215	const struct mtk_pwm_platform_data *data;
caf065f8 JC	216	struct mtk_pwm_chip *pc;
	217	struct resource *res;
	218	unsigned int i;
	219	int ret;
	220
	221	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	222	if (!pc)
	223	return -ENOMEM;
	224
424268c7 ZM	225	data = of_device_get_match_data(&pdev->dev);
	226	if (data == NULL)
	227	return -EINVAL;
360cc036	228	pc->soc = data;
424268c7	229
caf065f8 JC	230	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	231	pc->regs = devm_ioremap_resource(&pdev->dev, res);
	232	if (IS_ERR(pc->regs))
	233	return PTR_ERR(pc->regs);
	234
424268c7	235	for (i = 0; i < data->num_pwms + 2; i++) {
caf065f8	236	pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
424268c7 ZM	237	if (IS_ERR(pc->clks[i])) {
	238	dev_err(&pdev->dev, "clock: %s fail: %ld\n",
	239	mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i]));
caf065f8	240	return PTR_ERR(pc->clks[i]);
424268c7	241	}
caf065f8 JC	242	}
caf065f8 JC	243
caf065f8 JC	244	platform_set_drvdata(pdev, pc);
	245
	246	pc->chip.dev = &pdev->dev;
	247	pc->chip.ops = &mtk_pwm_ops;
	248	pc->chip.base = -1;
424268c7	249	pc->chip.npwm = data->num_pwms;
caf065f8 JC	250
	251	ret = pwmchip_add(&pc->chip);
	252	if (ret < 0) {
	253	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
e7c197ec	254	return ret;
caf065f8 JC	255	}
	256
	257	return 0;
caf065f8 JC	258	}
	259
	260	static int mtk_pwm_remove(struct platform_device *pdev)
	261	{
	262	struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
caf065f8 JC	263
	264	return pwmchip_remove(&pc->chip);
	265	}
	266
424268c7 ZM	267	static const struct mtk_pwm_platform_data mt2712_pwm_data = {
424268c7 ZM	268	.num_pwms = 8,
360cc036	269	.pwm45_fixup = false,
424268c7 ZM	270	};
	271
	272	static const struct mtk_pwm_platform_data mt7622_pwm_data = {
	273	.num_pwms = 6,
360cc036	274	.pwm45_fixup = false,
424268c7 ZM	275	};
	276
	277	static const struct mtk_pwm_platform_data mt7623_pwm_data = {
	278	.num_pwms = 5,
360cc036	279	.pwm45_fixup = true,
424268c7 ZM	280	};
424268c7 ZM	281
caf065f8	282	static const struct of_device_id mtk_pwm_of_match[] = {
424268c7 ZM	283	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
	284	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
	285	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
	286	{ },
caf065f8 JC	287	};
	288	MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
	289
	290	static struct platform_driver mtk_pwm_driver = {
	291	.driver = {
	292	.name = "mtk-pwm",
caf065f8 JC	293	.of_match_table = mtk_pwm_of_match,
	294	},
	295	.probe = mtk_pwm_probe,
	296	.remove = mtk_pwm_remove,
	297	};
	298	module_platform_driver(mtk_pwm_driver);
	299
	300	MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
caf065f8	301	MODULE_LICENSE("GPL");