[linux-block.git] / drivers / pwm / pwm-mediatek.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MediaTek Pulse Width Modulator driver
 *
 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
 *
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/types.h>

/* PWM registers and bits definitions */
#define PWMCON			0x00
#define PWMHDUR			0x04
#define PWMLDUR			0x08
#define PWMGDUR			0x0c
#define PWMWAVENUM		0x28
#define PWMDWIDTH		0x2c
#define PWM45DWIDTH_FIXUP	0x30
#define PWMTHRES		0x30
#define PWM45THRES_FIXUP	0x34
#define PWM_CK_26M_SEL		0x210

#define PWM_CLK_DIV_MAX		7

struct pwm_mediatek_of_data {
	unsigned int num_pwms;
	bool pwm45_fixup;
	bool has_ck_26m_sel;
};

/**
 * struct pwm_mediatek_chip - struct representing PWM chip
 * @chip: linux PWM chip representation
 * @regs: base address of PWM chip
 * @clk_top: the top clock generator
 * @clk_main: the clock used by PWM core
 * @clk_pwms: the clock used by each PWM channel
 * @clk_freq: the fix clock frequency of legacy MIPS SoC
 * @soc: pointer to chip's platform data
 */
struct pwm_mediatek_chip {
	struct pwm_chip chip;
	void __iomem *regs;
	struct clk *clk_top;
	struct clk *clk_main;
	struct clk **clk_pwms;
	const struct pwm_mediatek_of_data *soc;
};

static const unsigned int pwm_mediatek_reg_offset[] = {
	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
};

static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct pwm_mediatek_chip, chip);
}

static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
				   struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	int ret;

	ret = clk_prepare_enable(pc->clk_top);
	if (ret < 0)
		return ret;

	ret = clk_prepare_enable(pc->clk_main);
	if (ret < 0)
		goto disable_clk_top;

	ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
	if (ret < 0)
		goto disable_clk_main;

	return 0;

disable_clk_main:
	clk_disable_unprepare(pc->clk_main);
disable_clk_top:
	clk_disable_unprepare(pc->clk_top);

	return ret;
}

static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
				     struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);

	clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
	clk_disable_unprepare(pc->clk_main);
	clk_disable_unprepare(pc->clk_top);
}

static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
				     unsigned int num, unsigned int offset)
{
	return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
}

static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
				       unsigned int num, unsigned int offset,
				       u32 value)
{
	writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
}

static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
			       int duty_ns, int period_ns)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
	    reg_thres = PWMTHRES;
	u64 resolution;
	int ret;

	ret = pwm_mediatek_clk_enable(chip, pwm);

	if (ret < 0)
		return ret;

	/* Make sure we use the bus clock and not the 26MHz clock */
	if (pc->soc->has_ck_26m_sel)
		writel(0, pc->regs + PWM_CK_26M_SEL);

	/* Using resolution in picosecond gets accuracy higher */
	resolution = (u64)NSEC_PER_SEC * 1000;
	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));

	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
	while (cnt_period > 8191) {
		resolution *= 2;
		clkdiv++;
		cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
						   resolution);
	}

	if (clkdiv > PWM_CLK_DIV_MAX) {
		pwm_mediatek_clk_disable(chip, pwm);
		dev_err(chip->dev, "period %d not supported\n", period_ns);
		return -EINVAL;
	}

	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
		/*
		 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
		 * from the other PWMs on MT7623.
		 */
		reg_width = PWM45DWIDTH_FIXUP;
		reg_thres = PWM45THRES_FIXUP;
	}

	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);

	pwm_mediatek_clk_disable(chip, pwm);

	return 0;
}

static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 value;
	int ret;

	ret = pwm_mediatek_clk_enable(chip, pwm);
	if (ret < 0)
		return ret;

	value = readl(pc->regs);
	value |= BIT(pwm->hwpwm);
	writel(value, pc->regs);

	return 0;
}

static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 value;

	value = readl(pc->regs);
	value &= ~BIT(pwm->hwpwm);
	writel(value, pc->regs);

	pwm_mediatek_clk_disable(chip, pwm);
}

static const struct pwm_ops pwm_mediatek_ops = {
	.config = pwm_mediatek_config,
	.enable = pwm_mediatek_enable,
	.disable = pwm_mediatek_disable,
	.owner = THIS_MODULE,
};

static int pwm_mediatek_probe(struct platform_device *pdev)
{
	struct pwm_mediatek_chip *pc;
	unsigned int i;
	int ret;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	pc->soc = of_device_get_match_data(&pdev->dev);

	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->regs))
		return PTR_ERR(pc->regs);

	pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
				    sizeof(*pc->clk_pwms), GFP_KERNEL);
	if (!pc->clk_pwms)
		return -ENOMEM;

	pc->clk_top = devm_clk_get(&pdev->dev, "top");
	if (IS_ERR(pc->clk_top)) {
		dev_err(&pdev->dev, "clock: top fail: %ld\n",
			PTR_ERR(pc->clk_top));
		return PTR_ERR(pc->clk_top);
	}

	pc->clk_main = devm_clk_get(&pdev->dev, "main");
	if (IS_ERR(pc->clk_main)) {
		dev_err(&pdev->dev, "clock: main fail: %ld\n",
			PTR_ERR(pc->clk_main));
		return PTR_ERR(pc->clk_main);
	}

	for (i = 0; i < pc->soc->num_pwms; i++) {
		char name[8];

		snprintf(name, sizeof(name), "pwm%d", i + 1);

		pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
		if (IS_ERR(pc->clk_pwms[i])) {
			dev_err(&pdev->dev, "clock: %s fail: %ld\n",
				name, PTR_ERR(pc->clk_pwms[i]));
			return PTR_ERR(pc->clk_pwms[i]);
		}
	}

	platform_set_drvdata(pdev, pc);

	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &pwm_mediatek_ops;
	pc->chip.base = -1;
	pc->chip.npwm = pc->soc->num_pwms;

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		return ret;
	}

	return 0;
}

static int pwm_mediatek_remove(struct platform_device *pdev)
{
	struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev);

	return pwmchip_remove(&pc->chip);
}

static const struct pwm_mediatek_of_data mt2712_pwm_data = {
	.num_pwms = 8,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt7622_pwm_data = {
	.num_pwms = 6,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt7623_pwm_data = {
	.num_pwms = 5,
	.pwm45_fixup = true,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt7628_pwm_data = {
	.num_pwms = 4,
	.pwm45_fixup = true,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt7629_pwm_data = {
	.num_pwms = 1,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt8516_pwm_data = {
	.num_pwms = 5,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
};

static const struct of_device_id pwm_mediatek_of_match[] = {
	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
	{ },
};
MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);

static struct platform_driver pwm_mediatek_driver = {
	.driver = {
		.name = "pwm-mediatek",
		.of_match_table = pwm_mediatek_of_match,
	},
	.probe = pwm_mediatek_probe,
	.remove = pwm_mediatek_remove,
};
module_platform_driver(pwm_mediatek_driver);

MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4bea6dd5	1	// SPDX-License-Identifier: GPL-2.0
caf065f8	2	/*
4bea6dd5	3	* MediaTek Pulse Width Modulator driver
caf065f8 JC	4	*
caf065f8 JC	5	* Copyright (C) 2015 John Crispin <blogic@openwrt.org>
e7c197ec	6	* Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
caf065f8	7	*
caf065f8 JC	8	*/
	9
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/ioport.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/clk.h>
	16	#include <linux/of.h>
424268c7	17	#include <linux/of_device.h>
caf065f8 JC	18	#include <linux/platform_device.h>
	19	#include <linux/pwm.h>
	20	#include <linux/slab.h>
	21	#include <linux/types.h>
	22
	23	/* PWM registers and bits definitions */
	24	#define PWMCON 0x00
	25	#define PWMHDUR 0x04
	26	#define PWMLDUR 0x08
	27	#define PWMGDUR 0x0c
	28	#define PWMWAVENUM 0x28
	29	#define PWMDWIDTH 0x2c
360cc036	30	#define PWM45DWIDTH_FIXUP 0x30
caf065f8	31	#define PWMTHRES 0x30
360cc036	32	#define PWM45THRES_FIXUP 0x34
0c0ead76	33	#define PWM_CK_26M_SEL 0x210
caf065f8	34
8bdb65dc ZM	35	#define PWM_CLK_DIV_MAX 7
8bdb65dc ZM	36
2503781c	37	struct pwm_mediatek_of_data {
424268c7	38	unsigned int num_pwms;
360cc036	39	bool pwm45_fixup;
0c0ead76	40	bool has_ck_26m_sel;
caf065f8 JC	41	};
	42
	43	/**
2503781c	44	* struct pwm_mediatek_chip - struct representing PWM chip
caf065f8 JC	45	* @chip: linux PWM chip representation
caf065f8 JC	46	* @regs: base address of PWM chip
efecdeb8 SS	47	* @clk_top: the top clock generator
	48	* @clk_main: the clock used by PWM core
	49	* @clk_pwms: the clock used by each PWM channel
	50	* @clk_freq: the fix clock frequency of legacy MIPS SoC
fc810e7c	51	* @soc: pointer to chip's platform data
caf065f8	52	*/
2503781c	53	struct pwm_mediatek_chip {
caf065f8 JC	54	struct pwm_chip chip;
caf065f8 JC	55	void __iomem *regs;
efecdeb8 SS	56	struct clk *clk_top;
	57	struct clk *clk_main;
	58	struct clk **clk_pwms;
2503781c	59	const struct pwm_mediatek_of_data *soc;
caf065f8 JC	60	};
caf065f8 JC	61
2503781c	62	static const unsigned int pwm_mediatek_reg_offset[] = {
424268c7 ZM	63	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
	64	};
	65
2503781c SS	66	static inline struct pwm_mediatek_chip *
2503781c SS	67	to_pwm_mediatek_chip(struct pwm_chip *chip)
caf065f8	68	{
2503781c	69	return container_of(chip, struct pwm_mediatek_chip, chip);
caf065f8 JC	70	}
caf065f8 JC	71
2503781c SS	72	static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
2503781c SS	73	struct pwm_device *pwm)
e7c197ec	74	{
2503781c	75	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
e7c197ec ZM	76	int ret;
e7c197ec ZM	77
efecdeb8	78	ret = clk_prepare_enable(pc->clk_top);
e7c197ec ZM	79	if (ret < 0)
	80	return ret;
	81
efecdeb8	82	ret = clk_prepare_enable(pc->clk_main);
e7c197ec ZM	83	if (ret < 0)
	84	goto disable_clk_top;
	85
efecdeb8	86	ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
e7c197ec ZM	87	if (ret < 0)
	88	goto disable_clk_main;
	89
	90	return 0;
	91
	92	disable_clk_main:
efecdeb8	93	clk_disable_unprepare(pc->clk_main);
e7c197ec	94	disable_clk_top:
efecdeb8	95	clk_disable_unprepare(pc->clk_top);
e7c197ec ZM	96
	97	return ret;
	98	}
	99
2503781c SS	100	static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
2503781c SS	101	struct pwm_device *pwm)
e7c197ec	102	{
2503781c	103	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
e7c197ec	104
efecdeb8 SS	105	clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
	106	clk_disable_unprepare(pc->clk_main);
	107	clk_disable_unprepare(pc->clk_top);
e7c197ec ZM	108	}
e7c197ec ZM	109
2503781c SS	110	static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
2503781c SS	111	unsigned int num, unsigned int offset)
caf065f8	112	{
2503781c	113	return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
caf065f8 JC	114	}
caf065f8 JC	115
2503781c SS	116	static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
	117	unsigned int num, unsigned int offset,
	118	u32 value)
caf065f8	119	{
2503781c	120	writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
caf065f8 JC	121	}
caf065f8 JC	122
2503781c SS	123	static int pwm_mediatek_config(struct pwm_chip chip, struct pwm_device pwm,
2503781c SS	124	int duty_ns, int period_ns)
caf065f8	125	{
2503781c	126	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
04c0a4e0	127	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
360cc036	128	reg_thres = PWMTHRES;
04c0a4e0	129	u64 resolution;
e7c197ec ZM	130	int ret;
e7c197ec ZM	131
2503781c SS	132	ret = pwm_mediatek_clk_enable(chip, pwm);
2503781c SS	133
e7c197ec ZM	134	if (ret < 0)
e7c197ec ZM	135	return ret;
caf065f8	136
0c0ead76 FP	137	/* Make sure we use the bus clock and not the 26MHz clock */
	138	if (pc->soc->has_ck_26m_sel)
	139	writel(0, pc->regs + PWM_CK_26M_SEL);
	140
04c0a4e0 SW	141	/* Using resolution in picosecond gets accuracy higher */
04c0a4e0 SW	142	resolution = (u64)NSEC_PER_SEC * 1000;
2503781c	143	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
caf065f8	144
04c0a4e0 SW	145	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
04c0a4e0 SW	146	while (cnt_period > 8191) {
caf065f8 JC	147	resolution *= 2;
caf065f8 JC	148	clkdiv++;
04c0a4e0 SW	149	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
04c0a4e0 SW	150	resolution);
caf065f8 JC	151	}
caf065f8 JC	152
8bdb65dc	153	if (clkdiv > PWM_CLK_DIV_MAX) {
2503781c	154	pwm_mediatek_clk_disable(chip, pwm);
8bdb65dc	155	dev_err(chip->dev, "period %d not supported\n", period_ns);
caf065f8	156	return -EINVAL;
8bdb65dc	157	}
caf065f8	158
360cc036 SW	159	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
	160	/*
	161	* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
	162	* from the other PWMs on MT7623.
	163	*/
	164	reg_width = PWM45DWIDTH_FIXUP;
	165	reg_thres = PWM45THRES_FIXUP;
	166	}
	167
04c0a4e0	168	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
2503781c SS	169	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) \| clkdiv);
	170	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
	171	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
caf065f8	172
2503781c	173	pwm_mediatek_clk_disable(chip, pwm);
e7c197ec	174
caf065f8 JC	175	return 0;
	176	}
	177
2503781c	178	static int pwm_mediatek_enable(struct pwm_chip chip, struct pwm_device pwm)
caf065f8	179	{
2503781c	180	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
caf065f8 JC	181	u32 value;
	182	int ret;
	183
2503781c	184	ret = pwm_mediatek_clk_enable(chip, pwm);
caf065f8 JC	185	if (ret < 0)
	186	return ret;
	187
	188	value = readl(pc->regs);
	189	value \|= BIT(pwm->hwpwm);
	190	writel(value, pc->regs);
	191
	192	return 0;
	193	}
	194
2503781c	195	static void pwm_mediatek_disable(struct pwm_chip chip, struct pwm_device pwm)
caf065f8	196	{
2503781c	197	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
caf065f8 JC	198	u32 value;
	199
	200	value = readl(pc->regs);
	201	value &= ~BIT(pwm->hwpwm);
	202	writel(value, pc->regs);
	203
2503781c	204	pwm_mediatek_clk_disable(chip, pwm);
caf065f8 JC	205	}
caf065f8 JC	206
2503781c SS	207	static const struct pwm_ops pwm_mediatek_ops = {
	208	.config = pwm_mediatek_config,
	209	.enable = pwm_mediatek_enable,
	210	.disable = pwm_mediatek_disable,
caf065f8 JC	211	.owner = THIS_MODULE,
	212	};
	213
2503781c	214	static int pwm_mediatek_probe(struct platform_device *pdev)
caf065f8	215	{
2503781c	216	struct pwm_mediatek_chip *pc;
caf065f8 JC	217	unsigned int i;
	218	int ret;
	219
	220	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	221	if (!pc)
	222	return -ENOMEM;
	223
e6c7c258	224	pc->soc = of_device_get_match_data(&pdev->dev);
424268c7	225
7681c2bd	226	pc->regs = devm_platform_ioremap_resource(pdev, 0);
caf065f8 JC	227	if (IS_ERR(pc->regs))
	228	return PTR_ERR(pc->regs);
	229
efecdeb8 SS	230	pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
	231	sizeof(*pc->clk_pwms), GFP_KERNEL);
	232	if (!pc->clk_pwms)
	233	return -ENOMEM;
	234
	235	pc->clk_top = devm_clk_get(&pdev->dev, "top");
	236	if (IS_ERR(pc->clk_top)) {
	237	dev_err(&pdev->dev, "clock: top fail: %ld\n",
	238	PTR_ERR(pc->clk_top));
	239	return PTR_ERR(pc->clk_top);
	240	}
	241
	242	pc->clk_main = devm_clk_get(&pdev->dev, "main");
	243	if (IS_ERR(pc->clk_main)) {
	244	dev_err(&pdev->dev, "clock: main fail: %ld\n",
	245	PTR_ERR(pc->clk_main));
	246	return PTR_ERR(pc->clk_main);
	247	}
	248
	249	for (i = 0; i < pc->soc->num_pwms; i++) {
	250	char name[8];
	251
	252	snprintf(name, sizeof(name), "pwm%d", i + 1);
	253
	254	pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
	255	if (IS_ERR(pc->clk_pwms[i])) {
424268c7	256	dev_err(&pdev->dev, "clock: %s fail: %ld\n",
efecdeb8 SS	257	name, PTR_ERR(pc->clk_pwms[i]));
efecdeb8 SS	258	return PTR_ERR(pc->clk_pwms[i]);
424268c7	259	}
caf065f8 JC	260	}
caf065f8 JC	261
caf065f8 JC	262	platform_set_drvdata(pdev, pc);
	263
	264	pc->chip.dev = &pdev->dev;
2503781c	265	pc->chip.ops = &pwm_mediatek_ops;
caf065f8	266	pc->chip.base = -1;
e6c7c258	267	pc->chip.npwm = pc->soc->num_pwms;
caf065f8 JC	268
	269	ret = pwmchip_add(&pc->chip);
	270	if (ret < 0) {
	271	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
e7c197ec	272	return ret;
caf065f8 JC	273	}
	274
	275	return 0;
caf065f8 JC	276	}
caf065f8 JC	277
2503781c	278	static int pwm_mediatek_remove(struct platform_device *pdev)
caf065f8	279	{
2503781c	280	struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev);
caf065f8 JC	281
	282	return pwmchip_remove(&pc->chip);
	283	}
	284
2503781c	285	static const struct pwm_mediatek_of_data mt2712_pwm_data = {
424268c7	286	.num_pwms = 8,
360cc036	287	.pwm45_fixup = false,
0c0ead76	288	.has_ck_26m_sel = false,
424268c7 ZM	289	};
424268c7 ZM	290
2503781c	291	static const struct pwm_mediatek_of_data mt7622_pwm_data = {
424268c7	292	.num_pwms = 6,
360cc036	293	.pwm45_fixup = false,
0c0ead76	294	.has_ck_26m_sel = false,
424268c7 ZM	295	};
424268c7 ZM	296
2503781c	297	static const struct pwm_mediatek_of_data mt7623_pwm_data = {
424268c7	298	.num_pwms = 5,
360cc036	299	.pwm45_fixup = true,
0c0ead76	300	.has_ck_26m_sel = false,
8cdc43af JC	301	};
8cdc43af JC	302
2503781c	303	static const struct pwm_mediatek_of_data mt7628_pwm_data = {
8cdc43af JC	304	.num_pwms = 4,
8cdc43af JC	305	.pwm45_fixup = true,
0c0ead76	306	.has_ck_26m_sel = false,
424268c7 ZM	307	};
424268c7 ZM	308
715d14da SS	309	static const struct pwm_mediatek_of_data mt7629_pwm_data = {
	310	.num_pwms = 1,
	311	.pwm45_fixup = false,
0c0ead76	312	.has_ck_26m_sel = false,
715d14da SS	313	};
715d14da SS	314
2503781c	315	static const struct pwm_mediatek_of_data mt8516_pwm_data = {
8d190728 FP	316	.num_pwms = 5,
8d190728 FP	317	.pwm45_fixup = false,
0c0ead76	318	.has_ck_26m_sel = true,
8d190728 FP	319	};
8d190728 FP	320
2503781c	321	static const struct of_device_id pwm_mediatek_of_match[] = {
424268c7 ZM	322	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
	323	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
	324	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
8cdc43af	325	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
715d14da	326	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
8d190728	327	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
424268c7	328	{ },
caf065f8	329	};
2503781c	330	MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
caf065f8	331
2503781c	332	static struct platform_driver pwm_mediatek_driver = {
caf065f8	333	.driver = {
2503781c SS	334	.name = "pwm-mediatek",
2503781c SS	335	.of_match_table = pwm_mediatek_of_match,
caf065f8	336	},
2503781c SS	337	.probe = pwm_mediatek_probe,
2503781c SS	338	.remove = pwm_mediatek_remove,
caf065f8	339	};
2503781c	340	module_platform_driver(pwm_mediatek_driver);
caf065f8 JC	341
caf065f8 JC	342	MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4bea6dd5	343	MODULE_LICENSE("GPL v2");