[linux-block.git] / drivers / pwm / pwm-mediatek.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MediaTek Pulse Width Modulator driver
 *
 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
 *
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/types.h>

/* PWM registers and bits definitions */
#define PWMCON			0x00
#define PWMHDUR			0x04
#define PWMLDUR			0x08
#define PWMGDUR			0x0c
#define PWMWAVENUM		0x28
#define PWMDWIDTH		0x2c
#define PWM45DWIDTH_FIXUP	0x30
#define PWMTHRES		0x30
#define PWM45THRES_FIXUP	0x34
#define PWM_CK_26M_SEL		0x210

#define PWM_CLK_DIV_MAX		7

struct pwm_mediatek_of_data {
	unsigned int num_pwms;
	bool pwm45_fixup;
	bool has_ck_26m_sel;
};

/**
 * struct pwm_mediatek_chip - struct representing PWM chip
 * @chip: linux PWM chip representation
 * @regs: base address of PWM chip
 * @clk_top: the top clock generator
 * @clk_main: the clock used by PWM core
 * @clk_pwms: the clock used by each PWM channel
 * @clk_freq: the fix clock frequency of legacy MIPS SoC
 * @soc: pointer to chip's platform data
 */
struct pwm_mediatek_chip {
	struct pwm_chip chip;
	void __iomem *regs;
	struct clk *clk_top;
	struct clk *clk_main;
	struct clk **clk_pwms;
	const struct pwm_mediatek_of_data *soc;
};

static const unsigned int pwm_mediatek_reg_offset[] = {
	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
};

static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct pwm_mediatek_chip, chip);
}

static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
				   struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	int ret;

	ret = clk_prepare_enable(pc->clk_top);
	if (ret < 0)
		return ret;

	ret = clk_prepare_enable(pc->clk_main);
	if (ret < 0)
		goto disable_clk_top;

	ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
	if (ret < 0)
		goto disable_clk_main;

	return 0;

disable_clk_main:
	clk_disable_unprepare(pc->clk_main);
disable_clk_top:
	clk_disable_unprepare(pc->clk_top);

	return ret;
}

static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
				     struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);

	clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
	clk_disable_unprepare(pc->clk_main);
	clk_disable_unprepare(pc->clk_top);
}

static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
				       unsigned int num, unsigned int offset,
				       u32 value)
{
	writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
}

static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
			       int duty_ns, int period_ns)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
	    reg_thres = PWMTHRES;
	u64 resolution;
	int ret;

	ret = pwm_mediatek_clk_enable(chip, pwm);

	if (ret < 0)
		return ret;

	/* Make sure we use the bus clock and not the 26MHz clock */
	if (pc->soc->has_ck_26m_sel)
		writel(0, pc->regs + PWM_CK_26M_SEL);

	/* Using resolution in picosecond gets accuracy higher */
	resolution = (u64)NSEC_PER_SEC * 1000;
	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));

	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
	while (cnt_period > 8191) {
		resolution *= 2;
		clkdiv++;
		cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
						   resolution);
	}

	if (clkdiv > PWM_CLK_DIV_MAX) {
		pwm_mediatek_clk_disable(chip, pwm);
		dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
		return -EINVAL;
	}

	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
		/*
		 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
		 * from the other PWMs on MT7623.
		 */
		reg_width = PWM45DWIDTH_FIXUP;
		reg_thres = PWM45THRES_FIXUP;
	}

	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);

	pwm_mediatek_clk_disable(chip, pwm);

	return 0;
}

static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 value;
	int ret;

	ret = pwm_mediatek_clk_enable(chip, pwm);
	if (ret < 0)
		return ret;

	value = readl(pc->regs);
	value |= BIT(pwm->hwpwm);
	writel(value, pc->regs);

	return 0;
}

static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 value;

	value = readl(pc->regs);
	value &= ~BIT(pwm->hwpwm);
	writel(value, pc->regs);

	pwm_mediatek_clk_disable(chip, pwm);
}

static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      const struct pwm_state *state)
{
	int err;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (pwm->state.enabled)
			pwm_mediatek_disable(chip, pwm);

		return 0;
	}

	err = pwm_mediatek_config(pwm->chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!pwm->state.enabled)
		err = pwm_mediatek_enable(chip, pwm);

	return err;
}

static const struct pwm_ops pwm_mediatek_ops = {
	.apply = pwm_mediatek_apply,
	.owner = THIS_MODULE,
};

static int pwm_mediatek_probe(struct platform_device *pdev)
{
	struct pwm_mediatek_chip *pc;
	unsigned int i;
	int ret;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	pc->soc = of_device_get_match_data(&pdev->dev);

	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->regs))
		return PTR_ERR(pc->regs);

	pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
				    sizeof(*pc->clk_pwms), GFP_KERNEL);
	if (!pc->clk_pwms)
		return -ENOMEM;

	pc->clk_top = devm_clk_get(&pdev->dev, "top");
	if (IS_ERR(pc->clk_top))
		return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
				     "Failed to get top clock\n");

	pc->clk_main = devm_clk_get(&pdev->dev, "main");
	if (IS_ERR(pc->clk_main))
		return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
				     "Failed to get main clock\n");

	for (i = 0; i < pc->soc->num_pwms; i++) {
		char name[8];

		snprintf(name, sizeof(name), "pwm%d", i + 1);

		pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
		if (IS_ERR(pc->clk_pwms[i]))
			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
					     "Failed to get %s clock\n", name);
	}

	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &pwm_mediatek_ops;
	pc->chip.npwm = pc->soc->num_pwms;

	ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");

	return 0;
}

static const struct pwm_mediatek_of_data mt2712_pwm_data = {
	.num_pwms = 8,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt6795_pwm_data = {
	.num_pwms = 7,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt7622_pwm_data = {
	.num_pwms = 6,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
};

static const struct pwm_mediatek_of_data mt7623_pwm_data = {
	.num_pwms = 5,
	.pwm45_fixup = true,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt7628_pwm_data = {
	.num_pwms = 4,
	.pwm45_fixup = true,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt7629_pwm_data = {
	.num_pwms = 1,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
};

static const struct pwm_mediatek_of_data mt8183_pwm_data = {
	.num_pwms = 4,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
};

static const struct pwm_mediatek_of_data mt8365_pwm_data = {
	.num_pwms = 3,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
};

static const struct pwm_mediatek_of_data mt7986_pwm_data = {
	.num_pwms = 2,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
};

static const struct pwm_mediatek_of_data mt8516_pwm_data = {
	.num_pwms = 5,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
};

static const struct of_device_id pwm_mediatek_of_match[] = {
	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
	{ .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
	{ },
};
MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);

static struct platform_driver pwm_mediatek_driver = {
	.driver = {
		.name = "pwm-mediatek",
		.of_match_table = pwm_mediatek_of_match,
	},
	.probe = pwm_mediatek_probe,
};
module_platform_driver(pwm_mediatek_driver);

MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4bea6dd5	1	// SPDX-License-Identifier: GPL-2.0
caf065f8	2	/*
4bea6dd5	3	* MediaTek Pulse Width Modulator driver
caf065f8 JC	4	*
caf065f8 JC	5	* Copyright (C) 2015 John Crispin <blogic@openwrt.org>
e7c197ec	6	* Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
caf065f8	7	*
caf065f8 JC	8	*/
	9
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/ioport.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/clk.h>
	16	#include <linux/of.h>
424268c7	17	#include <linux/of_device.h>
caf065f8 JC	18	#include <linux/platform_device.h>
	19	#include <linux/pwm.h>
	20	#include <linux/slab.h>
	21	#include <linux/types.h>
	22
	23	/* PWM registers and bits definitions */
	24	#define PWMCON 0x00
	25	#define PWMHDUR 0x04
	26	#define PWMLDUR 0x08
	27	#define PWMGDUR 0x0c
	28	#define PWMWAVENUM 0x28
	29	#define PWMDWIDTH 0x2c
360cc036	30	#define PWM45DWIDTH_FIXUP 0x30
caf065f8	31	#define PWMTHRES 0x30
360cc036	32	#define PWM45THRES_FIXUP 0x34
0c0ead76	33	#define PWM_CK_26M_SEL 0x210
caf065f8	34
8bdb65dc ZM	35	#define PWM_CLK_DIV_MAX 7
8bdb65dc ZM	36
2503781c	37	struct pwm_mediatek_of_data {
424268c7	38	unsigned int num_pwms;
360cc036	39	bool pwm45_fixup;
0c0ead76	40	bool has_ck_26m_sel;
caf065f8 JC	41	};
	42
	43	/**
2503781c	44	* struct pwm_mediatek_chip - struct representing PWM chip
caf065f8 JC	45	* @chip: linux PWM chip representation
caf065f8 JC	46	* @regs: base address of PWM chip
efecdeb8 SS	47	* @clk_top: the top clock generator
	48	* @clk_main: the clock used by PWM core
	49	* @clk_pwms: the clock used by each PWM channel
	50	* @clk_freq: the fix clock frequency of legacy MIPS SoC
fc810e7c	51	* @soc: pointer to chip's platform data
caf065f8	52	*/
2503781c	53	struct pwm_mediatek_chip {
caf065f8 JC	54	struct pwm_chip chip;
caf065f8 JC	55	void __iomem *regs;
efecdeb8 SS	56	struct clk *clk_top;
	57	struct clk *clk_main;
	58	struct clk **clk_pwms;
2503781c	59	const struct pwm_mediatek_of_data *soc;
caf065f8 JC	60	};
caf065f8 JC	61
2503781c	62	static const unsigned int pwm_mediatek_reg_offset[] = {
424268c7 ZM	63	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
	64	};
	65
2503781c SS	66	static inline struct pwm_mediatek_chip *
2503781c SS	67	to_pwm_mediatek_chip(struct pwm_chip *chip)
caf065f8	68	{
2503781c	69	return container_of(chip, struct pwm_mediatek_chip, chip);
caf065f8 JC	70	}
caf065f8 JC	71
2503781c SS	72	static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
2503781c SS	73	struct pwm_device *pwm)
e7c197ec	74	{
2503781c	75	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
e7c197ec ZM	76	int ret;
e7c197ec ZM	77
efecdeb8	78	ret = clk_prepare_enable(pc->clk_top);
e7c197ec ZM	79	if (ret < 0)
	80	return ret;
	81
efecdeb8	82	ret = clk_prepare_enable(pc->clk_main);
e7c197ec ZM	83	if (ret < 0)
	84	goto disable_clk_top;
	85
efecdeb8	86	ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
e7c197ec ZM	87	if (ret < 0)
	88	goto disable_clk_main;
	89
	90	return 0;
	91
	92	disable_clk_main:
efecdeb8	93	clk_disable_unprepare(pc->clk_main);
e7c197ec	94	disable_clk_top:
efecdeb8	95	clk_disable_unprepare(pc->clk_top);
e7c197ec ZM	96
	97	return ret;
	98	}
	99
2503781c SS	100	static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
2503781c SS	101	struct pwm_device *pwm)
e7c197ec	102	{
2503781c	103	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
e7c197ec	104
efecdeb8 SS	105	clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
	106	clk_disable_unprepare(pc->clk_main);
	107	clk_disable_unprepare(pc->clk_top);
e7c197ec ZM	108	}
e7c197ec ZM	109
2503781c SS	110	static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
	111	unsigned int num, unsigned int offset,
	112	u32 value)
caf065f8	113	{
2503781c	114	writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
caf065f8 JC	115	}
caf065f8 JC	116
2503781c SS	117	static int pwm_mediatek_config(struct pwm_chip chip, struct pwm_device pwm,
2503781c SS	118	int duty_ns, int period_ns)
caf065f8	119	{
2503781c	120	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
04c0a4e0	121	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
360cc036	122	reg_thres = PWMTHRES;
04c0a4e0	123	u64 resolution;
e7c197ec ZM	124	int ret;
e7c197ec ZM	125
2503781c SS	126	ret = pwm_mediatek_clk_enable(chip, pwm);
2503781c SS	127
e7c197ec ZM	128	if (ret < 0)
e7c197ec ZM	129	return ret;
caf065f8	130
0c0ead76 FP	131	/* Make sure we use the bus clock and not the 26MHz clock */
	132	if (pc->soc->has_ck_26m_sel)
	133	writel(0, pc->regs + PWM_CK_26M_SEL);
	134
04c0a4e0 SW	135	/* Using resolution in picosecond gets accuracy higher */
04c0a4e0 SW	136	resolution = (u64)NSEC_PER_SEC * 1000;
2503781c	137	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
caf065f8	138
04c0a4e0 SW	139	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
04c0a4e0 SW	140	while (cnt_period > 8191) {
caf065f8 JC	141	resolution *= 2;
caf065f8 JC	142	clkdiv++;
04c0a4e0 SW	143	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
04c0a4e0 SW	144	resolution);
caf065f8 JC	145	}
caf065f8 JC	146
8bdb65dc	147	if (clkdiv > PWM_CLK_DIV_MAX) {
2503781c	148	pwm_mediatek_clk_disable(chip, pwm);
4d690e50	149	dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
caf065f8	150	return -EINVAL;
8bdb65dc	151	}
caf065f8	152
360cc036 SW	153	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
	154	/*
	155	* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
	156	* from the other PWMs on MT7623.
	157	*/
	158	reg_width = PWM45DWIDTH_FIXUP;
	159	reg_thres = PWM45THRES_FIXUP;
	160	}
	161
04c0a4e0	162	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
2503781c SS	163	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) \| clkdiv);
	164	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
	165	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
caf065f8	166
2503781c	167	pwm_mediatek_clk_disable(chip, pwm);
e7c197ec	168
caf065f8 JC	169	return 0;
	170	}
	171
2503781c	172	static int pwm_mediatek_enable(struct pwm_chip chip, struct pwm_device pwm)
caf065f8	173	{
2503781c	174	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
caf065f8 JC	175	u32 value;
	176	int ret;
	177
2503781c	178	ret = pwm_mediatek_clk_enable(chip, pwm);
caf065f8 JC	179	if (ret < 0)
	180	return ret;
	181
	182	value = readl(pc->regs);
	183	value \|= BIT(pwm->hwpwm);
	184	writel(value, pc->regs);
	185
	186	return 0;
	187	}
	188
2503781c	189	static void pwm_mediatek_disable(struct pwm_chip chip, struct pwm_device pwm)
caf065f8	190	{
2503781c	191	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
caf065f8 JC	192	u32 value;
	193
	194	value = readl(pc->regs);
	195	value &= ~BIT(pwm->hwpwm);
	196	writel(value, pc->regs);
	197
2503781c	198	pwm_mediatek_clk_disable(chip, pwm);
caf065f8 JC	199	}
caf065f8 JC	200
758de66f UKK	201	static int pwm_mediatek_apply(struct pwm_chip chip, struct pwm_device pwm,
	202	const struct pwm_state *state)
	203	{
	204	int err;
	205
	206	if (state->polarity != PWM_POLARITY_NORMAL)
	207	return -EINVAL;
	208
	209	if (!state->enabled) {
	210	if (pwm->state.enabled)
	211	pwm_mediatek_disable(chip, pwm);
	212
	213	return 0;
	214	}
	215
	216	err = pwm_mediatek_config(pwm->chip, pwm, state->duty_cycle, state->period);
	217	if (err)
	218	return err;
	219
	220	if (!pwm->state.enabled)
	221	err = pwm_mediatek_enable(chip, pwm);
	222
	223	return err;
	224	}
	225
2503781c	226	static const struct pwm_ops pwm_mediatek_ops = {
758de66f	227	.apply = pwm_mediatek_apply,
caf065f8 JC	228	.owner = THIS_MODULE,
	229	};
	230
2503781c	231	static int pwm_mediatek_probe(struct platform_device *pdev)
caf065f8	232	{
2503781c	233	struct pwm_mediatek_chip *pc;
caf065f8 JC	234	unsigned int i;
	235	int ret;
	236
	237	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	238	if (!pc)
	239	return -ENOMEM;
	240
e6c7c258	241	pc->soc = of_device_get_match_data(&pdev->dev);
424268c7	242
7681c2bd	243	pc->regs = devm_platform_ioremap_resource(pdev, 0);
caf065f8 JC	244	if (IS_ERR(pc->regs))
	245	return PTR_ERR(pc->regs);
	246
446925f1	247	pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
efecdeb8 SS	248	sizeof(*pc->clk_pwms), GFP_KERNEL);
	249	if (!pc->clk_pwms)
	250	return -ENOMEM;
	251
	252	pc->clk_top = devm_clk_get(&pdev->dev, "top");
5264e8ca ADR	253	if (IS_ERR(pc->clk_top))
5264e8ca ADR	254	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
4d690e50	255	"Failed to get top clock\n");
efecdeb8 SS	256
efecdeb8 SS	257	pc->clk_main = devm_clk_get(&pdev->dev, "main");
5264e8ca ADR	258	if (IS_ERR(pc->clk_main))
5264e8ca ADR	259	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
4d690e50	260	"Failed to get main clock\n");
efecdeb8 SS	261
	262	for (i = 0; i < pc->soc->num_pwms; i++) {
	263	char name[8];
	264
	265	snprintf(name, sizeof(name), "pwm%d", i + 1);
	266
	267	pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
5264e8ca ADR	268	if (IS_ERR(pc->clk_pwms[i]))
5264e8ca ADR	269	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
4d690e50	270	"Failed to get %s clock\n", name);
caf065f8 JC	271	}
caf065f8 JC	272
caf065f8	273	pc->chip.dev = &pdev->dev;
2503781c	274	pc->chip.ops = &pwm_mediatek_ops;
e6c7c258	275	pc->chip.npwm = pc->soc->num_pwms;
caf065f8	276
e0150252	277	ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
5264e8ca ADR	278	if (ret < 0)
5264e8ca ADR	279	return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
caf065f8 JC	280
caf065f8 JC	281	return 0;
caf065f8 JC	282	}
caf065f8 JC	283
2503781c	284	static const struct pwm_mediatek_of_data mt2712_pwm_data = {
424268c7	285	.num_pwms = 8,
360cc036	286	.pwm45_fixup = false,
0c0ead76	287	.has_ck_26m_sel = false,
424268c7 ZM	288	};
424268c7 ZM	289
cb696e74 ADR	290	static const struct pwm_mediatek_of_data mt6795_pwm_data = {
	291	.num_pwms = 7,
	292	.pwm45_fixup = false,
	293	.has_ck_26m_sel = false,
	294	};
	295
2503781c	296	static const struct pwm_mediatek_of_data mt7622_pwm_data = {
424268c7	297	.num_pwms = 6,
360cc036	298	.pwm45_fixup = false,
aa3c668f	299	.has_ck_26m_sel = true,
424268c7 ZM	300	};
424268c7 ZM	301
2503781c	302	static const struct pwm_mediatek_of_data mt7623_pwm_data = {
424268c7	303	.num_pwms = 5,
360cc036	304	.pwm45_fixup = true,
0c0ead76	305	.has_ck_26m_sel = false,
8cdc43af JC	306	};
8cdc43af JC	307
2503781c	308	static const struct pwm_mediatek_of_data mt7628_pwm_data = {
8cdc43af JC	309	.num_pwms = 4,
8cdc43af JC	310	.pwm45_fixup = true,
0c0ead76	311	.has_ck_26m_sel = false,
424268c7 ZM	312	};
424268c7 ZM	313
715d14da SS	314	static const struct pwm_mediatek_of_data mt7629_pwm_data = {
	315	.num_pwms = 1,
	316	.pwm45_fixup = false,
0c0ead76	317	.has_ck_26m_sel = false,
715d14da SS	318	};
715d14da SS	319
8b2fbaed FP	320	static const struct pwm_mediatek_of_data mt8183_pwm_data = {
	321	.num_pwms = 4,
	322	.pwm45_fixup = false,
	323	.has_ck_26m_sel = true,
	324	};
	325
394b5175 FP	326	static const struct pwm_mediatek_of_data mt8365_pwm_data = {
	327	.num_pwms = 3,
	328	.pwm45_fixup = false,
	329	.has_ck_26m_sel = true,
	330	};
	331
241eab76 DG	332	static const struct pwm_mediatek_of_data mt7986_pwm_data = {
	333	.num_pwms = 2,
	334	.pwm45_fixup = false,
	335	.has_ck_26m_sel = true,
	336	};
	337
2503781c	338	static const struct pwm_mediatek_of_data mt8516_pwm_data = {
8d190728 FP	339	.num_pwms = 5,
8d190728 FP	340	.pwm45_fixup = false,
0c0ead76	341	.has_ck_26m_sel = true,
8d190728 FP	342	};
8d190728 FP	343
2503781c	344	static const struct of_device_id pwm_mediatek_of_match[] = {
424268c7	345	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
cb696e74	346	{ .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
424268c7 ZM	347	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
424268c7 ZM	348	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
8cdc43af	349	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
715d14da	350	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
241eab76	351	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
8b2fbaed	352	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
394b5175	353	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
8d190728	354	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
424268c7	355	{ },
caf065f8	356	};
2503781c	357	MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
caf065f8	358
2503781c	359	static struct platform_driver pwm_mediatek_driver = {
caf065f8	360	.driver = {
2503781c SS	361	.name = "pwm-mediatek",
2503781c SS	362	.of_match_table = pwm_mediatek_of_match,
caf065f8	363	},
2503781c	364	.probe = pwm_mediatek_probe,
caf065f8	365	};
2503781c	366	module_platform_driver(pwm_mediatek_driver);
caf065f8 JC	367
caf065f8 JC	368	MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4bea6dd5	369	MODULE_LICENSE("GPL v2");