[linux-block.git] / drivers / pwm / pwm-mediatek.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MediaTek Pulse Width Modulator driver
 *
 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
 *
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/types.h>

/* PWM registers and bits definitions */
#define PWMCON			0x00
#define PWMHDUR			0x04
#define PWMLDUR			0x08
#define PWMGDUR			0x0c
#define PWMWAVENUM		0x28
#define PWMDWIDTH		0x2c
#define PWM45DWIDTH_FIXUP	0x30
#define PWMTHRES		0x30
#define PWM45THRES_FIXUP	0x34
#define PWM_CK_26M_SEL		0x210

#define PWM_CLK_DIV_MAX		7

struct pwm_mediatek_of_data {
	unsigned int num_pwms;
	bool pwm45_fixup;
	bool has_ck_26m_sel;
	const unsigned int *reg_offset;
};

/**
 * struct pwm_mediatek_chip - struct representing PWM chip
 * @regs: base address of PWM chip
 * @clk_top: the top clock generator
 * @clk_main: the clock used by PWM core
 * @clk_pwms: the clock used by each PWM channel
 * @soc: pointer to chip's platform data
 */
struct pwm_mediatek_chip {
	void __iomem *regs;
	struct clk *clk_top;
	struct clk *clk_main;
	struct clk **clk_pwms;
	const struct pwm_mediatek_of_data *soc;
};

static const unsigned int mtk_pwm_reg_offset_v1[] = {
	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
};

static const unsigned int mtk_pwm_reg_offset_v2[] = {
	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
};

static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
				   struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	int ret;

	ret = clk_prepare_enable(pc->clk_top);
	if (ret < 0)
		return ret;

	ret = clk_prepare_enable(pc->clk_main);
	if (ret < 0)
		goto disable_clk_top;

	ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
	if (ret < 0)
		goto disable_clk_main;

	return 0;

disable_clk_main:
	clk_disable_unprepare(pc->clk_main);
disable_clk_top:
	clk_disable_unprepare(pc->clk_top);

	return ret;
}

static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
				     struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);

	clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
	clk_disable_unprepare(pc->clk_main);
	clk_disable_unprepare(pc->clk_top);
}

static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
				       unsigned int num, unsigned int offset,
				       u32 value)
{
	writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
}

static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
			       int duty_ns, int period_ns)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
	    reg_thres = PWMTHRES;
	u64 resolution;
	int ret;

	ret = pwm_mediatek_clk_enable(chip, pwm);

	if (ret < 0)
		return ret;

	/* Make sure we use the bus clock and not the 26MHz clock */
	if (pc->soc->has_ck_26m_sel)
		writel(0, pc->regs + PWM_CK_26M_SEL);

	/* Using resolution in picosecond gets accuracy higher */
	resolution = (u64)NSEC_PER_SEC * 1000;
	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));

	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
	while (cnt_period > 8191) {
		resolution *= 2;
		clkdiv++;
		cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
						   resolution);
	}

	if (clkdiv > PWM_CLK_DIV_MAX) {
		pwm_mediatek_clk_disable(chip, pwm);
		dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns);
		return -EINVAL;
	}

	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
		/*
		 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
		 * from the other PWMs on MT7623.
		 */
		reg_width = PWM45DWIDTH_FIXUP;
		reg_thres = PWM45THRES_FIXUP;
	}

	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);

	pwm_mediatek_clk_disable(chip, pwm);

	return 0;
}

static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 value;
	int ret;

	ret = pwm_mediatek_clk_enable(chip, pwm);
	if (ret < 0)
		return ret;

	value = readl(pc->regs);
	value |= BIT(pwm->hwpwm);
	writel(value, pc->regs);

	return 0;
}

static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
	u32 value;

	value = readl(pc->regs);
	value &= ~BIT(pwm->hwpwm);
	writel(value, pc->regs);

	pwm_mediatek_clk_disable(chip, pwm);
}

static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      const struct pwm_state *state)
{
	int err;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (pwm->state.enabled)
			pwm_mediatek_disable(chip, pwm);

		return 0;
	}

	err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!pwm->state.enabled)
		err = pwm_mediatek_enable(chip, pwm);

	return err;
}

static const struct pwm_ops pwm_mediatek_ops = {
	.apply = pwm_mediatek_apply,
};

static int pwm_mediatek_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	struct pwm_mediatek_chip *pc;
	const struct pwm_mediatek_of_data *soc;
	unsigned int i;
	int ret;

	soc = of_device_get_match_data(&pdev->dev);

	chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	pc = to_pwm_mediatek_chip(chip);

	pc->soc = soc;

	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->regs))
		return PTR_ERR(pc->regs);

	pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms,
				    sizeof(*pc->clk_pwms), GFP_KERNEL);
	if (!pc->clk_pwms)
		return -ENOMEM;

	pc->clk_top = devm_clk_get(&pdev->dev, "top");
	if (IS_ERR(pc->clk_top))
		return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
				     "Failed to get top clock\n");

	pc->clk_main = devm_clk_get(&pdev->dev, "main");
	if (IS_ERR(pc->clk_main))
		return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
				     "Failed to get main clock\n");

	for (i = 0; i < soc->num_pwms; i++) {
		char name[8];

		snprintf(name, sizeof(name), "pwm%d", i + 1);

		pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
		if (IS_ERR(pc->clk_pwms[i]))
			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
					     "Failed to get %s clock\n", name);
	}

	chip->ops = &pwm_mediatek_ops;

	ret = devm_pwmchip_add(&pdev->dev, chip);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");

	return 0;
}

static const struct pwm_mediatek_of_data mt2712_pwm_data = {
	.num_pwms = 8,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt6795_pwm_data = {
	.num_pwms = 7,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7622_pwm_data = {
	.num_pwms = 6,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7623_pwm_data = {
	.num_pwms = 5,
	.pwm45_fixup = true,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7628_pwm_data = {
	.num_pwms = 4,
	.pwm45_fixup = true,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7629_pwm_data = {
	.num_pwms = 1,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7981_pwm_data = {
	.num_pwms = 3,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v2,
};

static const struct pwm_mediatek_of_data mt7986_pwm_data = {
	.num_pwms = 2,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt7988_pwm_data = {
	.num_pwms = 8,
	.pwm45_fixup = false,
	.has_ck_26m_sel = false,
	.reg_offset = mtk_pwm_reg_offset_v2,
};

static const struct pwm_mediatek_of_data mt8183_pwm_data = {
	.num_pwms = 4,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt8365_pwm_data = {
	.num_pwms = 3,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct pwm_mediatek_of_data mt8516_pwm_data = {
	.num_pwms = 5,
	.pwm45_fixup = false,
	.has_ck_26m_sel = true,
	.reg_offset = mtk_pwm_reg_offset_v1,
};

static const struct of_device_id pwm_mediatek_of_match[] = {
	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
	{ .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
	{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
	{ .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
	{ },
};
MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);

static struct platform_driver pwm_mediatek_driver = {
	.driver = {
		.name = "pwm-mediatek",
		.of_match_table = pwm_mediatek_of_match,
	},
	.probe = pwm_mediatek_probe,
};
module_platform_driver(pwm_mediatek_driver);

MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("MediaTek general purpose Pulse Width Modulator driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4bea6dd5	1	// SPDX-License-Identifier: GPL-2.0
caf065f8	2	/*
4bea6dd5	3	* MediaTek Pulse Width Modulator driver
caf065f8 JC	4	*
caf065f8 JC	5	* Copyright (C) 2015 John Crispin <blogic@openwrt.org>
e7c197ec	6	* Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
caf065f8	7	*
caf065f8 JC	8	*/
	9
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/ioport.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/clk.h>
	16	#include <linux/of.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pwm.h>
	19	#include <linux/slab.h>
	20	#include <linux/types.h>
	21
	22	/* PWM registers and bits definitions */
	23	#define PWMCON 0x00
	24	#define PWMHDUR 0x04
	25	#define PWMLDUR 0x08
	26	#define PWMGDUR 0x0c
	27	#define PWMWAVENUM 0x28
	28	#define PWMDWIDTH 0x2c
360cc036	29	#define PWM45DWIDTH_FIXUP 0x30
caf065f8	30	#define PWMTHRES 0x30
360cc036	31	#define PWM45THRES_FIXUP 0x34
0c0ead76	32	#define PWM_CK_26M_SEL 0x210
caf065f8	33
8bdb65dc ZM	34	#define PWM_CLK_DIV_MAX 7
8bdb65dc ZM	35
2503781c	36	struct pwm_mediatek_of_data {
424268c7	37	unsigned int num_pwms;
360cc036	38	bool pwm45_fixup;
0c0ead76	39	bool has_ck_26m_sel;
967da67a	40	const unsigned int *reg_offset;
caf065f8 JC	41	};
	42
	43	/**
2503781c	44	* struct pwm_mediatek_chip - struct representing PWM chip
caf065f8	45	* @regs: base address of PWM chip
efecdeb8 SS	46	* @clk_top: the top clock generator
	47	* @clk_main: the clock used by PWM core
	48	* @clk_pwms: the clock used by each PWM channel
fc810e7c	49	* @soc: pointer to chip's platform data
caf065f8	50	*/
2503781c	51	struct pwm_mediatek_chip {
caf065f8	52	void __iomem *regs;
efecdeb8 SS	53	struct clk *clk_top;
	54	struct clk *clk_main;
	55	struct clk **clk_pwms;
2503781c	56	const struct pwm_mediatek_of_data *soc;
caf065f8 JC	57	};
caf065f8 JC	58
967da67a	59	static const unsigned int mtk_pwm_reg_offset_v1[] = {
424268c7 ZM	60	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
	61	};
	62
967da67a DG	63	static const unsigned int mtk_pwm_reg_offset_v2[] = {
	64	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
	65	};
	66
2503781c SS	67	static inline struct pwm_mediatek_chip *
2503781c SS	68	to_pwm_mediatek_chip(struct pwm_chip *chip)
caf065f8	69	{
1c8090d7	70	return pwmchip_get_drvdata(chip);
caf065f8 JC	71	}
caf065f8 JC	72
2503781c SS	73	static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
2503781c SS	74	struct pwm_device *pwm)
e7c197ec	75	{
2503781c	76	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
e7c197ec ZM	77	int ret;
e7c197ec ZM	78
efecdeb8	79	ret = clk_prepare_enable(pc->clk_top);
e7c197ec ZM	80	if (ret < 0)
	81	return ret;
	82
efecdeb8	83	ret = clk_prepare_enable(pc->clk_main);
e7c197ec ZM	84	if (ret < 0)
	85	goto disable_clk_top;
	86
efecdeb8	87	ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
e7c197ec ZM	88	if (ret < 0)
	89	goto disable_clk_main;
	90
	91	return 0;
	92
	93	disable_clk_main:
efecdeb8	94	clk_disable_unprepare(pc->clk_main);
e7c197ec	95	disable_clk_top:
efecdeb8	96	clk_disable_unprepare(pc->clk_top);
e7c197ec ZM	97
	98	return ret;
	99	}
	100
2503781c SS	101	static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
2503781c SS	102	struct pwm_device *pwm)
e7c197ec	103	{
2503781c	104	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
e7c197ec	105
efecdeb8 SS	106	clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
	107	clk_disable_unprepare(pc->clk_main);
	108	clk_disable_unprepare(pc->clk_top);
e7c197ec ZM	109	}
e7c197ec ZM	110
2503781c SS	111	static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
	112	unsigned int num, unsigned int offset,
	113	u32 value)
caf065f8	114	{
967da67a	115	writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
caf065f8 JC	116	}
caf065f8 JC	117
2503781c SS	118	static int pwm_mediatek_config(struct pwm_chip chip, struct pwm_device pwm,
2503781c SS	119	int duty_ns, int period_ns)
caf065f8	120	{
2503781c	121	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
04c0a4e0	122	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
360cc036	123	reg_thres = PWMTHRES;
04c0a4e0	124	u64 resolution;
e7c197ec ZM	125	int ret;
e7c197ec ZM	126
2503781c SS	127	ret = pwm_mediatek_clk_enable(chip, pwm);
2503781c SS	128
e7c197ec ZM	129	if (ret < 0)
e7c197ec ZM	130	return ret;
caf065f8	131
0c0ead76 FP	132	/* Make sure we use the bus clock and not the 26MHz clock */
	133	if (pc->soc->has_ck_26m_sel)
	134	writel(0, pc->regs + PWM_CK_26M_SEL);
	135
04c0a4e0 SW	136	/* Using resolution in picosecond gets accuracy higher */
04c0a4e0 SW	137	resolution = (u64)NSEC_PER_SEC * 1000;
2503781c	138	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
caf065f8	139
04c0a4e0 SW	140	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
04c0a4e0 SW	141	while (cnt_period > 8191) {
caf065f8 JC	142	resolution *= 2;
caf065f8 JC	143	clkdiv++;
04c0a4e0 SW	144	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
04c0a4e0 SW	145	resolution);
caf065f8 JC	146	}
caf065f8 JC	147
8bdb65dc	148	if (clkdiv > PWM_CLK_DIV_MAX) {
2503781c	149	pwm_mediatek_clk_disable(chip, pwm);
f1b1e747	150	dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns);
caf065f8	151	return -EINVAL;
8bdb65dc	152	}
caf065f8	153
360cc036 SW	154	if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
	155	/*
	156	* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
	157	* from the other PWMs on MT7623.
	158	*/
	159	reg_width = PWM45DWIDTH_FIXUP;
	160	reg_thres = PWM45THRES_FIXUP;
	161	}
	162
04c0a4e0	163	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
2503781c SS	164	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) \| clkdiv);
	165	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
	166	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
caf065f8	167
2503781c	168	pwm_mediatek_clk_disable(chip, pwm);
e7c197ec	169
caf065f8 JC	170	return 0;
	171	}
	172
2503781c	173	static int pwm_mediatek_enable(struct pwm_chip chip, struct pwm_device pwm)
caf065f8	174	{
2503781c	175	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
caf065f8 JC	176	u32 value;
	177	int ret;
	178
2503781c	179	ret = pwm_mediatek_clk_enable(chip, pwm);
caf065f8 JC	180	if (ret < 0)
	181	return ret;
	182
	183	value = readl(pc->regs);
	184	value \|= BIT(pwm->hwpwm);
	185	writel(value, pc->regs);
	186
	187	return 0;
	188	}
	189
2503781c	190	static void pwm_mediatek_disable(struct pwm_chip chip, struct pwm_device pwm)
caf065f8	191	{
2503781c	192	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
caf065f8 JC	193	u32 value;
	194
	195	value = readl(pc->regs);
	196	value &= ~BIT(pwm->hwpwm);
	197	writel(value, pc->regs);
	198
2503781c	199	pwm_mediatek_clk_disable(chip, pwm);
caf065f8 JC	200	}
caf065f8 JC	201
758de66f UKK	202	static int pwm_mediatek_apply(struct pwm_chip chip, struct pwm_device pwm,
	203	const struct pwm_state *state)
	204	{
	205	int err;
	206
	207	if (state->polarity != PWM_POLARITY_NORMAL)
	208	return -EINVAL;
	209
	210	if (!state->enabled) {
	211	if (pwm->state.enabled)
	212	pwm_mediatek_disable(chip, pwm);
	213
	214	return 0;
	215	}
	216
80943bbd	217	err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period);
758de66f UKK	218	if (err)
	219	return err;
	220
	221	if (!pwm->state.enabled)
	222	err = pwm_mediatek_enable(chip, pwm);
	223
	224	return err;
	225	}
	226
2503781c	227	static const struct pwm_ops pwm_mediatek_ops = {
758de66f	228	.apply = pwm_mediatek_apply,
caf065f8 JC	229	};
caf065f8 JC	230
2503781c	231	static int pwm_mediatek_probe(struct platform_device *pdev)
caf065f8	232	{
1c8090d7	233	struct pwm_chip *chip;
2503781c	234	struct pwm_mediatek_chip *pc;
1c8090d7	235	const struct pwm_mediatek_of_data *soc;
caf065f8 JC	236	unsigned int i;
	237	int ret;
	238
1c8090d7 UKK	239	soc = of_device_get_match_data(&pdev->dev);
	240
	241	chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc));
	242	if (IS_ERR(chip))
	243	return PTR_ERR(chip);
	244	pc = to_pwm_mediatek_chip(chip);
caf065f8	245
1c8090d7	246	pc->soc = soc;
424268c7	247
7681c2bd	248	pc->regs = devm_platform_ioremap_resource(pdev, 0);
caf065f8 JC	249	if (IS_ERR(pc->regs))
	250	return PTR_ERR(pc->regs);
	251
1c8090d7	252	pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms,
efecdeb8 SS	253	sizeof(*pc->clk_pwms), GFP_KERNEL);
	254	if (!pc->clk_pwms)
	255	return -ENOMEM;
	256
	257	pc->clk_top = devm_clk_get(&pdev->dev, "top");
5264e8ca ADR	258	if (IS_ERR(pc->clk_top))
5264e8ca ADR	259	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
4d690e50	260	"Failed to get top clock\n");
efecdeb8 SS	261
efecdeb8 SS	262	pc->clk_main = devm_clk_get(&pdev->dev, "main");
5264e8ca ADR	263	if (IS_ERR(pc->clk_main))
5264e8ca ADR	264	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
4d690e50	265	"Failed to get main clock\n");
efecdeb8	266
1c8090d7	267	for (i = 0; i < soc->num_pwms; i++) {
efecdeb8 SS	268	char name[8];
	269
	270	snprintf(name, sizeof(name), "pwm%d", i + 1);
	271
	272	pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
5264e8ca ADR	273	if (IS_ERR(pc->clk_pwms[i]))
5264e8ca ADR	274	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
4d690e50	275	"Failed to get %s clock\n", name);
caf065f8 JC	276	}
caf065f8 JC	277
1c8090d7	278	chip->ops = &pwm_mediatek_ops;
caf065f8	279
1c8090d7	280	ret = devm_pwmchip_add(&pdev->dev, chip);
5264e8ca ADR	281	if (ret < 0)
5264e8ca ADR	282	return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
caf065f8 JC	283
caf065f8 JC	284	return 0;
caf065f8 JC	285	}
caf065f8 JC	286
2503781c	287	static const struct pwm_mediatek_of_data mt2712_pwm_data = {
424268c7	288	.num_pwms = 8,
360cc036	289	.pwm45_fixup = false,
0c0ead76	290	.has_ck_26m_sel = false,
967da67a	291	.reg_offset = mtk_pwm_reg_offset_v1,
424268c7 ZM	292	};
424268c7 ZM	293
cb696e74 ADR	294	static const struct pwm_mediatek_of_data mt6795_pwm_data = {
	295	.num_pwms = 7,
	296	.pwm45_fixup = false,
	297	.has_ck_26m_sel = false,
967da67a	298	.reg_offset = mtk_pwm_reg_offset_v1,
cb696e74 ADR	299	};
cb696e74 ADR	300
2503781c	301	static const struct pwm_mediatek_of_data mt7622_pwm_data = {
424268c7	302	.num_pwms = 6,
360cc036	303	.pwm45_fixup = false,
aa3c668f	304	.has_ck_26m_sel = true,
967da67a	305	.reg_offset = mtk_pwm_reg_offset_v1,
424268c7 ZM	306	};
424268c7 ZM	307
2503781c	308	static const struct pwm_mediatek_of_data mt7623_pwm_data = {
424268c7	309	.num_pwms = 5,
360cc036	310	.pwm45_fixup = true,
0c0ead76	311	.has_ck_26m_sel = false,
967da67a	312	.reg_offset = mtk_pwm_reg_offset_v1,
8cdc43af JC	313	};
8cdc43af JC	314
2503781c	315	static const struct pwm_mediatek_of_data mt7628_pwm_data = {
8cdc43af JC	316	.num_pwms = 4,
8cdc43af JC	317	.pwm45_fixup = true,
0c0ead76	318	.has_ck_26m_sel = false,
967da67a	319	.reg_offset = mtk_pwm_reg_offset_v1,
424268c7 ZM	320	};
424268c7 ZM	321
715d14da SS	322	static const struct pwm_mediatek_of_data mt7629_pwm_data = {
	323	.num_pwms = 1,
	324	.pwm45_fixup = false,
0c0ead76	325	.has_ck_26m_sel = false,
967da67a	326	.reg_offset = mtk_pwm_reg_offset_v1,
715d14da SS	327	};
715d14da SS	328
967da67a DG	329	static const struct pwm_mediatek_of_data mt7981_pwm_data = {
967da67a DG	330	.num_pwms = 3,
8b2fbaed FP	331	.pwm45_fixup = false,
8b2fbaed FP	332	.has_ck_26m_sel = true,
967da67a	333	.reg_offset = mtk_pwm_reg_offset_v2,
8b2fbaed FP	334	};
8b2fbaed FP	335
967da67a DG	336	static const struct pwm_mediatek_of_data mt7986_pwm_data = {
967da67a DG	337	.num_pwms = 2,
394b5175 FP	338	.pwm45_fixup = false,
394b5175 FP	339	.has_ck_26m_sel = true,
967da67a	340	.reg_offset = mtk_pwm_reg_offset_v1,
394b5175 FP	341	};
394b5175 FP	342
eb58bf4a RM	343	static const struct pwm_mediatek_of_data mt7988_pwm_data = {
	344	.num_pwms = 8,
	345	.pwm45_fixup = false,
	346	.has_ck_26m_sel = false,
	347	.reg_offset = mtk_pwm_reg_offset_v2,
	348	};
	349
967da67a DG	350	static const struct pwm_mediatek_of_data mt8183_pwm_data = {
	351	.num_pwms = 4,
	352	.pwm45_fixup = false,
	353	.has_ck_26m_sel = true,
	354	.reg_offset = mtk_pwm_reg_offset_v1,
	355	};
	356
	357	static const struct pwm_mediatek_of_data mt8365_pwm_data = {
	358	.num_pwms = 3,
241eab76 DG	359	.pwm45_fixup = false,
241eab76 DG	360	.has_ck_26m_sel = true,
967da67a	361	.reg_offset = mtk_pwm_reg_offset_v1,
241eab76 DG	362	};
241eab76 DG	363
2503781c	364	static const struct pwm_mediatek_of_data mt8516_pwm_data = {
8d190728 FP	365	.num_pwms = 5,
8d190728 FP	366	.pwm45_fixup = false,
0c0ead76	367	.has_ck_26m_sel = true,
967da67a	368	.reg_offset = mtk_pwm_reg_offset_v1,
8d190728 FP	369	};
8d190728 FP	370
2503781c	371	static const struct of_device_id pwm_mediatek_of_match[] = {
424268c7	372	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
cb696e74	373	{ .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
424268c7 ZM	374	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
424268c7 ZM	375	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
8cdc43af	376	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
715d14da	377	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
967da67a	378	{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
241eab76	379	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
eb58bf4a	380	{ .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
8b2fbaed	381	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
394b5175	382	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
8d190728	383	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
424268c7	384	{ },
caf065f8	385	};
2503781c	386	MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
caf065f8	387
2503781c	388	static struct platform_driver pwm_mediatek_driver = {
caf065f8	389	.driver = {
2503781c SS	390	.name = "pwm-mediatek",
2503781c SS	391	.of_match_table = pwm_mediatek_of_match,
caf065f8	392	},
2503781c	393	.probe = pwm_mediatek_probe,
caf065f8	394	};
2503781c	395	module_platform_driver(pwm_mediatek_driver);
caf065f8 JC	396
caf065f8 JC	397	MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2c69747c	398	MODULE_DESCRIPTION("MediaTek general purpose Pulse Width Modulator driver");
4bea6dd5	399	MODULE_LICENSE("GPL v2");