pwm: lpss: Fix base_unit calculation for PWM frequency
[linux-block.git] / drivers / pwm / pwm-lpss.c
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1/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
093e00bb 9 * Author: Alan Cox <alan@linux.intel.com>
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10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
37670676 16#include <linux/delay.h>
e0c86a3b 17#include <linux/io.h>
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18#include <linux/kernel.h>
19#include <linux/module.h>
f080be27 20#include <linux/pm_runtime.h>
883e4d07 21#include <linux/time.h>
093e00bb 22
c558e39e 23#include "pwm-lpss.h"
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24
25#define PWM 0x00000000
26#define PWM_ENABLE BIT(31)
27#define PWM_SW_UPDATE BIT(30)
28#define PWM_BASE_UNIT_SHIFT 8
d16a5aa9 29#define PWM_ON_TIME_DIV_MASK 0x000000ff
d16a5aa9 30
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31/* Size of each PWM register space if multiple */
32#define PWM_SIZE 0x400
33
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34struct pwm_lpss_chip {
35 struct pwm_chip chip;
36 void __iomem *regs;
883e4d07 37 const struct pwm_lpss_boardinfo *info;
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38};
39
093e00bb 40/* BayTrail */
c558e39e 41const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
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42 .clk_rate = 25000000,
43 .npwm = 1,
883e4d07 44 .base_unit_bits = 16,
d16a5aa9 45};
c558e39e 46EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
d16a5aa9 47
373c5782 48/* Braswell */
c558e39e 49const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
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50 .clk_rate = 19200000,
51 .npwm = 1,
883e4d07 52 .base_unit_bits = 16,
373c5782 53};
c558e39e 54EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
373c5782 55
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56/* Broxton */
57const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
58 .clk_rate = 19200000,
59 .npwm = 4,
883e4d07 60 .base_unit_bits = 22,
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61};
62EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
63
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64static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
65{
66 return container_of(chip, struct pwm_lpss_chip, chip);
67}
68
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69static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
70{
71 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
72
73 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
74}
75
76static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
77{
78 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
79
80 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
81}
82
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83static void pwm_lpss_update(struct pwm_device *pwm)
84{
85 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
86 /* Give it some time to propagate */
87 usleep_range(10, 50);
88}
89
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90static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
91 int duty_ns, int period_ns)
92{
93 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
94 u8 on_time_div;
883e4d07 95 unsigned long c, base_unit_range;
96 unsigned long long base_unit, freq = NSEC_PER_SEC;
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97 u32 ctrl;
98
99 do_div(freq, period_ns);
100
883e4d07 101 /*
102 * The equation is:
e5ca4245 103 * base_unit = round(base_unit_range * freq / c)
883e4d07 104 */
105 base_unit_range = BIT(lpwm->info->base_unit_bits);
e5ca4245 106 freq *= base_unit_range;
d16a5aa9 107
883e4d07 108 c = lpwm->info->clk_rate;
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109 if (!c)
110 return -EINVAL;
111
e5ca4245 112 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
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113
114 if (duty_ns <= 0)
115 duty_ns = 1;
116 on_time_div = 255 - (255 * duty_ns / period_ns);
117
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118 pm_runtime_get_sync(chip->dev);
119
4e11f5ac 120 ctrl = pwm_lpss_read(pwm);
883e4d07 121 ctrl &= ~PWM_ON_TIME_DIV_MASK;
122 ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
123 base_unit &= (base_unit_range - 1);
124 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
d16a5aa9 125 ctrl |= on_time_div;
4e11f5ac 126 pwm_lpss_write(pwm, ctrl);
d16a5aa9 127
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128 /*
129 * If the PWM is already enabled we need to notify the hardware
130 * about the change by setting PWM_SW_UPDATE.
131 */
132 if (pwm_is_enabled(pwm))
133 pwm_lpss_update(pwm);
134
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135 pm_runtime_put(chip->dev);
136
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137 return 0;
138}
139
140static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
141{
f080be27 142 pm_runtime_get_sync(chip->dev);
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143
144 /*
145 * Hardware must first see PWM_SW_UPDATE before the PWM can be
146 * enabled.
147 */
148 pwm_lpss_update(pwm);
4e11f5ac 149 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
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150 return 0;
151}
152
153static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
154{
4e11f5ac 155 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
f080be27 156 pm_runtime_put(chip->dev);
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157}
158
159static const struct pwm_ops pwm_lpss_ops = {
160 .config = pwm_lpss_config,
161 .enable = pwm_lpss_enable,
162 .disable = pwm_lpss_disable,
163 .owner = THIS_MODULE,
164};
165
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166struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
167 const struct pwm_lpss_boardinfo *info)
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168{
169 struct pwm_lpss_chip *lpwm;
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170 int ret;
171
093e00bb 172 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
d16a5aa9 173 if (!lpwm)
093e00bb 174 return ERR_PTR(-ENOMEM);
d16a5aa9 175
093e00bb 176 lpwm->regs = devm_ioremap_resource(dev, r);
d16a5aa9 177 if (IS_ERR(lpwm->regs))
89c0339e 178 return ERR_CAST(lpwm->regs);
093e00bb 179
883e4d07 180 lpwm->info = info;
093e00bb 181 lpwm->chip.dev = dev;
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182 lpwm->chip.ops = &pwm_lpss_ops;
183 lpwm->chip.base = -1;
4e11f5ac 184 lpwm->chip.npwm = info->npwm;
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185
186 ret = pwmchip_add(&lpwm->chip);
187 if (ret) {
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188 dev_err(dev, "failed to add PWM chip: %d\n", ret);
189 return ERR_PTR(ret);
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190 }
191
093e00bb 192 return lpwm;
d16a5aa9 193}
c558e39e 194EXPORT_SYMBOL_GPL(pwm_lpss_probe);
d16a5aa9 195
c558e39e 196int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
d16a5aa9 197{
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198 return pwmchip_remove(&lpwm->chip);
199}
c558e39e 200EXPORT_SYMBOL_GPL(pwm_lpss_remove);
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201
202MODULE_DESCRIPTION("PWM driver for Intel LPSS");
203MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
204MODULE_LICENSE("GPL v2");