[linux-block.git] / drivers / pwm / pwm-lpss.c

/*
 * Intel Low Power Subsystem PWM controller driver
 *
 * Copyright (C) 2014, Intel Corporation
 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
 * Author: Alan Cox <alan@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/time.h>

#include "pwm-lpss.h"

#define PWM				0x00000000
#define PWM_ENABLE			BIT(31)
#define PWM_SW_UPDATE			BIT(30)
#define PWM_BASE_UNIT_SHIFT		8
#define PWM_ON_TIME_DIV_MASK		0x000000ff

/* Size of each PWM register space if multiple */
#define PWM_SIZE			0x400

static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
{
	return container_of(chip, struct pwm_lpss_chip, chip);
}

static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);

	return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
}

static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);

	writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
}

static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
	const unsigned int ms = 500 * USEC_PER_MSEC;
	u32 val;
	int err;

	/*
	 * PWM Configuration register has SW_UPDATE bit that is set when a new
	 * configuration is written to the register. The bit is automatically
	 * cleared at the start of the next output cycle by the IP block.
	 *
	 * If one writes a new configuration to the register while it still has
	 * the bit enabled, PWM may freeze. That is, while one can still write
	 * to the register, it won't have an effect. Thus, we try to sleep long
	 * enough that the bit gets cleared and make sure the bit is not
	 * enabled while we update the configuration.
	 */
	err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
	if (err)
		dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");

	return err;
}

static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
{
	return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
}

static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
			     int duty_ns, int period_ns)
{
	unsigned long long on_time_div;
	unsigned long c = lpwm->info->clk_rate, base_unit_range;
	unsigned long long base_unit, freq = NSEC_PER_SEC;
	u32 ctrl;

	do_div(freq, period_ns);

	/*
	 * The equation is:
	 * base_unit = round(base_unit_range * freq / c)
	 */
	base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
	freq *= base_unit_range;

	base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);

	on_time_div = 255ULL * duty_ns;
	do_div(on_time_div, period_ns);
	on_time_div = 255ULL - on_time_div;

	ctrl = pwm_lpss_read(pwm);
	ctrl &= ~PWM_ON_TIME_DIV_MASK;
	ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
	base_unit &= base_unit_range;
	ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
	ctrl |= on_time_div;
	pwm_lpss_write(pwm, ctrl);
}

static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
{
	if (cond)
		pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
}

static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			  struct pwm_state *state)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	int ret;

	if (state->enabled) {
		if (!pwm_is_enabled(pwm)) {
			pm_runtime_get_sync(chip->dev);
			ret = pwm_lpss_is_updating(pwm);
			if (ret) {
				pm_runtime_put(chip->dev);
				return ret;
			}
			pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
			pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
			pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
			ret = pwm_lpss_wait_for_update(pwm);
			if (ret) {
				pm_runtime_put(chip->dev);
				return ret;
			}
			pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
		} else {
			ret = pwm_lpss_is_updating(pwm);
			if (ret)
				return ret;
			pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
			pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
			return pwm_lpss_wait_for_update(pwm);
		}
	} else if (pwm_is_enabled(pwm)) {
		pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
		pm_runtime_put(chip->dev);
	}

	return 0;
}

static const struct pwm_ops pwm_lpss_ops = {
	.apply = pwm_lpss_apply,
	.owner = THIS_MODULE,
};

struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
				     const struct pwm_lpss_boardinfo *info)
{
	struct pwm_lpss_chip *lpwm;
	unsigned long c;
	int ret;

	if (WARN_ON(info->npwm > MAX_PWMS))
		return ERR_PTR(-ENODEV);

	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
	if (!lpwm)
		return ERR_PTR(-ENOMEM);

	lpwm->regs = devm_ioremap_resource(dev, r);
	if (IS_ERR(lpwm->regs))
		return ERR_CAST(lpwm->regs);

	lpwm->info = info;

	c = lpwm->info->clk_rate;
	if (!c)
		return ERR_PTR(-EINVAL);

	lpwm->chip.dev = dev;
	lpwm->chip.ops = &pwm_lpss_ops;
	lpwm->chip.base = -1;
	lpwm->chip.npwm = info->npwm;

	ret = pwmchip_add(&lpwm->chip);
	if (ret) {
		dev_err(dev, "failed to add PWM chip: %d\n", ret);
		return ERR_PTR(ret);
	}

	return lpwm;
}
EXPORT_SYMBOL_GPL(pwm_lpss_probe);

int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
{
	int i;

	for (i = 0; i < lpwm->info->npwm; i++) {
		if (pwm_is_enabled(&lpwm->chip.pwms[i]))
			pm_runtime_put(lpwm->chip.dev);
	}
	return pwmchip_remove(&lpwm->chip);
}
EXPORT_SYMBOL_GPL(pwm_lpss_remove);

int pwm_lpss_suspend(struct device *dev)
{
	struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
	int i;

	for (i = 0; i < lpwm->info->npwm; i++)
		lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);

	return 0;
}
EXPORT_SYMBOL_GPL(pwm_lpss_suspend);

int pwm_lpss_resume(struct device *dev)
{
	struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
	int i;

	for (i = 0; i < lpwm->info->npwm; i++)
		writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);

	return 0;
}
EXPORT_SYMBOL_GPL(pwm_lpss_resume);

MODULE_DESCRIPTION("PWM driver for Intel LPSS");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d16a5aa9 MW	1	/*
	2	* Intel Low Power Subsystem PWM controller driver
	3	*
	4	* Copyright (C) 2014, Intel Corporation
	5	* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
	6	* Author: Chew Kean Ho <kean.ho.chew@intel.com>
	7	* Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
	8	* Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
093e00bb	9	* Author: Alan Cox <alan@linux.intel.com>
d16a5aa9 MW	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
37670676	16	#include <linux/delay.h>
e0c86a3b	17	#include <linux/io.h>
10d56a4c	18	#include <linux/iopoll.h>
d16a5aa9 MW	19	#include <linux/kernel.h>
d16a5aa9 MW	20	#include <linux/module.h>
f080be27	21	#include <linux/pm_runtime.h>
883e4d07	22	#include <linux/time.h>
093e00bb	23
c558e39e	24	#include "pwm-lpss.h"
d16a5aa9 MW	25
	26	#define PWM 0x00000000
	27	#define PWM_ENABLE BIT(31)
	28	#define PWM_SW_UPDATE BIT(30)
	29	#define PWM_BASE_UNIT_SHIFT 8
d16a5aa9	30	#define PWM_ON_TIME_DIV_MASK 0x000000ff
d16a5aa9	31
4e11f5ac MW	32	/* Size of each PWM register space if multiple */
	33	#define PWM_SIZE 0x400
	34
d16a5aa9 MW	35	static inline struct pwm_lpss_chip to_lpwm(struct pwm_chip chip)
	36	{
	37	return container_of(chip, struct pwm_lpss_chip, chip);
	38	}
	39
4e11f5ac MW	40	static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
	41	{
	42	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	43
	44	return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
	45	}
	46
	47	static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
	48	{
	49	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	50
	51	writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
	52	}
	53
b997e3ed	54	static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
37670676	55	{
10d56a4c IK	56	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	57	const void __iomem addr = lpwm->regs + pwm->hwpwm PWM_SIZE + PWM;
	58	const unsigned int ms = 500 * USEC_PER_MSEC;
	59	u32 val;
	60	int err;
	61
b14e8cef	62	/*
10d56a4c IK	63	* PWM Configuration register has SW_UPDATE bit that is set when a new
	64	* configuration is written to the register. The bit is automatically
	65	* cleared at the start of the next output cycle by the IP block.
	66	*
	67	* If one writes a new configuration to the register while it still has
	68	* the bit enabled, PWM may freeze. That is, while one can still write
	69	* to the register, it won't have an effect. Thus, we try to sleep long
	70	* enough that the bit gets cleared and make sure the bit is not
	71	* enabled while we update the configuration.
b14e8cef	72	*/
10d56a4c IK	73	err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
	74	if (err)
	75	dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
b14e8cef	76
10d56a4c IK	77	return err;
	78	}
	79
	80	static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
	81	{
	82	return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
37670676 MW	83	}
37670676 MW	84
b14e8cef AS	85	static void pwm_lpss_prepare(struct pwm_lpss_chip lpwm, struct pwm_device pwm,
b14e8cef AS	86	int duty_ns, int period_ns)
d16a5aa9	87	{
ab248b60	88	unsigned long long on_time_div;
d9cd4a73	89	unsigned long c = lpwm->info->clk_rate, base_unit_range;
883e4d07	90	unsigned long long base_unit, freq = NSEC_PER_SEC;
d16a5aa9 MW	91	u32 ctrl;
	92
	93	do_div(freq, period_ns);
	94
883e4d07	95	/*
883e4d07	96	* The equation is:
e5ca4245	97	* base_unit = round(base_unit_range * freq / c)
883e4d07	98	*/
684309e5	99	base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
e5ca4245	100	freq *= base_unit_range;
d16a5aa9	101
e5ca4245	102	base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
d16a5aa9	103
ab248b60 MW	104	on_time_div = 255ULL * duty_ns;
	105	do_div(on_time_div, period_ns);
	106	on_time_div = 255ULL - on_time_div;
d16a5aa9	107
4e11f5ac	108	ctrl = pwm_lpss_read(pwm);
883e4d07	109	ctrl &= ~PWM_ON_TIME_DIV_MASK;
684309e5 AS	110	ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
684309e5 AS	111	base_unit &= base_unit_range;
883e4d07	112	ctrl \|= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
d16a5aa9	113	ctrl \|= on_time_div;
4e11f5ac	114	pwm_lpss_write(pwm, ctrl);
d16a5aa9 MW	115	}
d16a5aa9 MW	116
b997e3ed HG	117	static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
	118	{
	119	if (cond)
	120	pwm_lpss_write(pwm, pwm_lpss_read(pwm) \| PWM_ENABLE);
	121	}
	122
b14e8cef AS	123	static int pwm_lpss_apply(struct pwm_chip chip, struct pwm_device pwm,
b14e8cef AS	124	struct pwm_state *state)
d16a5aa9	125	{
b14e8cef	126	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
10d56a4c	127	int ret;
37670676	128
b14e8cef AS	129	if (state->enabled) {
	130	if (!pwm_is_enabled(pwm)) {
	131	pm_runtime_get_sync(chip->dev);
10d56a4c IK	132	ret = pwm_lpss_is_updating(pwm);
	133	if (ret) {
	134	pm_runtime_put(chip->dev);
	135	return ret;
	136	}
b14e8cef	137	pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
b997e3ed HG	138	pwm_lpss_write(pwm, pwm_lpss_read(pwm) \| PWM_SW_UPDATE);
	139	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
	140	ret = pwm_lpss_wait_for_update(pwm);
10d56a4c IK	141	if (ret) {
	142	pm_runtime_put(chip->dev);
	143	return ret;
	144	}
b997e3ed	145	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
b14e8cef	146	} else {
10d56a4c IK	147	ret = pwm_lpss_is_updating(pwm);
	148	if (ret)
	149	return ret;
b14e8cef	150	pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
b997e3ed HG	151	pwm_lpss_write(pwm, pwm_lpss_read(pwm) \| PWM_SW_UPDATE);
b997e3ed HG	152	return pwm_lpss_wait_for_update(pwm);
b14e8cef AS	153	}
	154	} else if (pwm_is_enabled(pwm)) {
	155	pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
	156	pm_runtime_put(chip->dev);
	157	}
d16a5aa9	158
b14e8cef	159	return 0;
d16a5aa9 MW	160	}
	161
	162	static const struct pwm_ops pwm_lpss_ops = {
b14e8cef	163	.apply = pwm_lpss_apply,
d16a5aa9 MW	164	.owner = THIS_MODULE,
	165	};
	166
c558e39e AS	167	struct pwm_lpss_chip pwm_lpss_probe(struct device dev, struct resource *r,
c558e39e AS	168	const struct pwm_lpss_boardinfo *info)
d16a5aa9 MW	169	{
d16a5aa9 MW	170	struct pwm_lpss_chip *lpwm;
d9cd4a73	171	unsigned long c;
d16a5aa9 MW	172	int ret;
d16a5aa9 MW	173
1d375b58 HG	174	if (WARN_ON(info->npwm > MAX_PWMS))
	175	return ERR_PTR(-ENODEV);
	176
093e00bb	177	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
d16a5aa9	178	if (!lpwm)
093e00bb	179	return ERR_PTR(-ENOMEM);
d16a5aa9	180
093e00bb	181	lpwm->regs = devm_ioremap_resource(dev, r);
d16a5aa9	182	if (IS_ERR(lpwm->regs))
89c0339e	183	return ERR_CAST(lpwm->regs);
093e00bb	184
883e4d07	185	lpwm->info = info;
d9cd4a73 AS	186
	187	c = lpwm->info->clk_rate;
	188	if (!c)
	189	return ERR_PTR(-EINVAL);
	190
093e00bb	191	lpwm->chip.dev = dev;
d16a5aa9 MW	192	lpwm->chip.ops = &pwm_lpss_ops;
d16a5aa9 MW	193	lpwm->chip.base = -1;
4e11f5ac	194	lpwm->chip.npwm = info->npwm;
d16a5aa9 MW	195
	196	ret = pwmchip_add(&lpwm->chip);
	197	if (ret) {
093e00bb AC	198	dev_err(dev, "failed to add PWM chip: %d\n", ret);
093e00bb AC	199	return ERR_PTR(ret);
d16a5aa9 MW	200	}
d16a5aa9 MW	201
093e00bb	202	return lpwm;
d16a5aa9	203	}
c558e39e	204	EXPORT_SYMBOL_GPL(pwm_lpss_probe);
d16a5aa9	205
c558e39e	206	int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
d16a5aa9	207	{
42885551 HG	208	int i;
	209
	210	for (i = 0; i < lpwm->info->npwm; i++) {
	211	if (pwm_is_enabled(&lpwm->chip.pwms[i]))
	212	pm_runtime_put(lpwm->chip.dev);
	213	}
d16a5aa9 MW	214	return pwmchip_remove(&lpwm->chip);
d16a5aa9 MW	215	}
c558e39e	216	EXPORT_SYMBOL_GPL(pwm_lpss_remove);
d16a5aa9	217
1d375b58 HG	218	int pwm_lpss_suspend(struct device *dev)
	219	{
	220	struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
	221	int i;
	222
	223	for (i = 0; i < lpwm->info->npwm; i++)
	224	lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
	225
	226	return 0;
	227	}
	228	EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
	229
	230	int pwm_lpss_resume(struct device *dev)
	231	{
	232	struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
	233	int i;
	234
	235	for (i = 0; i < lpwm->info->npwm; i++)
	236	writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
	237
	238	return 0;
	239	}
	240	EXPORT_SYMBOL_GPL(pwm_lpss_resume);
	241
d16a5aa9 MW	242	MODULE_DESCRIPTION("PWM driver for Intel LPSS");
	243	MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
	244	MODULE_LICENSE("GPL v2");