[linux-2.6-block.git] / drivers / pwm / pwm-lpss.c

/*
 * Intel Low Power Subsystem PWM controller driver
 *
 * Copyright (C) 2014, Intel Corporation
 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
 * Author: Alan Cox <alan@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>

#include "pwm-lpss.h"

#define PWM				0x00000000
#define PWM_ENABLE			BIT(31)
#define PWM_SW_UPDATE			BIT(30)
#define PWM_BASE_UNIT_SHIFT		8
#define PWM_BASE_UNIT_MASK		0x00ffff00
#define PWM_ON_TIME_DIV_MASK		0x000000ff
#define PWM_DIVISION_CORRECTION		0x2
#define PWM_LIMIT			(0x8000 + PWM_DIVISION_CORRECTION)
#define NSECS_PER_SEC			1000000000UL

struct pwm_lpss_chip {
	struct pwm_chip chip;
	void __iomem *regs;
	unsigned long clk_rate;
};

/* BayTrail */
const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
	.clk_rate = 25000000
};
EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);

/* Braswell */
const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
	.clk_rate = 19200000
};
EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);

static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
{
	return container_of(chip, struct pwm_lpss_chip, chip);
}

static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
			   int duty_ns, int period_ns)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	u8 on_time_div;
	unsigned long c;
	unsigned long long base_unit, freq = NSECS_PER_SEC;
	u32 ctrl;

	do_div(freq, period_ns);

	/* The equation is: base_unit = ((freq / c) * 65536) + correction */
	base_unit = freq * 65536;

	c = lpwm->clk_rate;
	if (!c)
		return -EINVAL;

	do_div(base_unit, c);
	base_unit += PWM_DIVISION_CORRECTION;
	if (base_unit > PWM_LIMIT)
		return -EINVAL;

	if (duty_ns <= 0)
		duty_ns = 1;
	on_time_div = 255 - (255 * duty_ns / period_ns);

	ctrl = readl(lpwm->regs + PWM);
	ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK);
	ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
	ctrl |= on_time_div;
	/* request PWM to update on next cycle */
	ctrl |= PWM_SW_UPDATE;
	writel(ctrl, lpwm->regs + PWM);

	return 0;
}

static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	u32 ctrl;

	ctrl = readl(lpwm->regs + PWM);
	writel(ctrl | PWM_ENABLE, lpwm->regs + PWM);

	return 0;
}

static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	u32 ctrl;

	ctrl = readl(lpwm->regs + PWM);
	writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
}

static const struct pwm_ops pwm_lpss_ops = {
	.config = pwm_lpss_config,
	.enable = pwm_lpss_enable,
	.disable = pwm_lpss_disable,
	.owner = THIS_MODULE,
};

struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
				     const struct pwm_lpss_boardinfo *info)
{
	struct pwm_lpss_chip *lpwm;
	int ret;

	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
	if (!lpwm)
		return ERR_PTR(-ENOMEM);

	lpwm->regs = devm_ioremap_resource(dev, r);
	if (IS_ERR(lpwm->regs))
		return ERR_CAST(lpwm->regs);

	lpwm->clk_rate = info->clk_rate;
	lpwm->chip.dev = dev;
	lpwm->chip.ops = &pwm_lpss_ops;
	lpwm->chip.base = -1;
	lpwm->chip.npwm = 1;

	ret = pwmchip_add(&lpwm->chip);
	if (ret) {
		dev_err(dev, "failed to add PWM chip: %d\n", ret);
		return ERR_PTR(ret);
	}

	return lpwm;
}
EXPORT_SYMBOL_GPL(pwm_lpss_probe);

int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
{
	u32 ctrl;

	ctrl = readl(lpwm->regs + PWM);
	writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);

	return pwmchip_remove(&lpwm->chip);
}
EXPORT_SYMBOL_GPL(pwm_lpss_remove);

MODULE_DESCRIPTION("PWM driver for Intel LPSS");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d16a5aa9 MW	1	/*
	2	* Intel Low Power Subsystem PWM controller driver
	3	*
	4	* Copyright (C) 2014, Intel Corporation
	5	* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
	6	* Author: Chew Kean Ho <kean.ho.chew@intel.com>
	7	* Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
	8	* Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
093e00bb	9	* Author: Alan Cox <alan@linux.intel.com>
d16a5aa9 MW	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
e0c86a3b	16	#include <linux/io.h>
d16a5aa9 MW	17	#include <linux/kernel.h>
d16a5aa9 MW	18	#include <linux/module.h>
093e00bb	19
c558e39e	20	#include "pwm-lpss.h"
d16a5aa9 MW	21
	22	#define PWM 0x00000000
	23	#define PWM_ENABLE BIT(31)
	24	#define PWM_SW_UPDATE BIT(30)
	25	#define PWM_BASE_UNIT_SHIFT 8
	26	#define PWM_BASE_UNIT_MASK 0x00ffff00
	27	#define PWM_ON_TIME_DIV_MASK 0x000000ff
	28	#define PWM_DIVISION_CORRECTION 0x2
	29	#define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION)
	30	#define NSECS_PER_SEC 1000000000UL
	31
	32	struct pwm_lpss_chip {
	33	struct pwm_chip chip;
	34	void __iomem *regs;
093e00bb AC	35	unsigned long clk_rate;
	36	};
	37
093e00bb	38	/* BayTrail */
c558e39e	39	const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
b2b7adeb	40	.clk_rate = 25000000
d16a5aa9	41	};
c558e39e	42	EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
d16a5aa9	43
373c5782	44	/* Braswell */
c558e39e	45	const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
b2b7adeb	46	.clk_rate = 19200000
373c5782	47	};
c558e39e	48	EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
373c5782	49
d16a5aa9 MW	50	static inline struct pwm_lpss_chip to_lpwm(struct pwm_chip chip)
	51	{
	52	return container_of(chip, struct pwm_lpss_chip, chip);
	53	}
	54
	55	static int pwm_lpss_config(struct pwm_chip chip, struct pwm_device pwm,
	56	int duty_ns, int period_ns)
	57	{
	58	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	59	u8 on_time_div;
	60	unsigned long c;
	61	unsigned long long base_unit, freq = NSECS_PER_SEC;
	62	u32 ctrl;
	63
	64	do_div(freq, period_ns);
	65
	66	/* The equation is: base_unit = ((freq / c) * 65536) + correction */
	67	base_unit = freq * 65536;
	68
093e00bb	69	c = lpwm->clk_rate;
d16a5aa9 MW	70	if (!c)
	71	return -EINVAL;
	72
	73	do_div(base_unit, c);
	74	base_unit += PWM_DIVISION_CORRECTION;
	75	if (base_unit > PWM_LIMIT)
	76	return -EINVAL;
	77
	78	if (duty_ns <= 0)
	79	duty_ns = 1;
	80	on_time_div = 255 - (255 * duty_ns / period_ns);
	81
	82	ctrl = readl(lpwm->regs + PWM);
	83	ctrl &= ~(PWM_BASE_UNIT_MASK \| PWM_ON_TIME_DIV_MASK);
	84	ctrl \|= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
	85	ctrl \|= on_time_div;
	86	/* request PWM to update on next cycle */
	87	ctrl \|= PWM_SW_UPDATE;
	88	writel(ctrl, lpwm->regs + PWM);
	89
	90	return 0;
	91	}
	92
	93	static int pwm_lpss_enable(struct pwm_chip chip, struct pwm_device pwm)
	94	{
	95	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	96	u32 ctrl;
d16a5aa9 MW	97
	98	ctrl = readl(lpwm->regs + PWM);
	99	writel(ctrl \| PWM_ENABLE, lpwm->regs + PWM);
	100
	101	return 0;
	102	}
	103
	104	static void pwm_lpss_disable(struct pwm_chip chip, struct pwm_device pwm)
	105	{
	106	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	107	u32 ctrl;
	108
	109	ctrl = readl(lpwm->regs + PWM);
	110	writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
d16a5aa9 MW	111	}
	112
	113	static const struct pwm_ops pwm_lpss_ops = {
	114	.config = pwm_lpss_config,
	115	.enable = pwm_lpss_enable,
	116	.disable = pwm_lpss_disable,
	117	.owner = THIS_MODULE,
	118	};
	119
c558e39e AS	120	struct pwm_lpss_chip pwm_lpss_probe(struct device dev, struct resource *r,
c558e39e AS	121	const struct pwm_lpss_boardinfo *info)
d16a5aa9 MW	122	{
d16a5aa9 MW	123	struct pwm_lpss_chip *lpwm;
d16a5aa9 MW	124	int ret;
d16a5aa9 MW	125
093e00bb	126	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
d16a5aa9	127	if (!lpwm)
093e00bb	128	return ERR_PTR(-ENOMEM);
d16a5aa9	129
093e00bb	130	lpwm->regs = devm_ioremap_resource(dev, r);
d16a5aa9	131	if (IS_ERR(lpwm->regs))
89c0339e	132	return ERR_CAST(lpwm->regs);
093e00bb	133
65accd87	134	lpwm->clk_rate = info->clk_rate;
093e00bb	135	lpwm->chip.dev = dev;
d16a5aa9 MW	136	lpwm->chip.ops = &pwm_lpss_ops;
	137	lpwm->chip.base = -1;
	138	lpwm->chip.npwm = 1;
	139
	140	ret = pwmchip_add(&lpwm->chip);
	141	if (ret) {
093e00bb AC	142	dev_err(dev, "failed to add PWM chip: %d\n", ret);
093e00bb AC	143	return ERR_PTR(ret);
d16a5aa9 MW	144	}
d16a5aa9 MW	145
093e00bb	146	return lpwm;
d16a5aa9	147	}
c558e39e	148	EXPORT_SYMBOL_GPL(pwm_lpss_probe);
d16a5aa9	149
c558e39e	150	int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
d16a5aa9	151	{
d16a5aa9 MW	152	u32 ctrl;
	153
	154	ctrl = readl(lpwm->regs + PWM);
	155	writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
	156
	157	return pwmchip_remove(&lpwm->chip);
	158	}
c558e39e	159	EXPORT_SYMBOL_GPL(pwm_lpss_remove);
d16a5aa9 MW	160
	161	MODULE_DESCRIPTION("PWM driver for Intel LPSS");
	162	MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
	163	MODULE_LICENSE("GPL v2");