Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[linux-2.6-block.git] / drivers / pwm / pwm-lpss.c
CommitLineData
d16a5aa9
MW
1/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
093e00bb 9 * Author: Alan Cox <alan@linux.intel.com>
d16a5aa9
MW
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
37670676 16#include <linux/delay.h>
e0c86a3b 17#include <linux/io.h>
d16a5aa9
MW
18#include <linux/kernel.h>
19#include <linux/module.h>
f080be27 20#include <linux/pm_runtime.h>
883e4d07 21#include <linux/time.h>
093e00bb 22
c558e39e 23#include "pwm-lpss.h"
d16a5aa9
MW
24
25#define PWM 0x00000000
26#define PWM_ENABLE BIT(31)
27#define PWM_SW_UPDATE BIT(30)
28#define PWM_BASE_UNIT_SHIFT 8
d16a5aa9 29#define PWM_ON_TIME_DIV_MASK 0x000000ff
d16a5aa9 30
4e11f5ac
MW
31/* Size of each PWM register space if multiple */
32#define PWM_SIZE 0x400
33
d16a5aa9
MW
34struct pwm_lpss_chip {
35 struct pwm_chip chip;
36 void __iomem *regs;
883e4d07 37 const struct pwm_lpss_boardinfo *info;
093e00bb
AC
38};
39
093e00bb 40/* BayTrail */
c558e39e 41const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
4e11f5ac
MW
42 .clk_rate = 25000000,
43 .npwm = 1,
883e4d07 44 .base_unit_bits = 16,
d16a5aa9 45};
c558e39e 46EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
d16a5aa9 47
373c5782 48/* Braswell */
c558e39e 49const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
4e11f5ac
MW
50 .clk_rate = 19200000,
51 .npwm = 1,
883e4d07 52 .base_unit_bits = 16,
373c5782 53};
c558e39e 54EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
373c5782 55
87219cb4
MW
56/* Broxton */
57const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
58 .clk_rate = 19200000,
59 .npwm = 4,
883e4d07 60 .base_unit_bits = 22,
87219cb4
MW
61};
62EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
63
d16a5aa9
MW
64static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
65{
66 return container_of(chip, struct pwm_lpss_chip, chip);
67}
68
4e11f5ac
MW
69static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
70{
71 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
72
73 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
74}
75
76static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
77{
78 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
79
80 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
81}
82
37670676
MW
83static void pwm_lpss_update(struct pwm_device *pwm)
84{
85 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
86 /* Give it some time to propagate */
87 usleep_range(10, 50);
88}
89
d16a5aa9
MW
90static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
91 int duty_ns, int period_ns)
92{
93 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
ab248b60 94 unsigned long long on_time_div;
d9cd4a73 95 unsigned long c = lpwm->info->clk_rate, base_unit_range;
883e4d07 96 unsigned long long base_unit, freq = NSEC_PER_SEC;
d16a5aa9
MW
97 u32 ctrl;
98
99 do_div(freq, period_ns);
100
883e4d07 101 /*
102 * The equation is:
e5ca4245 103 * base_unit = round(base_unit_range * freq / c)
883e4d07 104 */
105 base_unit_range = BIT(lpwm->info->base_unit_bits);
e5ca4245 106 freq *= base_unit_range;
d16a5aa9 107
e5ca4245 108 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
d16a5aa9
MW
109
110 if (duty_ns <= 0)
111 duty_ns = 1;
ab248b60
MW
112 on_time_div = 255ULL * duty_ns;
113 do_div(on_time_div, period_ns);
114 on_time_div = 255ULL - on_time_div;
d16a5aa9 115
f080be27
QZ
116 pm_runtime_get_sync(chip->dev);
117
4e11f5ac 118 ctrl = pwm_lpss_read(pwm);
883e4d07 119 ctrl &= ~PWM_ON_TIME_DIV_MASK;
120 ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
121 base_unit &= (base_unit_range - 1);
122 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
d16a5aa9 123 ctrl |= on_time_div;
4e11f5ac 124 pwm_lpss_write(pwm, ctrl);
d16a5aa9 125
37670676
MW
126 /*
127 * If the PWM is already enabled we need to notify the hardware
128 * about the change by setting PWM_SW_UPDATE.
129 */
130 if (pwm_is_enabled(pwm))
131 pwm_lpss_update(pwm);
132
f080be27
QZ
133 pm_runtime_put(chip->dev);
134
d16a5aa9
MW
135 return 0;
136}
137
138static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
139{
f080be27 140 pm_runtime_get_sync(chip->dev);
37670676
MW
141
142 /*
143 * Hardware must first see PWM_SW_UPDATE before the PWM can be
144 * enabled.
145 */
146 pwm_lpss_update(pwm);
4e11f5ac 147 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
d16a5aa9
MW
148 return 0;
149}
150
151static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
152{
4e11f5ac 153 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
f080be27 154 pm_runtime_put(chip->dev);
d16a5aa9
MW
155}
156
157static const struct pwm_ops pwm_lpss_ops = {
158 .config = pwm_lpss_config,
159 .enable = pwm_lpss_enable,
160 .disable = pwm_lpss_disable,
161 .owner = THIS_MODULE,
162};
163
c558e39e
AS
164struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
165 const struct pwm_lpss_boardinfo *info)
d16a5aa9
MW
166{
167 struct pwm_lpss_chip *lpwm;
d9cd4a73 168 unsigned long c;
d16a5aa9
MW
169 int ret;
170
093e00bb 171 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
d16a5aa9 172 if (!lpwm)
093e00bb 173 return ERR_PTR(-ENOMEM);
d16a5aa9 174
093e00bb 175 lpwm->regs = devm_ioremap_resource(dev, r);
d16a5aa9 176 if (IS_ERR(lpwm->regs))
89c0339e 177 return ERR_CAST(lpwm->regs);
093e00bb 178
883e4d07 179 lpwm->info = info;
d9cd4a73
AS
180
181 c = lpwm->info->clk_rate;
182 if (!c)
183 return ERR_PTR(-EINVAL);
184
093e00bb 185 lpwm->chip.dev = dev;
d16a5aa9
MW
186 lpwm->chip.ops = &pwm_lpss_ops;
187 lpwm->chip.base = -1;
4e11f5ac 188 lpwm->chip.npwm = info->npwm;
d16a5aa9
MW
189
190 ret = pwmchip_add(&lpwm->chip);
191 if (ret) {
093e00bb
AC
192 dev_err(dev, "failed to add PWM chip: %d\n", ret);
193 return ERR_PTR(ret);
d16a5aa9
MW
194 }
195
093e00bb 196 return lpwm;
d16a5aa9 197}
c558e39e 198EXPORT_SYMBOL_GPL(pwm_lpss_probe);
d16a5aa9 199
c558e39e 200int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
d16a5aa9 201{
d16a5aa9
MW
202 return pwmchip_remove(&lpwm->chip);
203}
c558e39e 204EXPORT_SYMBOL_GPL(pwm_lpss_remove);
d16a5aa9
MW
205
206MODULE_DESCRIPTION("PWM driver for Intel LPSS");
207MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
208MODULE_LICENSE("GPL v2");