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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d16a5aa9 MW |
2 | /* |
3 | * Intel Low Power Subsystem PWM controller driver | |
4 | * | |
5 | * Copyright (C) 2014, Intel Corporation | |
6 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> | |
7 | * Author: Chew Kean Ho <kean.ho.chew@intel.com> | |
8 | * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> | |
9 | * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> | |
093e00bb | 10 | * Author: Alan Cox <alan@linux.intel.com> |
d16a5aa9 MW |
11 | */ |
12 | ||
37670676 | 13 | #include <linux/delay.h> |
e0c86a3b | 14 | #include <linux/io.h> |
10d56a4c | 15 | #include <linux/iopoll.h> |
d16a5aa9 MW |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> | |
f080be27 | 18 | #include <linux/pm_runtime.h> |
883e4d07 | 19 | #include <linux/time.h> |
093e00bb | 20 | |
c558e39e | 21 | #include "pwm-lpss.h" |
d16a5aa9 MW |
22 | |
23 | #define PWM 0x00000000 | |
24 | #define PWM_ENABLE BIT(31) | |
25 | #define PWM_SW_UPDATE BIT(30) | |
26 | #define PWM_BASE_UNIT_SHIFT 8 | |
d16a5aa9 | 27 | #define PWM_ON_TIME_DIV_MASK 0x000000ff |
d16a5aa9 | 28 | |
4e11f5ac MW |
29 | /* Size of each PWM register space if multiple */ |
30 | #define PWM_SIZE 0x400 | |
31 | ||
d16a5aa9 MW |
32 | static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) |
33 | { | |
34 | return container_of(chip, struct pwm_lpss_chip, chip); | |
35 | } | |
36 | ||
4e11f5ac MW |
37 | static inline u32 pwm_lpss_read(const struct pwm_device *pwm) |
38 | { | |
39 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); | |
40 | ||
41 | return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); | |
42 | } | |
43 | ||
44 | static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) | |
45 | { | |
46 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); | |
47 | ||
48 | writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); | |
49 | } | |
50 | ||
b997e3ed | 51 | static int pwm_lpss_wait_for_update(struct pwm_device *pwm) |
37670676 | 52 | { |
10d56a4c IK |
53 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); |
54 | const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM; | |
55 | const unsigned int ms = 500 * USEC_PER_MSEC; | |
56 | u32 val; | |
57 | int err; | |
58 | ||
b14e8cef | 59 | /* |
10d56a4c IK |
60 | * PWM Configuration register has SW_UPDATE bit that is set when a new |
61 | * configuration is written to the register. The bit is automatically | |
62 | * cleared at the start of the next output cycle by the IP block. | |
63 | * | |
64 | * If one writes a new configuration to the register while it still has | |
65 | * the bit enabled, PWM may freeze. That is, while one can still write | |
66 | * to the register, it won't have an effect. Thus, we try to sleep long | |
67 | * enough that the bit gets cleared and make sure the bit is not | |
68 | * enabled while we update the configuration. | |
b14e8cef | 69 | */ |
10d56a4c IK |
70 | err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms); |
71 | if (err) | |
72 | dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n"); | |
b14e8cef | 73 | |
10d56a4c IK |
74 | return err; |
75 | } | |
76 | ||
77 | static inline int pwm_lpss_is_updating(struct pwm_device *pwm) | |
78 | { | |
d58560e6 HG |
79 | if (pwm_lpss_read(pwm) & PWM_SW_UPDATE) { |
80 | dev_err(pwm->chip->dev, "PWM_SW_UPDATE is still set, skipping update\n"); | |
81 | return -EBUSY; | |
82 | } | |
83 | ||
84 | return 0; | |
37670676 MW |
85 | } |
86 | ||
b14e8cef AS |
87 | static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, |
88 | int duty_ns, int period_ns) | |
d16a5aa9 | 89 | { |
ab248b60 | 90 | unsigned long long on_time_div; |
d9cd4a73 | 91 | unsigned long c = lpwm->info->clk_rate, base_unit_range; |
883e4d07 | 92 | unsigned long long base_unit, freq = NSEC_PER_SEC; |
d6d54bac | 93 | u32 ctrl; |
d16a5aa9 MW |
94 | |
95 | do_div(freq, period_ns); | |
96 | ||
883e4d07 | 97 | /* |
98 | * The equation is: | |
e5ca4245 | 99 | * base_unit = round(base_unit_range * freq / c) |
883e4d07 | 100 | */ |
181f4d2f | 101 | base_unit_range = BIT(lpwm->info->base_unit_bits); |
e5ca4245 | 102 | freq *= base_unit_range; |
d16a5aa9 | 103 | |
e5ca4245 | 104 | base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); |
ef9f60da HG |
105 | /* base_unit must not be 0 and we also want to avoid overflowing it */ |
106 | base_unit = clamp_val(base_unit, 1, base_unit_range - 1); | |
d16a5aa9 | 107 | |
ab248b60 MW |
108 | on_time_div = 255ULL * duty_ns; |
109 | do_div(on_time_div, period_ns); | |
110 | on_time_div = 255ULL - on_time_div; | |
d16a5aa9 | 111 | |
d6d54bac | 112 | ctrl = pwm_lpss_read(pwm); |
883e4d07 | 113 | ctrl &= ~PWM_ON_TIME_DIV_MASK; |
181f4d2f | 114 | ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); |
883e4d07 | 115 | ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; |
d16a5aa9 | 116 | ctrl |= on_time_div; |
2153bbc1 | 117 | |
d6d54bac HG |
118 | pwm_lpss_write(pwm, ctrl); |
119 | pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE); | |
d16a5aa9 MW |
120 | } |
121 | ||
b997e3ed HG |
122 | static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond) |
123 | { | |
124 | if (cond) | |
125 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); | |
126 | } | |
127 | ||
092d83e3 HG |
128 | static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm, |
129 | struct pwm_device *pwm, | |
d6d54bac | 130 | const struct pwm_state *state) |
092d83e3 HG |
131 | { |
132 | int ret; | |
133 | ||
134 | ret = pwm_lpss_is_updating(pwm); | |
135 | if (ret) | |
136 | return ret; | |
137 | ||
138 | pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); | |
d6d54bac | 139 | pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false); |
092d83e3 HG |
140 | ret = pwm_lpss_wait_for_update(pwm); |
141 | if (ret) | |
142 | return ret; | |
143 | ||
d6d54bac | 144 | pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true); |
092d83e3 HG |
145 | return 0; |
146 | } | |
147 | ||
b14e8cef | 148 | static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
71523d18 | 149 | const struct pwm_state *state) |
d16a5aa9 | 150 | { |
b14e8cef | 151 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
092d83e3 | 152 | int ret = 0; |
37670676 | 153 | |
b14e8cef AS |
154 | if (state->enabled) { |
155 | if (!pwm_is_enabled(pwm)) { | |
156 | pm_runtime_get_sync(chip->dev); | |
d6d54bac | 157 | ret = pwm_lpss_prepare_enable(lpwm, pwm, state); |
092d83e3 | 158 | if (ret) |
10d56a4c | 159 | pm_runtime_put(chip->dev); |
b14e8cef | 160 | } else { |
d6d54bac | 161 | ret = pwm_lpss_prepare_enable(lpwm, pwm, state); |
b14e8cef AS |
162 | } |
163 | } else if (pwm_is_enabled(pwm)) { | |
164 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); | |
165 | pm_runtime_put(chip->dev); | |
166 | } | |
d16a5aa9 | 167 | |
092d83e3 | 168 | return ret; |
d16a5aa9 MW |
169 | } |
170 | ||
280fec4c HG |
171 | static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm, |
172 | struct pwm_state *state) | |
173 | { | |
174 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); | |
175 | unsigned long base_unit_range; | |
176 | unsigned long long base_unit, freq, on_time_div; | |
177 | u32 ctrl; | |
178 | ||
01aa905d HG |
179 | pm_runtime_get_sync(chip->dev); |
180 | ||
280fec4c HG |
181 | base_unit_range = BIT(lpwm->info->base_unit_bits); |
182 | ||
183 | ctrl = pwm_lpss_read(pwm); | |
184 | on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK); | |
185 | base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1); | |
186 | ||
187 | freq = base_unit * lpwm->info->clk_rate; | |
188 | do_div(freq, base_unit_range); | |
189 | if (freq == 0) | |
190 | state->period = NSEC_PER_SEC; | |
191 | else | |
192 | state->period = NSEC_PER_SEC / (unsigned long)freq; | |
193 | ||
194 | on_time_div *= state->period; | |
195 | do_div(on_time_div, 255); | |
196 | state->duty_cycle = on_time_div; | |
197 | ||
198 | state->polarity = PWM_POLARITY_NORMAL; | |
199 | state->enabled = !!(ctrl & PWM_ENABLE); | |
200 | ||
01aa905d | 201 | pm_runtime_put(chip->dev); |
280fec4c HG |
202 | } |
203 | ||
d16a5aa9 | 204 | static const struct pwm_ops pwm_lpss_ops = { |
b14e8cef | 205 | .apply = pwm_lpss_apply, |
280fec4c | 206 | .get_state = pwm_lpss_get_state, |
d16a5aa9 MW |
207 | .owner = THIS_MODULE, |
208 | }; | |
209 | ||
c558e39e AS |
210 | struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, |
211 | const struct pwm_lpss_boardinfo *info) | |
d16a5aa9 MW |
212 | { |
213 | struct pwm_lpss_chip *lpwm; | |
d9cd4a73 | 214 | unsigned long c; |
01aa905d HG |
215 | int i, ret; |
216 | u32 ctrl; | |
d16a5aa9 | 217 | |
1d375b58 HG |
218 | if (WARN_ON(info->npwm > MAX_PWMS)) |
219 | return ERR_PTR(-ENODEV); | |
220 | ||
093e00bb | 221 | lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); |
d16a5aa9 | 222 | if (!lpwm) |
093e00bb | 223 | return ERR_PTR(-ENOMEM); |
d16a5aa9 | 224 | |
093e00bb | 225 | lpwm->regs = devm_ioremap_resource(dev, r); |
d16a5aa9 | 226 | if (IS_ERR(lpwm->regs)) |
89c0339e | 227 | return ERR_CAST(lpwm->regs); |
093e00bb | 228 | |
883e4d07 | 229 | lpwm->info = info; |
d9cd4a73 AS |
230 | |
231 | c = lpwm->info->clk_rate; | |
232 | if (!c) | |
233 | return ERR_PTR(-EINVAL); | |
234 | ||
093e00bb | 235 | lpwm->chip.dev = dev; |
d16a5aa9 | 236 | lpwm->chip.ops = &pwm_lpss_ops; |
4e11f5ac | 237 | lpwm->chip.npwm = info->npwm; |
d16a5aa9 MW |
238 | |
239 | ret = pwmchip_add(&lpwm->chip); | |
240 | if (ret) { | |
093e00bb AC |
241 | dev_err(dev, "failed to add PWM chip: %d\n", ret); |
242 | return ERR_PTR(ret); | |
d16a5aa9 MW |
243 | } |
244 | ||
01aa905d HG |
245 | for (i = 0; i < lpwm->info->npwm; i++) { |
246 | ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]); | |
247 | if (ctrl & PWM_ENABLE) | |
248 | pm_runtime_get(dev); | |
249 | } | |
250 | ||
093e00bb | 251 | return lpwm; |
d16a5aa9 | 252 | } |
c558e39e | 253 | EXPORT_SYMBOL_GPL(pwm_lpss_probe); |
d16a5aa9 | 254 | |
c558e39e | 255 | int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) |
d16a5aa9 | 256 | { |
d16a5aa9 MW |
257 | return pwmchip_remove(&lpwm->chip); |
258 | } | |
c558e39e | 259 | EXPORT_SYMBOL_GPL(pwm_lpss_remove); |
d16a5aa9 MW |
260 | |
261 | MODULE_DESCRIPTION("PWM driver for Intel LPSS"); | |
262 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); | |
263 | MODULE_LICENSE("GPL v2"); |