[linux-2.6-block.git] / drivers / pwm / pwm-lpc32xx.c

/*
 * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2.
 *
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

struct lpc32xx_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
};

#define PWM_ENABLE	BIT(31)

#define to_lpc32xx_pwm_chip(_chip) \
	container_of(_chip, struct lpc32xx_pwm_chip, chip)

static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			      int duty_ns, int period_ns)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	unsigned long long c;
	int period_cycles, duty_cycles;
	u32 val;
	c = clk_get_rate(lpc32xx->clk);

	/* The highest acceptable divisor is 256, which is represented by 0 */
	period_cycles = div64_u64(c * period_ns,
			       (unsigned long long)NSEC_PER_SEC * 256);
	if (!period_cycles || period_cycles > 256)
		return -ERANGE;
	if (period_cycles == 256)
		period_cycles = 0;

	/* Compute 256 x #duty/period value and care for corner cases */
	duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
				period_ns);
	if (!duty_cycles)
		duty_cycles = 1;
	if (duty_cycles > 255)
		duty_cycles = 255;

	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	val &= ~0xFFFF;
	val |= (period_cycles << 8) | duty_cycles;
	writel(val, lpc32xx->base + (pwm->hwpwm << 2));

	return 0;
}

static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	u32 val;
	int ret;

	ret = clk_prepare_enable(lpc32xx->clk);
	if (ret)
		return ret;

	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	val |= PWM_ENABLE;
	writel(val, lpc32xx->base + (pwm->hwpwm << 2));

	return 0;
}

static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	u32 val;

	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	val &= ~PWM_ENABLE;
	writel(val, lpc32xx->base + (pwm->hwpwm << 2));

	clk_disable_unprepare(lpc32xx->clk);
}

static const struct pwm_ops lpc32xx_pwm_ops = {
	.config = lpc32xx_pwm_config,
	.enable = lpc32xx_pwm_enable,
	.disable = lpc32xx_pwm_disable,
	.owner = THIS_MODULE,
};

static int lpc32xx_pwm_probe(struct platform_device *pdev)
{
	struct lpc32xx_pwm_chip *lpc32xx;
	struct resource *res;
	int ret;

	lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
	if (!lpc32xx)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(lpc32xx->base))
		return PTR_ERR(lpc32xx->base);

	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(lpc32xx->clk))
		return PTR_ERR(lpc32xx->clk);

	lpc32xx->chip.dev = &pdev->dev;
	lpc32xx->chip.ops = &lpc32xx_pwm_ops;
	lpc32xx->chip.npwm = 1;
	lpc32xx->chip.base = -1;

	ret = pwmchip_add(&lpc32xx->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, lpc32xx);

	return 0;
}

static int lpc32xx_pwm_remove(struct platform_device *pdev)
{
	struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
	unsigned int i;

	for (i = 0; i < lpc32xx->chip.npwm; i++)
		pwm_disable(&lpc32xx->chip.pwms[i]);

	return pwmchip_remove(&lpc32xx->chip);
}

static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
	{ .compatible = "nxp,lpc3220-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);

static struct platform_driver lpc32xx_pwm_driver = {
	.driver = {
		.name = "lpc32xx-pwm",
		.of_match_table = lpc32xx_pwm_dt_ids,
	},
	.probe = lpc32xx_pwm_probe,
	.remove = lpc32xx_pwm_remove,
};
module_platform_driver(lpc32xx_pwm_driver);

MODULE_ALIAS("platform:lpc32xx-pwm");
MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
MODULE_DESCRIPTION("LPC32XX PWM Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2132fa8d APS	1	/*
	2	* Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; version 2.
	7	*
	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/err.h>
	12	#include <linux/io.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pwm.h>
	19	#include <linux/slab.h>
	20
	21	struct lpc32xx_pwm_chip {
	22	struct pwm_chip chip;
	23	struct clk *clk;
	24	void __iomem *base;
	25	};
	26
5a9fc9c6	27	#define PWM_ENABLE BIT(31)
2132fa8d APS	28
	29	#define to_lpc32xx_pwm_chip(_chip) \
	30	container_of(_chip, struct lpc32xx_pwm_chip, chip)
	31
	32	static int lpc32xx_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	33	int duty_ns, int period_ns)
	34	{
	35	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	36	unsigned long long c;
	37	int period_cycles, duty_cycles;
affb923d	38	u32 val;
5a9fc9c6	39	c = clk_get_rate(lpc32xx->clk);
2132fa8d	40
5a9fc9c6 VZ	41	/* The highest acceptable divisor is 256, which is represented by 0 */
	42	period_cycles = div64_u64(c * period_ns,
	43	(unsigned long long)NSEC_PER_SEC * 256);
d6dbdf0d VZ	44	if (!period_cycles \|\| period_cycles > 256)
	45	return -ERANGE;
	46	if (period_cycles == 256)
5a9fc9c6	47	period_cycles = 0;
2132fa8d	48
5a9fc9c6 VZ	49	/* Compute 256 x #duty/period value and care for corner cases */
	50	duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
	51	period_ns);
	52	if (!duty_cycles)
	53	duty_cycles = 1;
	54	if (duty_cycles > 255)
	55	duty_cycles = 255;
2132fa8d	56
affb923d AL	57	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
affb923d AL	58	val &= ~0xFFFF;
5a9fc9c6	59	val \|= (period_cycles << 8) \| duty_cycles;
affb923d	60	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
2132fa8d APS	61
	62	return 0;
	63	}
	64
	65	static int lpc32xx_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	66	{
	67	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
08ee77b5 AL	68	u32 val;
	69	int ret;
	70
82aff048	71	ret = clk_prepare_enable(lpc32xx->clk);
08ee77b5 AL	72	if (ret)
	73	return ret;
	74
	75	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	76	val \|= PWM_ENABLE;
	77	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
2132fa8d	78
08ee77b5	79	return 0;
2132fa8d APS	80	}
	81
	82	static void lpc32xx_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	83	{
	84	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
08ee77b5 AL	85	u32 val;
	86
	87	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
	88	val &= ~PWM_ENABLE;
	89	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
2132fa8d	90
82aff048	91	clk_disable_unprepare(lpc32xx->clk);
2132fa8d APS	92	}
	93
	94	static const struct pwm_ops lpc32xx_pwm_ops = {
	95	.config = lpc32xx_pwm_config,
	96	.enable = lpc32xx_pwm_enable,
	97	.disable = lpc32xx_pwm_disable,
	98	.owner = THIS_MODULE,
	99	};
	100
	101	static int lpc32xx_pwm_probe(struct platform_device *pdev)
	102	{
	103	struct lpc32xx_pwm_chip *lpc32xx;
	104	struct resource *res;
	105	int ret;
	106
	107	lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
	108	if (!lpc32xx)
	109	return -ENOMEM;
	110
	111	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6d4294d1 TR	112	lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
	113	if (IS_ERR(lpc32xx->base))
	114	return PTR_ERR(lpc32xx->base);
2132fa8d APS	115
	116	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
	117	if (IS_ERR(lpc32xx->clk))
	118	return PTR_ERR(lpc32xx->clk);
	119
	120	lpc32xx->chip.dev = &pdev->dev;
	121	lpc32xx->chip.ops = &lpc32xx_pwm_ops;
ebe1fca3	122	lpc32xx->chip.npwm = 1;
8fc6d09d	123	lpc32xx->chip.base = -1;
2132fa8d APS	124
	125	ret = pwmchip_add(&lpc32xx->chip);
	126	if (ret < 0) {
	127	dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
	128	return ret;
	129	}
	130
	131	platform_set_drvdata(pdev, lpc32xx);
	132
	133	return 0;
	134	}
	135
77f37917	136	static int lpc32xx_pwm_remove(struct platform_device *pdev)
2132fa8d APS	137	{
2132fa8d APS	138	struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
54b2a999 AB	139	unsigned int i;
	140
	141	for (i = 0; i < lpc32xx->chip.npwm; i++)
	142	pwm_disable(&lpc32xx->chip.pwms[i]);
2132fa8d	143
2132fa8d APS	144	return pwmchip_remove(&lpc32xx->chip);
	145	}
	146
f1a8870a	147	static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
2132fa8d APS	148	{ .compatible = "nxp,lpc3220-pwm", },
	149	{ /* sentinel */ }
	150	};
	151	MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
	152
	153	static struct platform_driver lpc32xx_pwm_driver = {
	154	.driver = {
	155	.name = "lpc32xx-pwm",
3cb3b2bf	156	.of_match_table = lpc32xx_pwm_dt_ids,
2132fa8d APS	157	},
2132fa8d APS	158	.probe = lpc32xx_pwm_probe,
fd109112	159	.remove = lpc32xx_pwm_remove,
2132fa8d APS	160	};
	161	module_platform_driver(lpc32xx_pwm_driver);
	162
	163	MODULE_ALIAS("platform:lpc32xx-pwm");
	164	MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
	165	MODULE_DESCRIPTION("LPC32XX PWM Driver");
	166	MODULE_LICENSE("GPL v2");