[linux-2.6-block.git] / drivers / pwm / pwm-lpc32xx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

struct lpc32xx_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
};

#define PWM_ENABLE	BIT(31)
#define PWM_PIN_LEVEL	BIT(30)

#define to_lpc32xx_pwm_chip(_chip) \
	container_of(_chip, struct lpc32xx_pwm_chip, chip)

static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			      int duty_ns, int period_ns)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	unsigned long long c;
	int period_cycles, duty_cycles;
	u32 val;
	c = clk_get_rate(lpc32xx->clk);

	/* The highest acceptable divisor is 256, which is represented by 0 */
	period_cycles = div64_u64(c * period_ns,
			       (unsigned long long)NSEC_PER_SEC * 256);
	if (!period_cycles || period_cycles > 256)
		return -ERANGE;
	if (period_cycles == 256)
		period_cycles = 0;

	/* Compute 256 x #duty/period value and care for corner cases */
	duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
				period_ns);
	if (!duty_cycles)
		duty_cycles = 1;
	if (duty_cycles > 255)
		duty_cycles = 255;

	val = readl(lpc32xx->base);
	val &= ~0xFFFF;
	val |= (period_cycles << 8) | duty_cycles;
	writel(val, lpc32xx->base);

	return 0;
}

static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	u32 val;
	int ret;

	ret = clk_prepare_enable(lpc32xx->clk);
	if (ret)
		return ret;

	val = readl(lpc32xx->base);
	val |= PWM_ENABLE;
	writel(val, lpc32xx->base);

	return 0;
}

static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	u32 val;

	val = readl(lpc32xx->base);
	val &= ~PWM_ENABLE;
	writel(val, lpc32xx->base);

	clk_disable_unprepare(lpc32xx->clk);
}

static int lpc32xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			     const struct pwm_state *state)
{
	int err;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (pwm->state.enabled)
			lpc32xx_pwm_disable(chip, pwm);

		return 0;
	}

	err = lpc32xx_pwm_config(chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!pwm->state.enabled)
		err = lpc32xx_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops lpc32xx_pwm_ops = {
	.apply = lpc32xx_pwm_apply,
};

static int lpc32xx_pwm_probe(struct platform_device *pdev)
{
	struct lpc32xx_pwm_chip *lpc32xx;
	int ret;
	u32 val;

	lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
	if (!lpc32xx)
		return -ENOMEM;

	lpc32xx->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(lpc32xx->base))
		return PTR_ERR(lpc32xx->base);

	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(lpc32xx->clk))
		return PTR_ERR(lpc32xx->clk);

	lpc32xx->chip.dev = &pdev->dev;
	lpc32xx->chip.ops = &lpc32xx_pwm_ops;
	lpc32xx->chip.npwm = 1;

	/* If PWM is disabled, configure the output to the default value */
	val = readl(lpc32xx->base);
	val &= ~PWM_PIN_LEVEL;
	writel(val, lpc32xx->base);

	ret = devm_pwmchip_add(&pdev->dev, &lpc32xx->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
		return ret;
	}

	return 0;
}

static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
	{ .compatible = "nxp,lpc3220-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);

static struct platform_driver lpc32xx_pwm_driver = {
	.driver = {
		.name = "lpc32xx-pwm",
		.of_match_table = lpc32xx_pwm_dt_ids,
	},
	.probe = lpc32xx_pwm_probe,
};
module_platform_driver(lpc32xx_pwm_driver);

MODULE_ALIAS("platform:lpc32xx-pwm");
MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
MODULE_DESCRIPTION("LPC32XX PWM Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a10e763b	1	// SPDX-License-Identifier: GPL-2.0-only
2132fa8d APS	2	/*
2132fa8d APS	3	* Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2132fa8d APS	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/err.h>
	8	#include <linux/io.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/of_address.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/pwm.h>
	15	#include <linux/slab.h>
	16
	17	struct lpc32xx_pwm_chip {
	18	struct pwm_chip chip;
	19	struct clk *clk;
	20	void __iomem *base;
	21	};
	22
5a9fc9c6	23	#define PWM_ENABLE BIT(31)
acfd92fd	24	#define PWM_PIN_LEVEL BIT(30)
2132fa8d APS	25
	26	#define to_lpc32xx_pwm_chip(_chip) \
	27	container_of(_chip, struct lpc32xx_pwm_chip, chip)
	28
	29	static int lpc32xx_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	30	int duty_ns, int period_ns)
	31	{
	32	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	33	unsigned long long c;
	34	int period_cycles, duty_cycles;
affb923d	35	u32 val;
5a9fc9c6	36	c = clk_get_rate(lpc32xx->clk);
2132fa8d	37
5a9fc9c6 VZ	38	/* The highest acceptable divisor is 256, which is represented by 0 */
	39	period_cycles = div64_u64(c * period_ns,
	40	(unsigned long long)NSEC_PER_SEC * 256);
d6dbdf0d VZ	41	if (!period_cycles \|\| period_cycles > 256)
	42	return -ERANGE;
	43	if (period_cycles == 256)
5a9fc9c6	44	period_cycles = 0;
2132fa8d	45
5a9fc9c6 VZ	46	/* Compute 256 x #duty/period value and care for corner cases */
	47	duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
	48	period_ns);
	49	if (!duty_cycles)
	50	duty_cycles = 1;
	51	if (duty_cycles > 255)
	52	duty_cycles = 255;
2132fa8d	53
4aae44f6	54	val = readl(lpc32xx->base);
affb923d	55	val &= ~0xFFFF;
5a9fc9c6	56	val \|= (period_cycles << 8) \| duty_cycles;
4aae44f6	57	writel(val, lpc32xx->base);
2132fa8d APS	58
	59	return 0;
	60	}
	61
	62	static int lpc32xx_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	63	{
	64	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
08ee77b5 AL	65	u32 val;
	66	int ret;
	67
82aff048	68	ret = clk_prepare_enable(lpc32xx->clk);
08ee77b5 AL	69	if (ret)
	70	return ret;
	71
4aae44f6	72	val = readl(lpc32xx->base);
08ee77b5	73	val \|= PWM_ENABLE;
4aae44f6	74	writel(val, lpc32xx->base);
2132fa8d	75
08ee77b5	76	return 0;
2132fa8d APS	77	}
	78
	79	static void lpc32xx_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	80	{
	81	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
08ee77b5 AL	82	u32 val;
08ee77b5 AL	83
4aae44f6	84	val = readl(lpc32xx->base);
08ee77b5	85	val &= ~PWM_ENABLE;
4aae44f6	86	writel(val, lpc32xx->base);
2132fa8d	87
82aff048	88	clk_disable_unprepare(lpc32xx->clk);
2132fa8d APS	89	}
2132fa8d APS	90
5fa3b87f UKK	91	static int lpc32xx_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	92	const struct pwm_state *state)
	93	{
	94	int err;
	95
	96	if (state->polarity != PWM_POLARITY_NORMAL)
	97	return -EINVAL;
	98
	99	if (!state->enabled) {
	100	if (pwm->state.enabled)
	101	lpc32xx_pwm_disable(chip, pwm);
	102
	103	return 0;
	104	}
	105
80943bbd	106	err = lpc32xx_pwm_config(chip, pwm, state->duty_cycle, state->period);
5fa3b87f UKK	107	if (err)
	108	return err;
	109
	110	if (!pwm->state.enabled)
	111	err = lpc32xx_pwm_enable(chip, pwm);
	112
	113	return err;
	114	}
	115
2132fa8d	116	static const struct pwm_ops lpc32xx_pwm_ops = {
5fa3b87f	117	.apply = lpc32xx_pwm_apply,
2132fa8d APS	118	};
	119
	120	static int lpc32xx_pwm_probe(struct platform_device *pdev)
	121	{
	122	struct lpc32xx_pwm_chip *lpc32xx;
2132fa8d	123	int ret;
acfd92fd	124	u32 val;
2132fa8d APS	125
	126	lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
	127	if (!lpc32xx)
	128	return -ENOMEM;
	129
fd7c575a	130	lpc32xx->base = devm_platform_ioremap_resource(pdev, 0);
6d4294d1 TR	131	if (IS_ERR(lpc32xx->base))
6d4294d1 TR	132	return PTR_ERR(lpc32xx->base);
2132fa8d APS	133
	134	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
	135	if (IS_ERR(lpc32xx->clk))
	136	return PTR_ERR(lpc32xx->clk);
	137
	138	lpc32xx->chip.dev = &pdev->dev;
	139	lpc32xx->chip.ops = &lpc32xx_pwm_ops;
ebe1fca3	140	lpc32xx->chip.npwm = 1;
2132fa8d	141
3d2813fb	142	/* If PWM is disabled, configure the output to the default value */
4aae44f6	143	val = readl(lpc32xx->base);
3d2813fb	144	val &= ~PWM_PIN_LEVEL;
4aae44f6	145	writel(val, lpc32xx->base);
3d2813fb	146
da68a9f4	147	ret = devm_pwmchip_add(&pdev->dev, &lpc32xx->chip);
2132fa8d APS	148	if (ret < 0) {
	149	dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
	150	return ret;
	151	}
	152
2132fa8d APS	153	return 0;
	154	}
	155
f1a8870a	156	static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
2132fa8d APS	157	{ .compatible = "nxp,lpc3220-pwm", },
	158	{ /* sentinel */ }
	159	};
	160	MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
	161
	162	static struct platform_driver lpc32xx_pwm_driver = {
	163	.driver = {
	164	.name = "lpc32xx-pwm",
3cb3b2bf	165	.of_match_table = lpc32xx_pwm_dt_ids,
2132fa8d APS	166	},
2132fa8d APS	167	.probe = lpc32xx_pwm_probe,
2132fa8d APS	168	};
	169	module_platform_driver(lpc32xx_pwm_driver);
	170
	171	MODULE_ALIAS("platform:lpc32xx-pwm");
	172	MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
	173	MODULE_DESCRIPTION("LPC32XX PWM Driver");
	174	MODULE_LICENSE("GPL v2");