[linux-2.6-block.git] / drivers / pwm / pwm-keembay.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Keem Bay PWM driver
 *
 * Copyright (C) 2020 Intel Corporation
 * Authors: Lai Poey Seng <poey.seng.lai@intel.com>
 *          Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
 *
 * Limitations:
 * - Upon disabling a channel, the currently running
 *   period will not be completed. However, upon
 *   reconfiguration of the duty cycle/period, the
 *   currently running period will be completed first.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/regmap.h>

#define KMB_TOTAL_PWM_CHANNELS		6
#define KMB_PWM_COUNT_MAX		U16_MAX
#define KMB_PWM_EN_BIT			BIT(31)

/* Mask */
#define KMB_PWM_HIGH_MASK		GENMASK(31, 16)
#define KMB_PWM_LOW_MASK		GENMASK(15, 0)
#define KMB_PWM_LEADIN_MASK		GENMASK(30, 0)

/* PWM Register offset */
#define KMB_PWM_LEADIN_OFFSET(ch)	(0x00 + 4 * (ch))
#define KMB_PWM_HIGHLOW_OFFSET(ch)	(0x20 + 4 * (ch))

struct keembay_pwm {
	struct pwm_chip chip;
	struct device *dev;
	struct clk *clk;
	void __iomem *base;
};

static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip)
{
	return container_of(chip, struct keembay_pwm, chip);
}

static void keembay_clk_unprepare(void *data)
{
	clk_disable_unprepare(data);
}

static int keembay_clk_enable(struct device *dev, struct clk *clk)
{
	int ret;

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk);
}

/*
 * With gcc 10, CONFIG_CC_OPTIMIZE_FOR_SIZE and only "inline" instead of
 * "__always_inline" this fails to compile because the compiler doesn't notice
 * for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.
 */
static __always_inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask,
					   u32 val, u32 offset)
{
	u32 buff = readl(priv->base + offset);

	buff = u32_replace_bits(buff, val, mask);
	writel(buff, priv->base + offset);
}

static void keembay_pwm_enable(struct keembay_pwm *priv, int ch)
{
	keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1,
				KMB_PWM_LEADIN_OFFSET(ch));
}

static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)
{
	keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0,
				KMB_PWM_LEADIN_OFFSET(ch));
}

static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				 struct pwm_state *state)
{
	struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
	unsigned long long high, low;
	unsigned long clk_rate;
	u32 highlow;

	clk_rate = clk_get_rate(priv->clk);

	/* Read channel enabled status */
	highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
	if (highlow & KMB_PWM_EN_BIT)
		state->enabled = true;
	else
		state->enabled = false;

	/* Read period and duty cycle */
	highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
	low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;
	high = FIELD_GET(KMB_PWM_HIGH_MASK, highlow) * NSEC_PER_SEC;
	state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);
	state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);
	state->polarity = PWM_POLARITY_NORMAL;

	return 0;
}

static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			     const struct pwm_state *state)
{
	struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
	struct pwm_state current_state;
	unsigned long long div;
	unsigned long clk_rate;
	u32 pwm_count = 0;
	u16 high, low;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	/*
	 * Configure the pwm repeat count as infinite at (15:0) and leadin
	 * low time as 0 at (30:16), which is in terms of clock cycles.
	 */
	keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0,
				KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));

	keembay_pwm_get_state(chip, pwm, &current_state);

	if (!state->enabled) {
		if (current_state.enabled)
			keembay_pwm_disable(priv, pwm->hwpwm);
		return 0;
	}

	/*
	 * The upper 16 bits and lower 16 bits of the KMB_PWM_HIGHLOW_OFFSET
	 * register contain the high time and low time of waveform accordingly.
	 * All the values are in terms of clock cycles.
	 */

	clk_rate = clk_get_rate(priv->clk);
	div = clk_rate * state->duty_cycle;
	div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
	if (div > KMB_PWM_COUNT_MAX)
		return -ERANGE;

	high = div;
	div = clk_rate * state->period;
	div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
	div = div - high;
	if (div > KMB_PWM_COUNT_MAX)
		return -ERANGE;

	low = div;

	pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, high) |
		    FIELD_PREP(KMB_PWM_LOW_MASK, low);

	writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));

	if (state->enabled && !current_state.enabled)
		keembay_pwm_enable(priv, pwm->hwpwm);

	return 0;
}

static const struct pwm_ops keembay_pwm_ops = {
	.apply = keembay_pwm_apply,
	.get_state = keembay_pwm_get_state,
};

static int keembay_pwm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct keembay_pwm *priv;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk))
		return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");

	priv->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	ret = keembay_clk_enable(dev, priv->clk);
	if (ret)
		return ret;

	priv->chip.dev = dev;
	priv->chip.ops = &keembay_pwm_ops;
	priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS;

	ret = devm_pwmchip_add(dev, &priv->chip);
	if (ret)
		return dev_err_probe(dev, ret, "Failed to add PWM chip\n");

	return 0;
}

static const struct of_device_id keembay_pwm_of_match[] = {
	{ .compatible = "intel,keembay-pwm" },
	{ }
};
MODULE_DEVICE_TABLE(of, keembay_pwm_of_match);

static struct platform_driver keembay_pwm_driver = {
	.probe	= keembay_pwm_probe,
	.driver	= {
		.name = "pwm-keembay",
		.of_match_table = keembay_pwm_of_match,
	},
};
module_platform_driver(keembay_pwm_driver);

MODULE_ALIAS("platform:pwm-keembay");
MODULE_DESCRIPTION("Intel Keem Bay PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bd899ceb VA	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Intel Keem Bay PWM driver
	4	*
	5	* Copyright (C) 2020 Intel Corporation
	6	* Authors: Lai Poey Seng <poey.seng.lai@intel.com>
	7	* Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
	8	*
	9	* Limitations:
	10	* - Upon disabling a channel, the currently running
	11	* period will not be completed. However, upon
	12	* reconfiguration of the duty cycle/period, the
	13	* currently running period will be completed first.
	14	*/
	15
	16	#include <linux/bitfield.h>
	17	#include <linux/clk.h>
	18	#include <linux/io.h>
	19	#include <linux/mod_devicetable.h>
	20	#include <linux/module.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/pwm.h>
	23	#include <linux/regmap.h>
	24
	25	#define KMB_TOTAL_PWM_CHANNELS 6
	26	#define KMB_PWM_COUNT_MAX U16_MAX
	27	#define KMB_PWM_EN_BIT BIT(31)
	28
	29	/* Mask */
	30	#define KMB_PWM_HIGH_MASK GENMASK(31, 16)
	31	#define KMB_PWM_LOW_MASK GENMASK(15, 0)
	32	#define KMB_PWM_LEADIN_MASK GENMASK(30, 0)
	33
	34	/* PWM Register offset */
	35	#define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch))
	36	#define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch))
	37
	38	struct keembay_pwm {
	39	struct pwm_chip chip;
	40	struct device *dev;
	41	struct clk *clk;
	42	void __iomem *base;
	43	};
	44
	45	static inline struct keembay_pwm to_keembay_pwm_dev(struct pwm_chip chip)
	46	{
	47	return container_of(chip, struct keembay_pwm, chip);
	48	}
	49
	50	static void keembay_clk_unprepare(void *data)
	51	{
	52	clk_disable_unprepare(data);
	53	}
	54
	55	static int keembay_clk_enable(struct device dev, struct clk clk)
	56	{
	57	int ret;
	58
	59	ret = clk_prepare_enable(clk);
	60	if (ret)
	61	return ret;
	62
	63	return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk);
	64	}
65
bb72e1db UKK	66	/*
	67	* With gcc 10, CONFIG_CC_OPTIMIZE_FOR_SIZE and only "inline" instead of
	68	* "__always_inline" this fails to compile because the compiler doesn't notice
	69	* for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.
	70	*/
	71	static __always_inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask,
bd899ceb VA	72	u32 val, u32 offset)
	73	{
	74	u32 buff = readl(priv->base + offset);
	75
	76	buff = u32_replace_bits(buff, val, mask);
	77	writel(buff, priv->base + offset);
	78	}
	79
	80	static void keembay_pwm_enable(struct keembay_pwm *priv, int ch)
	81	{
	82	keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1,
	83	KMB_PWM_LEADIN_OFFSET(ch));
	84	}
	85
	86	static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)
	87	{
	88	keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0,
	89	KMB_PWM_LEADIN_OFFSET(ch));
	90	}
	91
6c452cff UKK	92	static int keembay_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
6c452cff UKK	93	struct pwm_state *state)
bd899ceb VA	94	{
	95	struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
	96	unsigned long long high, low;
	97	unsigned long clk_rate;
	98	u32 highlow;
	99
	100	clk_rate = clk_get_rate(priv->clk);
	101
	102	/* Read channel enabled status */
	103	highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
	104	if (highlow & KMB_PWM_EN_BIT)
	105	state->enabled = true;
	106	else
	107	state->enabled = false;
	108
	109	/* Read period and duty cycle */
	110	highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
	111	low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;
	112	high = FIELD_GET(KMB_PWM_HIGH_MASK, highlow) * NSEC_PER_SEC;
	113	state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);
	114	state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);
	115	state->polarity = PWM_POLARITY_NORMAL;
6c452cff UKK	116
6c452cff UKK	117	return 0;
bd899ceb VA	118	}
	119
	120	static int keembay_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	121	const struct pwm_state *state)
	122	{
	123	struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
	124	struct pwm_state current_state;
	125	unsigned long long div;
	126	unsigned long clk_rate;
	127	u32 pwm_count = 0;
	128	u16 high, low;
	129
	130	if (state->polarity != PWM_POLARITY_NORMAL)
	131	return -EINVAL;
	132
	133	/*
	134	* Configure the pwm repeat count as infinite at (15:0) and leadin
	135	* low time as 0 at (30:16), which is in terms of clock cycles.
	136	*/
	137	keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0,
	138	KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
	139
	140	keembay_pwm_get_state(chip, pwm, &current_state);
	141
	142	if (!state->enabled) {
	143	if (current_state.enabled)
	144	keembay_pwm_disable(priv, pwm->hwpwm);
	145	return 0;
	146	}
	147
	148	/*
	149	* The upper 16 bits and lower 16 bits of the KMB_PWM_HIGHLOW_OFFSET
	150	* register contain the high time and low time of waveform accordingly.
	151	* All the values are in terms of clock cycles.
	152	*/
	153
	154	clk_rate = clk_get_rate(priv->clk);
	155	div = clk_rate * state->duty_cycle;
	156	div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
	157	if (div > KMB_PWM_COUNT_MAX)
	158	return -ERANGE;
	159
	160	high = div;
	161	div = clk_rate * state->period;
	162	div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
	163	div = div - high;
	164	if (div > KMB_PWM_COUNT_MAX)
	165	return -ERANGE;
	166
	167	low = div;
	168
	169	pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, high) \|
	170	FIELD_PREP(KMB_PWM_LOW_MASK, low);
	171
	172	writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
	173
	174	if (state->enabled && !current_state.enabled)
	175	keembay_pwm_enable(priv, pwm->hwpwm);
	176
	177	return 0;
	178	}
	179
	180	static const struct pwm_ops keembay_pwm_ops = {
bd899ceb VA	181	.apply = keembay_pwm_apply,
	182	.get_state = keembay_pwm_get_state,
	183	};
	184
	185	static int keembay_pwm_probe(struct platform_device *pdev)
	186	{
	187	struct device *dev = &pdev->dev;
	188	struct keembay_pwm *priv;
	189	int ret;
	190
	191	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	192	if (!priv)
	193	return -ENOMEM;
	194
	195	priv->clk = devm_clk_get(dev, NULL);
	196	if (IS_ERR(priv->clk))
	197	return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");
	198
	199	priv->base = devm_platform_ioremap_resource(pdev, 0);
	200	if (IS_ERR(priv->base))
	201	return PTR_ERR(priv->base);
	202
	203	ret = keembay_clk_enable(dev, priv->clk);
	204	if (ret)
	205	return ret;
	206
bd899ceb VA	207	priv->chip.dev = dev;
	208	priv->chip.ops = &keembay_pwm_ops;
	209	priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS;
	210
0aa2bec5	211	ret = devm_pwmchip_add(dev, &priv->chip);
bd899ceb VA	212	if (ret)
	213	return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
	214
bd899ceb VA	215	return 0;
	216	}
	217
bd899ceb VA	218	static const struct of_device_id keembay_pwm_of_match[] = {
	219	{ .compatible = "intel,keembay-pwm" },
	220	{ }
	221	};
	222	MODULE_DEVICE_TABLE(of, keembay_pwm_of_match);
	223
	224	static struct platform_driver keembay_pwm_driver = {
	225	.probe = keembay_pwm_probe,
bd899ceb VA	226	.driver = {
	227	.name = "pwm-keembay",
	228	.of_match_table = keembay_pwm_of_match,
	229	},
	230	};
	231	module_platform_driver(keembay_pwm_driver);
	232
	233	MODULE_ALIAS("platform:pwm-keembay");
	234	MODULE_DESCRIPTION("Intel Keem Bay PWM driver");
	235	MODULE_LICENSE("GPL v2");