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f6b8a570 TR |
1 | /* |
2 | * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> | |
3 | * JZ4740 platform PWM support | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * You should have received a copy of the GNU General Public License along | |
11 | * with this program; if not, write to the Free Software Foundation, Inc., | |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/clk.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
cc201733 | 21 | #include <linux/of_device.h> |
f6b8a570 TR |
22 | #include <linux/platform_device.h> |
23 | #include <linux/pwm.h> | |
24 | ||
f6b8a570 TR |
25 | #include <asm/mach-jz4740/timer.h> |
26 | ||
27 | #define NUM_PWM 8 | |
28 | ||
f6b8a570 TR |
29 | struct jz4740_pwm_chip { |
30 | struct pwm_chip chip; | |
31 | struct clk *clk; | |
32 | }; | |
33 | ||
34 | static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip) | |
35 | { | |
36 | return container_of(chip, struct jz4740_pwm_chip, chip); | |
37 | } | |
38 | ||
39 | static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) | |
40 | { | |
f6b8a570 TR |
41 | /* |
42 | * Timers 0 and 1 are used for system tasks, so they are unavailable | |
43 | * for use as PWMs. | |
44 | */ | |
45 | if (pwm->hwpwm < 2) | |
46 | return -EBUSY; | |
47 | ||
f6b8a570 TR |
48 | jz4740_timer_start(pwm->hwpwm); |
49 | ||
50 | return 0; | |
51 | } | |
52 | ||
53 | static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
54 | { | |
f6b8a570 TR |
55 | jz4740_timer_set_ctrl(pwm->hwpwm, 0); |
56 | ||
f6b8a570 TR |
57 | jz4740_timer_stop(pwm->hwpwm); |
58 | } | |
59 | ||
60 | static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
61 | { | |
62 | uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm); | |
63 | ||
64 | ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; | |
65 | jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); | |
66 | jz4740_timer_enable(pwm->hwpwm); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
71 | static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
72 | { | |
73 | uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); | |
74 | ||
df56b171 MH |
75 | /* Disable PWM output. |
76 | * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the | |
77 | * counter is stopped, while in TCU1 mode the order does not matter. | |
78 | */ | |
f6b8a570 | 79 | ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; |
f6b8a570 | 80 | jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); |
df56b171 MH |
81 | |
82 | /* Stop counter */ | |
83 | jz4740_timer_disable(pwm->hwpwm); | |
f6b8a570 TR |
84 | } |
85 | ||
86 | static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
87 | int duty_ns, int period_ns) | |
88 | { | |
89 | struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip); | |
90 | unsigned long long tmp; | |
91 | unsigned long period, duty; | |
92 | unsigned int prescaler = 0; | |
93 | uint16_t ctrl; | |
94 | bool is_enabled; | |
95 | ||
96 | tmp = (unsigned long long)clk_get_rate(jz4740->clk) * period_ns; | |
97 | do_div(tmp, 1000000000); | |
98 | period = tmp; | |
99 | ||
100 | while (period > 0xffff && prescaler < 6) { | |
101 | period >>= 2; | |
102 | ++prescaler; | |
103 | } | |
104 | ||
105 | if (prescaler == 6) | |
106 | return -EINVAL; | |
107 | ||
108 | tmp = (unsigned long long)period * duty_ns; | |
109 | do_div(tmp, period_ns); | |
110 | duty = period - tmp; | |
111 | ||
112 | if (duty >= period) | |
113 | duty = period - 1; | |
114 | ||
115 | is_enabled = jz4740_timer_is_enabled(pwm->hwpwm); | |
116 | if (is_enabled) | |
117 | jz4740_pwm_disable(chip, pwm); | |
118 | ||
119 | jz4740_timer_set_count(pwm->hwpwm, 0); | |
120 | jz4740_timer_set_duty(pwm->hwpwm, duty); | |
121 | jz4740_timer_set_period(pwm->hwpwm, period); | |
122 | ||
123 | ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | | |
124 | JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; | |
125 | ||
126 | jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); | |
127 | ||
128 | if (is_enabled) | |
129 | jz4740_pwm_enable(chip, pwm); | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
174dcc8e PC |
134 | static int jz4740_pwm_set_polarity(struct pwm_chip *chip, |
135 | struct pwm_device *pwm, enum pwm_polarity polarity) | |
136 | { | |
137 | uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm); | |
138 | ||
139 | switch (polarity) { | |
140 | case PWM_POLARITY_NORMAL: | |
141 | ctrl &= ~JZ_TIMER_CTRL_PWM_ACTIVE_LOW; | |
142 | break; | |
143 | case PWM_POLARITY_INVERSED: | |
144 | ctrl |= JZ_TIMER_CTRL_PWM_ACTIVE_LOW; | |
145 | break; | |
146 | } | |
147 | ||
148 | jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); | |
149 | return 0; | |
150 | } | |
151 | ||
f6b8a570 TR |
152 | static const struct pwm_ops jz4740_pwm_ops = { |
153 | .request = jz4740_pwm_request, | |
154 | .free = jz4740_pwm_free, | |
155 | .config = jz4740_pwm_config, | |
174dcc8e | 156 | .set_polarity = jz4740_pwm_set_polarity, |
f6b8a570 TR |
157 | .enable = jz4740_pwm_enable, |
158 | .disable = jz4740_pwm_disable, | |
159 | .owner = THIS_MODULE, | |
160 | }; | |
161 | ||
3e9fe83d | 162 | static int jz4740_pwm_probe(struct platform_device *pdev) |
f6b8a570 TR |
163 | { |
164 | struct jz4740_pwm_chip *jz4740; | |
f6b8a570 TR |
165 | |
166 | jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL); | |
167 | if (!jz4740) | |
168 | return -ENOMEM; | |
169 | ||
0dc1135f | 170 | jz4740->clk = devm_clk_get(&pdev->dev, "ext"); |
f6b8a570 TR |
171 | if (IS_ERR(jz4740->clk)) |
172 | return PTR_ERR(jz4740->clk); | |
173 | ||
174 | jz4740->chip.dev = &pdev->dev; | |
175 | jz4740->chip.ops = &jz4740_pwm_ops; | |
176 | jz4740->chip.npwm = NUM_PWM; | |
177 | jz4740->chip.base = -1; | |
cc201733 PC |
178 | jz4740->chip.of_xlate = of_pwm_xlate_with_flags; |
179 | jz4740->chip.of_pwm_n_cells = 3; | |
f6b8a570 | 180 | |
f6b8a570 TR |
181 | platform_set_drvdata(pdev, jz4740); |
182 | ||
0dc1135f | 183 | return pwmchip_add(&jz4740->chip); |
f6b8a570 TR |
184 | } |
185 | ||
77f37917 | 186 | static int jz4740_pwm_remove(struct platform_device *pdev) |
f6b8a570 TR |
187 | { |
188 | struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev); | |
f6b8a570 | 189 | |
0dc1135f | 190 | return pwmchip_remove(&jz4740->chip); |
f6b8a570 TR |
191 | } |
192 | ||
cc201733 PC |
193 | #ifdef CONFIG_OF |
194 | static const struct of_device_id jz4740_pwm_dt_ids[] = { | |
195 | { .compatible = "ingenic,jz4740-pwm", }, | |
196 | { .compatible = "ingenic,jz4770-pwm", }, | |
197 | { .compatible = "ingenic,jz4780-pwm", }, | |
198 | {}, | |
199 | }; | |
200 | MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids); | |
201 | #endif | |
202 | ||
f6b8a570 TR |
203 | static struct platform_driver jz4740_pwm_driver = { |
204 | .driver = { | |
205 | .name = "jz4740-pwm", | |
cc201733 | 206 | .of_match_table = of_match_ptr(jz4740_pwm_dt_ids), |
f6b8a570 TR |
207 | }, |
208 | .probe = jz4740_pwm_probe, | |
fd109112 | 209 | .remove = jz4740_pwm_remove, |
f6b8a570 TR |
210 | }; |
211 | module_platform_driver(jz4740_pwm_driver); | |
212 | ||
213 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
214 | MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver"); | |
215 | MODULE_ALIAS("platform:jz4740-pwm"); | |
216 | MODULE_LICENSE("GPL"); |