[linux-block.git] / drivers / pwm / pwm-intel-lgm.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 Intel Corporation.
 *
 * Limitations:
 * - The hardware supports fixed period & configures only 2-wire mode.
 * - Supports normal polarity. Does not support changing polarity.
 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
 *   keep track of running period.
 * - When duty cycle is changed, PWM output may be a mix of previous setting
 *   and new setting for the first period. From second period, the output is
 *   based on new setting.
 * - It is a dedicated PWM fan controller. There are no other consumers for
 *   this PWM controller.
 */
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/reset.h>

#define LGM_PWM_FAN_CON0		0x0
#define LGM_PWM_FAN_EN_EN		BIT(0)
#define LGM_PWM_FAN_EN_DIS		0x0
#define LGM_PWM_FAN_EN_MSK		BIT(0)
#define LGM_PWM_FAN_MODE_2WIRE		0x0
#define LGM_PWM_FAN_MODE_MSK		BIT(1)
#define LGM_PWM_FAN_DC_MSK		GENMASK(23, 16)

#define LGM_PWM_FAN_CON1		0x4
#define LGM_PWM_FAN_MAX_RPM_MSK		GENMASK(15, 0)

#define LGM_PWM_MAX_RPM			(BIT(16) - 1)
#define LGM_PWM_DEFAULT_RPM		4000
#define LGM_PWM_MAX_DUTY_CYCLE		(BIT(8) - 1)

#define LGM_PWM_DC_BITS			8

#define LGM_PWM_PERIOD_2WIRE_NS		(40 * NSEC_PER_MSEC)

struct lgm_pwm_chip {
	struct pwm_chip chip;
	struct regmap *regmap;
	u32 period;
};

static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct lgm_pwm_chip, chip);
}

static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
{
	struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
	struct regmap *regmap = pc->regmap;

	return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
				  enable ? LGM_PWM_FAN_EN_EN : LGM_PWM_FAN_EN_DIS);
}

static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *state)
{
	struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
	u32 duty_cycle, val;
	int ret;

	/* The hardware only supports normal polarity and fixed period. */
	if (state->polarity != PWM_POLARITY_NORMAL || state->period < pc->period)
		return -EINVAL;

	if (!state->enabled)
		return lgm_pwm_enable(chip, 0);

	duty_cycle = min_t(u64, state->duty_cycle, pc->period);
	val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;

	ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_DC_MSK,
				 FIELD_PREP(LGM_PWM_FAN_DC_MSK, val));
	if (ret)
		return ret;

	return lgm_pwm_enable(chip, 1);
}

static int lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
			     struct pwm_state *state)
{
	struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
	u32 duty, val;

	state->enabled = regmap_test_bits(pc->regmap, LGM_PWM_FAN_CON0,
					  LGM_PWM_FAN_EN_EN);
	state->polarity = PWM_POLARITY_NORMAL;
	state->period = pc->period; /* fixed period */

	regmap_read(pc->regmap, LGM_PWM_FAN_CON0, &val);
	duty = FIELD_GET(LGM_PWM_FAN_DC_MSK, val);
	state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE);

	return 0;
}

static const struct pwm_ops lgm_pwm_ops = {
	.get_state = lgm_pwm_get_state,
	.apply = lgm_pwm_apply,
	.owner = THIS_MODULE,
};

static void lgm_pwm_init(struct lgm_pwm_chip *pc)
{
	struct regmap *regmap = pc->regmap;
	u32 con0_val;

	con0_val = FIELD_PREP(LGM_PWM_FAN_MODE_MSK, LGM_PWM_FAN_MODE_2WIRE);
	pc->period = LGM_PWM_PERIOD_2WIRE_NS;
	regmap_update_bits(regmap, LGM_PWM_FAN_CON1, LGM_PWM_FAN_MAX_RPM_MSK,
			   LGM_PWM_DEFAULT_RPM);
	regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_MODE_MSK,
			   con0_val);
}

static const struct regmap_config lgm_pwm_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
};

static void lgm_clk_release(void *data)
{
	struct clk *clk = data;

	clk_disable_unprepare(clk);
}

static int lgm_clk_enable(struct device *dev, struct clk *clk)
{
	int ret;

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	return devm_add_action_or_reset(dev, lgm_clk_release, clk);
}

static void lgm_reset_control_release(void *data)
{
	struct reset_control *rst = data;

	reset_control_assert(rst);
}

static int lgm_reset_control_deassert(struct device *dev, struct reset_control *rst)
{
	int ret;

	ret = reset_control_deassert(rst);
	if (ret)
		return ret;

	return devm_add_action_or_reset(dev, lgm_reset_control_release, rst);
}

static int lgm_pwm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct reset_control *rst;
	struct lgm_pwm_chip *pc;
	void __iomem *io_base;
	struct clk *clk;
	int ret;

	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	io_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(io_base))
		return PTR_ERR(io_base);

	pc->regmap = devm_regmap_init_mmio(dev, io_base, &lgm_pwm_regmap_config);
	if (IS_ERR(pc->regmap))
		return dev_err_probe(dev, PTR_ERR(pc->regmap),
				     "failed to init register map\n");

	clk = devm_clk_get(dev, NULL);
	if (IS_ERR(clk))
		return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");

	ret = lgm_clk_enable(dev, clk);
	if (ret)
		return dev_err_probe(dev, ret, "failed to enable clock\n");

	rst = devm_reset_control_get_exclusive(dev, NULL);
	if (IS_ERR(rst))
		return dev_err_probe(dev, PTR_ERR(rst),
				     "failed to get reset control\n");

	ret = lgm_reset_control_deassert(dev, rst);
	if (ret)
		return dev_err_probe(dev, ret, "cannot deassert reset control\n");

	pc->chip.dev = dev;
	pc->chip.ops = &lgm_pwm_ops;
	pc->chip.npwm = 1;

	lgm_pwm_init(pc);

	ret = devm_pwmchip_add(dev, &pc->chip);
	if (ret < 0)
		return dev_err_probe(dev, ret, "failed to add PWM chip\n");

	return 0;
}

static const struct of_device_id lgm_pwm_of_match[] = {
	{ .compatible = "intel,lgm-pwm" },
	{ }
};
MODULE_DEVICE_TABLE(of, lgm_pwm_of_match);

static struct platform_driver lgm_pwm_driver = {
	.driver = {
		.name = "intel-pwm",
		.of_match_table = lgm_pwm_of_match,
	},
	.probe = lgm_pwm_probe,
};
module_platform_driver(lgm_pwm_driver);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
97960add RT	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2020 Intel Corporation.
	4	*
	5	* Limitations:
	6	* - The hardware supports fixed period & configures only 2-wire mode.
	7	* - Supports normal polarity. Does not support changing polarity.
	8	* - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
	9	* keep track of running period.
	10	* - When duty cycle is changed, PWM output may be a mix of previous setting
	11	* and new setting for the first period. From second period, the output is
	12	* based on new setting.
	13	* - It is a dedicated PWM fan controller. There are no other consumers for
	14	* this PWM controller.
	15	*/
	16	#include <linux/bitfield.h>
	17	#include <linux/clk.h>
	18	#include <linux/module.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/mod_devicetable.h>
	21	#include <linux/pwm.h>
	22	#include <linux/regmap.h>
	23	#include <linux/reset.h>
	24
	25	#define LGM_PWM_FAN_CON0 0x0
	26	#define LGM_PWM_FAN_EN_EN BIT(0)
	27	#define LGM_PWM_FAN_EN_DIS 0x0
	28	#define LGM_PWM_FAN_EN_MSK BIT(0)
	29	#define LGM_PWM_FAN_MODE_2WIRE 0x0
	30	#define LGM_PWM_FAN_MODE_MSK BIT(1)
	31	#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
	32
	33	#define LGM_PWM_FAN_CON1 0x4
	34	#define LGM_PWM_FAN_MAX_RPM_MSK GENMASK(15, 0)
	35
	36	#define LGM_PWM_MAX_RPM (BIT(16) - 1)
	37	#define LGM_PWM_DEFAULT_RPM 4000
	38	#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
	39
	40	#define LGM_PWM_DC_BITS 8
	41
	42	#define LGM_PWM_PERIOD_2WIRE_NS (40 * NSEC_PER_MSEC)
	43
	44	struct lgm_pwm_chip {
	45	struct pwm_chip chip;
	46	struct regmap *regmap;
	47	u32 period;
	48	};
	49
	50	static inline struct lgm_pwm_chip to_lgm_pwm_chip(struct pwm_chip chip)
	51	{
	52	return container_of(chip, struct lgm_pwm_chip, chip);
	53	}
	54
	55	static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
	56	{
	57	struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
	58	struct regmap *regmap = pc->regmap;
	59
	60	return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
	61	enable ? LGM_PWM_FAN_EN_EN : LGM_PWM_FAN_EN_DIS);
	62	}
	63
	64	static int lgm_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
65	const struct pwm_state *state)
66	{
67	struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
68	u32 duty_cycle, val;
69	int ret;
70
71	/* The hardware only supports normal polarity and fixed period. */
72	if (state->polarity != PWM_POLARITY_NORMAL \|\| state->period < pc->period)
73	return -EINVAL;
74
75	if (!state->enabled)
76	return lgm_pwm_enable(chip, 0);
77
78	duty_cycle = min_t(u64, state->duty_cycle, pc->period);
79	val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
80
81	ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_DC_MSK,
82	FIELD_PREP(LGM_PWM_FAN_DC_MSK, val));
83	if (ret)
84	return ret;
85
86	return lgm_pwm_enable(chip, 1);
87	}
88
6c452cff UKK	89	static int lgm_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
6c452cff UKK	90	struct pwm_state *state)
97960add RT	91	{
	92	struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
	93	u32 duty, val;
	94
	95	state->enabled = regmap_test_bits(pc->regmap, LGM_PWM_FAN_CON0,
	96	LGM_PWM_FAN_EN_EN);
	97	state->polarity = PWM_POLARITY_NORMAL;
	98	state->period = pc->period; /* fixed period */
	99
	100	regmap_read(pc->regmap, LGM_PWM_FAN_CON0, &val);
	101	duty = FIELD_GET(LGM_PWM_FAN_DC_MSK, val);
	102	state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE);
6c452cff UKK	103
6c452cff UKK	104	return 0;
97960add RT	105	}
	106
	107	static const struct pwm_ops lgm_pwm_ops = {
	108	.get_state = lgm_pwm_get_state,
	109	.apply = lgm_pwm_apply,
	110	.owner = THIS_MODULE,
	111	};
	112
	113	static void lgm_pwm_init(struct lgm_pwm_chip *pc)
	114	{
	115	struct regmap *regmap = pc->regmap;
	116	u32 con0_val;
	117
	118	con0_val = FIELD_PREP(LGM_PWM_FAN_MODE_MSK, LGM_PWM_FAN_MODE_2WIRE);
	119	pc->period = LGM_PWM_PERIOD_2WIRE_NS;
	120	regmap_update_bits(regmap, LGM_PWM_FAN_CON1, LGM_PWM_FAN_MAX_RPM_MSK,
	121	LGM_PWM_DEFAULT_RPM);
	122	regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_MODE_MSK,
	123	con0_val);
	124	}
	125
	126	static const struct regmap_config lgm_pwm_regmap_config = {
	127	.reg_bits = 32,
	128	.reg_stride = 4,
	129	.val_bits = 32,
	130	};
	131
	132	static void lgm_clk_release(void *data)
	133	{
	134	struct clk *clk = data;
	135
	136	clk_disable_unprepare(clk);
	137	}
	138
	139	static int lgm_clk_enable(struct device dev, struct clk clk)
	140	{
	141	int ret;
	142
	143	ret = clk_prepare_enable(clk);
	144	if (ret)
	145	return ret;
	146
	147	return devm_add_action_or_reset(dev, lgm_clk_release, clk);
	148	}
	149
	150	static void lgm_reset_control_release(void *data)
	151	{
	152	struct reset_control *rst = data;
	153
	154	reset_control_assert(rst);
	155	}
	156
	157	static int lgm_reset_control_deassert(struct device dev, struct reset_control rst)
	158	{
	159	int ret;
	160
	161	ret = reset_control_deassert(rst);
	162	if (ret)
	163	return ret;
	164
	165	return devm_add_action_or_reset(dev, lgm_reset_control_release, rst);
	166	}
	167
	168	static int lgm_pwm_probe(struct platform_device *pdev)
169	{
170	struct device *dev = &pdev->dev;
171	struct reset_control *rst;
172	struct lgm_pwm_chip *pc;
173	void __iomem *io_base;
174	struct clk *clk;
175	int ret;
176
177	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
178	if (!pc)
179	return -ENOMEM;
180
97960add RT	181	io_base = devm_platform_ioremap_resource(pdev, 0);
	182	if (IS_ERR(io_base))
	183	return PTR_ERR(io_base);
	184
	185	pc->regmap = devm_regmap_init_mmio(dev, io_base, &lgm_pwm_regmap_config);
	186	if (IS_ERR(pc->regmap))
	187	return dev_err_probe(dev, PTR_ERR(pc->regmap),
	188	"failed to init register map\n");
	189
	190	clk = devm_clk_get(dev, NULL);
	191	if (IS_ERR(clk))
	192	return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
	193
	194	ret = lgm_clk_enable(dev, clk);
	195	if (ret)
	196	return dev_err_probe(dev, ret, "failed to enable clock\n");
	197
	198	rst = devm_reset_control_get_exclusive(dev, NULL);
	199	if (IS_ERR(rst))
	200	return dev_err_probe(dev, PTR_ERR(rst),
	201	"failed to get reset control\n");
	202
	203	ret = lgm_reset_control_deassert(dev, rst);
	204	if (ret)
	205	return dev_err_probe(dev, ret, "cannot deassert reset control\n");
	206
	207	pc->chip.dev = dev;
	208	pc->chip.ops = &lgm_pwm_ops;
	209	pc->chip.npwm = 1;
97960add RT	210
	211	lgm_pwm_init(pc);
	212
d8c11a65	213	ret = devm_pwmchip_add(dev, &pc->chip);
97960add RT	214	if (ret < 0)
	215	return dev_err_probe(dev, ret, "failed to add PWM chip\n");
	216
	217	return 0;
	218	}
	219
97960add RT	220	static const struct of_device_id lgm_pwm_of_match[] = {
	221	{ .compatible = "intel,lgm-pwm" },
	222	{ }
	223	};
	224	MODULE_DEVICE_TABLE(of, lgm_pwm_of_match);
	225
	226	static struct platform_driver lgm_pwm_driver = {
	227	.driver = {
	228	.name = "intel-pwm",
	229	.of_match_table = lgm_pwm_of_match,
	230	},
	231	.probe = lgm_pwm_probe,
97960add RT	232	};
	233	module_platform_driver(lgm_pwm_driver);
	234
	235	MODULE_LICENSE("GPL v2");