Commit | Line | Data |
---|---|---|
a99290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
166091b1 SH |
2 | /* |
3 | * simple driver for PWM (Pulse Width Modulator) controller | |
4 | * | |
166091b1 | 5 | * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> |
f6960976 UKK |
6 | * |
7 | * Limitations: | |
8 | * - When disabled the output is driven to 0 independent of the configured | |
9 | * polarity. | |
166091b1 SH |
10 | */ |
11 | ||
9f617ada MV |
12 | #include <linux/bitfield.h> |
13 | #include <linux/bitops.h> | |
166091b1 | 14 | #include <linux/clk.h> |
137fd45f | 15 | #include <linux/delay.h> |
e3adc7ef | 16 | #include <linux/err.h> |
166091b1 | 17 | #include <linux/io.h> |
e3adc7ef MV |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | |
2a8876cf | 20 | #include <linux/of.h> |
e3adc7ef MV |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pwm.h> | |
23 | #include <linux/slab.h> | |
c010dba8 | 24 | |
40f260c2 | 25 | #define MX3_PWMCR 0x00 /* PWM Control Register */ |
137fd45f | 26 | #define MX3_PWMSR 0x04 /* PWM Status Register */ |
40f260c2 LY |
27 | #define MX3_PWMSAR 0x0C /* PWM Sample Register */ |
28 | #define MX3_PWMPR 0x10 /* PWM Period Register */ | |
9f617ada MV |
29 | |
30 | #define MX3_PWMCR_FWM GENMASK(27, 26) | |
31 | #define MX3_PWMCR_STOPEN BIT(25) | |
32 | #define MX3_PWMCR_DOZEN BIT(24) | |
33 | #define MX3_PWMCR_WAITEN BIT(23) | |
34 | #define MX3_PWMCR_DBGEN BIT(22) | |
35 | #define MX3_PWMCR_BCTR BIT(21) | |
36 | #define MX3_PWMCR_HCTR BIT(20) | |
37 | ||
38 | #define MX3_PWMCR_POUTC GENMASK(19, 18) | |
39 | #define MX3_PWMCR_POUTC_NORMAL 0 | |
40 | #define MX3_PWMCR_POUTC_INVERTED 1 | |
41 | #define MX3_PWMCR_POUTC_OFF 2 | |
42 | ||
43 | #define MX3_PWMCR_CLKSRC GENMASK(17, 16) | |
44 | #define MX3_PWMCR_CLKSRC_OFF 0 | |
45 | #define MX3_PWMCR_CLKSRC_IPG 1 | |
46 | #define MX3_PWMCR_CLKSRC_IPG_HIGH 2 | |
47 | #define MX3_PWMCR_CLKSRC_IPG_32K 3 | |
48 | ||
49 | #define MX3_PWMCR_PRESCALER GENMASK(15, 4) | |
50 | ||
51 | #define MX3_PWMCR_SWR BIT(3) | |
52 | ||
53 | #define MX3_PWMCR_REPEAT GENMASK(2, 1) | |
54 | #define MX3_PWMCR_REPEAT_1X 0 | |
55 | #define MX3_PWMCR_REPEAT_2X 1 | |
56 | #define MX3_PWMCR_REPEAT_4X 2 | |
57 | #define MX3_PWMCR_REPEAT_8X 3 | |
58 | ||
59 | #define MX3_PWMCR_EN BIT(0) | |
60 | ||
61 | #define MX3_PWMSR_FWE BIT(6) | |
62 | #define MX3_PWMSR_CMP BIT(5) | |
63 | #define MX3_PWMSR_ROV BIT(4) | |
64 | #define MX3_PWMSR_FE BIT(3) | |
65 | ||
66 | #define MX3_PWMSR_FIFOAV GENMASK(2, 0) | |
67 | #define MX3_PWMSR_FIFOAV_EMPTY 0 | |
68 | #define MX3_PWMSR_FIFOAV_1WORD 1 | |
69 | #define MX3_PWMSR_FIFOAV_2WORDS 2 | |
70 | #define MX3_PWMSR_FIFOAV_3WORDS 3 | |
71 | #define MX3_PWMSR_FIFOAV_4WORDS 4 | |
72 | ||
73 | #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1) | |
74 | #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \ | |
75 | (x)) + 1) | |
137fd45f LY |
76 | |
77 | #define MX3_PWM_SWR_LOOP 5 | |
c010dba8 | 78 | |
bf9b0b1b MV |
79 | /* PWMPR register value of 0xffff has the same effect as 0xfffe */ |
80 | #define MX3_PWMPR_MAX 0xfffe | |
81 | ||
d80f8206 | 82 | struct pwm_imx27_chip { |
9f4c8f96 | 83 | struct clk *clk_ipg; |
7b27c160 | 84 | struct clk *clk_per; |
166091b1 | 85 | void __iomem *mmio_base; |
a3597d6c TR |
86 | |
87 | /* | |
88 | * The driver cannot read the current duty cycle from the hardware if | |
89 | * the hardware is disabled. Cache the last programmed duty cycle | |
90 | * value to return in that case. | |
91 | */ | |
92 | unsigned int duty_cycle; | |
166091b1 SH |
93 | }; |
94 | ||
dcef3929 UKK |
95 | static inline struct pwm_imx27_chip *to_pwm_imx27_chip(struct pwm_chip *chip) |
96 | { | |
97 | return pwmchip_get_drvdata(chip); | |
98 | } | |
29693248 | 99 | |
aad4e530 | 100 | static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx) |
9f4c8f96 | 101 | { |
9f4c8f96 AH |
102 | int ret; |
103 | ||
104 | ret = clk_prepare_enable(imx->clk_ipg); | |
105 | if (ret) | |
106 | return ret; | |
107 | ||
108 | ret = clk_prepare_enable(imx->clk_per); | |
109 | if (ret) { | |
110 | clk_disable_unprepare(imx->clk_ipg); | |
111 | return ret; | |
112 | } | |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
aad4e530 | 117 | static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx) |
9f4c8f96 | 118 | { |
9f4c8f96 AH |
119 | clk_disable_unprepare(imx->clk_per); |
120 | clk_disable_unprepare(imx->clk_ipg); | |
121 | } | |
122 | ||
6c452cff UKK |
123 | static int pwm_imx27_get_state(struct pwm_chip *chip, |
124 | struct pwm_device *pwm, struct pwm_state *state) | |
bf9b0b1b | 125 | { |
d80f8206 | 126 | struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); |
7ca17b20 | 127 | u32 period, prescaler, pwm_clk, val; |
bf9b0b1b | 128 | u64 tmp; |
7ca17b20 | 129 | int ret; |
bf9b0b1b | 130 | |
aad4e530 | 131 | ret = pwm_imx27_clk_prepare_enable(imx); |
9f4c8f96 | 132 | if (ret < 0) |
51b9f2fb | 133 | return ret; |
9f4c8f96 | 134 | |
bf9b0b1b MV |
135 | val = readl(imx->mmio_base + MX3_PWMCR); |
136 | ||
519ef9b5 | 137 | if (val & MX3_PWMCR_EN) |
bf9b0b1b | 138 | state->enabled = true; |
519ef9b5 | 139 | else |
bf9b0b1b | 140 | state->enabled = false; |
bf9b0b1b MV |
141 | |
142 | switch (FIELD_GET(MX3_PWMCR_POUTC, val)) { | |
143 | case MX3_PWMCR_POUTC_NORMAL: | |
144 | state->polarity = PWM_POLARITY_NORMAL; | |
145 | break; | |
146 | case MX3_PWMCR_POUTC_INVERTED: | |
147 | state->polarity = PWM_POLARITY_INVERSED; | |
148 | break; | |
149 | default: | |
175f53a7 | 150 | dev_warn(pwmchip_parent(chip), "can't set polarity, output disconnected"); |
bf9b0b1b MV |
151 | } |
152 | ||
153 | prescaler = MX3_PWMCR_PRESCALER_GET(val); | |
154 | pwm_clk = clk_get_rate(imx->clk_per); | |
bf9b0b1b MV |
155 | val = readl(imx->mmio_base + MX3_PWMPR); |
156 | period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val; | |
157 | ||
158 | /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */ | |
aef1a379 UKK |
159 | tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler; |
160 | state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk); | |
bf9b0b1b | 161 | |
a3597d6c TR |
162 | /* |
163 | * PWMSAR can be read only if PWM is enabled. If the PWM is disabled, | |
164 | * use the cached value. | |
165 | */ | |
166 | if (state->enabled) | |
bf9b0b1b | 167 | val = readl(imx->mmio_base + MX3_PWMSAR); |
a3597d6c TR |
168 | else |
169 | val = imx->duty_cycle; | |
170 | ||
aef1a379 UKK |
171 | tmp = NSEC_PER_SEC * (u64)(val) * prescaler; |
172 | state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk); | |
9f4c8f96 | 173 | |
2cb5cd90 | 174 | pwm_imx27_clk_disable_unprepare(imx); |
6c452cff UKK |
175 | |
176 | return 0; | |
66ad6a61 SH |
177 | } |
178 | ||
d80f8206 | 179 | static void pwm_imx27_sw_reset(struct pwm_chip *chip) |
19e73333 | 180 | { |
d80f8206 | 181 | struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); |
175f53a7 | 182 | struct device *dev = pwmchip_parent(chip); |
970247a4 LM |
183 | int wait_count = 0; |
184 | u32 cr; | |
185 | ||
186 | writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); | |
187 | do { | |
188 | usleep_range(200, 1000); | |
189 | cr = readl(imx->mmio_base + MX3_PWMCR); | |
190 | } while ((cr & MX3_PWMCR_SWR) && | |
191 | (wait_count++ < MX3_PWM_SWR_LOOP)); | |
192 | ||
193 | if (cr & MX3_PWMCR_SWR) | |
194 | dev_warn(dev, "software reset timeout\n"); | |
195 | } | |
19e73333 | 196 | |
d80f8206 UKK |
197 | static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip, |
198 | struct pwm_device *pwm) | |
73b1ff1f | 199 | { |
d80f8206 | 200 | struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); |
175f53a7 | 201 | struct device *dev = pwmchip_parent(chip); |
73b1ff1f LM |
202 | unsigned int period_ms; |
203 | int fifoav; | |
204 | u32 sr; | |
7b27c160 | 205 | |
73b1ff1f | 206 | sr = readl(imx->mmio_base + MX3_PWMSR); |
9f617ada | 207 | fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr); |
73b1ff1f | 208 | if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) { |
1706175c UKK |
209 | period_ms = DIV_ROUND_UP_ULL(pwm->state.period, |
210 | NSEC_PER_MSEC); | |
73b1ff1f | 211 | msleep(period_ms); |
7b27c160 | 212 | |
73b1ff1f | 213 | sr = readl(imx->mmio_base + MX3_PWMSR); |
9f617ada | 214 | if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr)) |
73b1ff1f LM |
215 | dev_warn(dev, "there is no free FIFO slot\n"); |
216 | } | |
19e73333 SH |
217 | } |
218 | ||
d80f8206 | 219 | static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
71523d18 | 220 | const struct pwm_state *state) |
166091b1 | 221 | { |
0ca1a11a | 222 | unsigned long period_cycles, duty_cycles, prescale; |
d80f8206 | 223 | struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); |
0ca1a11a | 224 | unsigned long long c; |
aef1a379 | 225 | unsigned long long clkrate; |
140827c1 | 226 | int ret; |
326ed314 | 227 | u32 cr; |
0ca1a11a | 228 | |
aef1a379 UKK |
229 | clkrate = clk_get_rate(imx->clk_per); |
230 | c = clkrate * state->period; | |
166091b1 | 231 | |
aef1a379 | 232 | do_div(c, NSEC_PER_SEC); |
bd88d319 TR |
233 | period_cycles = c; |
234 | ||
235 | prescale = period_cycles / 0x10000 + 1; | |
236 | ||
237 | period_cycles /= prescale; | |
aef1a379 | 238 | c = clkrate * state->duty_cycle; |
1ce65396 | 239 | do_div(c, NSEC_PER_SEC); |
bd88d319 | 240 | duty_cycles = c; |
1ce65396 | 241 | duty_cycles /= prescale; |
bd88d319 TR |
242 | |
243 | /* | |
244 | * according to imx pwm RM, the real period value should be PERIOD | |
245 | * value in PWMPR plus 2. | |
246 | */ | |
247 | if (period_cycles > 2) | |
248 | period_cycles -= 2; | |
249 | else | |
250 | period_cycles = 0; | |
251 | ||
252 | /* | |
253 | * Wait for a free FIFO slot if the PWM is already enabled, and flush | |
254 | * the FIFO if the PWM was disabled and is about to be enabled. | |
255 | */ | |
1706175c | 256 | if (pwm->state.enabled) { |
bd88d319 TR |
257 | pwm_imx27_wait_fifo_slot(chip, pwm); |
258 | } else { | |
aad4e530 | 259 | ret = pwm_imx27_clk_prepare_enable(imx); |
bd88d319 TR |
260 | if (ret) |
261 | return ret; | |
262 | ||
263 | pwm_imx27_sw_reset(chip); | |
0ca1a11a | 264 | } |
166091b1 | 265 | |
bd88d319 TR |
266 | writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); |
267 | writel(period_cycles, imx->mmio_base + MX3_PWMPR); | |
268 | ||
269 | /* | |
270 | * Store the duty cycle for future reference in cases where the | |
271 | * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled). | |
272 | */ | |
273 | imx->duty_cycle = duty_cycles; | |
274 | ||
275 | cr = MX3_PWMCR_PRESCALER_SET(prescale) | | |
276 | MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | | |
277 | FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) | | |
278 | MX3_PWMCR_DBGEN; | |
279 | ||
280 | if (state->polarity == PWM_POLARITY_INVERSED) | |
281 | cr |= FIELD_PREP(MX3_PWMCR_POUTC, | |
282 | MX3_PWMCR_POUTC_INVERTED); | |
283 | ||
284 | if (state->enabled) | |
285 | cr |= MX3_PWMCR_EN; | |
286 | ||
287 | writel(cr, imx->mmio_base + MX3_PWMCR); | |
288 | ||
15d4dbd6 | 289 | if (!state->enabled) |
aad4e530 | 290 | pwm_imx27_clk_disable_unprepare(imx); |
bd88d319 | 291 | |
0ca1a11a | 292 | return 0; |
166091b1 | 293 | } |
166091b1 | 294 | |
d80f8206 UKK |
295 | static const struct pwm_ops pwm_imx27_ops = { |
296 | .apply = pwm_imx27_apply, | |
297 | .get_state = pwm_imx27_get_state, | |
29693248 | 298 | }; |
166091b1 | 299 | |
d80f8206 UKK |
300 | static const struct of_device_id pwm_imx27_dt_ids[] = { |
301 | { .compatible = "fsl,imx27-pwm", }, | |
479e2e30 PZ |
302 | { /* sentinel */ } |
303 | }; | |
d80f8206 | 304 | MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids); |
479e2e30 | 305 | |
d80f8206 | 306 | static int pwm_imx27_probe(struct platform_device *pdev) |
166091b1 | 307 | { |
dcef3929 | 308 | struct pwm_chip *chip; |
d80f8206 | 309 | struct pwm_imx27_chip *imx; |
2cb5cd90 UKK |
310 | int ret; |
311 | u32 pwmcr; | |
166091b1 | 312 | |
dcef3929 UKK |
313 | chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*imx)); |
314 | if (IS_ERR(chip)) | |
315 | return PTR_ERR(chip); | |
316 | imx = to_pwm_imx27_chip(chip); | |
166091b1 | 317 | |
9f4c8f96 | 318 | imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
d109d74c AH |
319 | if (IS_ERR(imx->clk_ipg)) |
320 | return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg), | |
321 | "getting ipg clock failed\n"); | |
9f4c8f96 | 322 | |
7b27c160 | 323 | imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
d109d74c AH |
324 | if (IS_ERR(imx->clk_per)) |
325 | return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per), | |
326 | "failed to get peripheral clock\n"); | |
166091b1 | 327 | |
dcef3929 | 328 | chip->ops = &pwm_imx27_ops; |
166091b1 | 329 | |
1347c94f | 330 | imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); |
6d4294d1 TR |
331 | if (IS_ERR(imx->mmio_base)) |
332 | return PTR_ERR(imx->mmio_base); | |
166091b1 | 333 | |
2cb5cd90 UKK |
334 | ret = pwm_imx27_clk_prepare_enable(imx); |
335 | if (ret) | |
336 | return ret; | |
337 | ||
338 | /* keep clks on if pwm is running */ | |
339 | pwmcr = readl(imx->mmio_base + MX3_PWMCR); | |
340 | if (!(pwmcr & MX3_PWMCR_EN)) | |
341 | pwm_imx27_clk_disable_unprepare(imx); | |
342 | ||
dcef3929 | 343 | return devm_pwmchip_add(&pdev->dev, chip); |
166091b1 SH |
344 | } |
345 | ||
29693248 | 346 | static struct platform_driver imx_pwm_driver = { |
d80f8206 UKK |
347 | .driver = { |
348 | .name = "pwm-imx27", | |
349 | .of_match_table = pwm_imx27_dt_ids, | |
166091b1 | 350 | }, |
d80f8206 | 351 | .probe = pwm_imx27_probe, |
166091b1 | 352 | }; |
208d038f | 353 | module_platform_driver(imx_pwm_driver); |
166091b1 | 354 | |
2c69747c | 355 | MODULE_DESCRIPTION("i.MX27 and later i.MX SoCs Pulse Width Modulator driver"); |
166091b1 SH |
356 | MODULE_LICENSE("GPL v2"); |
357 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |