[linux-block.git] / drivers / pwm / pwm-imx27.c

// SPDX-License-Identifier: GPL-2.0
/*
 * simple driver for PWM (Pulse Width Modulator) controller
 *
 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
 *
 * Limitations:
 * - When disabled the output is driven to 0 independent of the configured
 *   polarity.
 */

#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

#define MX3_PWMCR			0x00    /* PWM Control Register */
#define MX3_PWMSR			0x04    /* PWM Status Register */
#define MX3_PWMSAR			0x0C    /* PWM Sample Register */
#define MX3_PWMPR			0x10    /* PWM Period Register */

#define MX3_PWMCR_FWM			GENMASK(27, 26)
#define MX3_PWMCR_STOPEN		BIT(25)
#define MX3_PWMCR_DOZEN			BIT(24)
#define MX3_PWMCR_WAITEN		BIT(23)
#define MX3_PWMCR_DBGEN			BIT(22)
#define MX3_PWMCR_BCTR			BIT(21)
#define MX3_PWMCR_HCTR			BIT(20)

#define MX3_PWMCR_POUTC			GENMASK(19, 18)
#define MX3_PWMCR_POUTC_NORMAL		0
#define MX3_PWMCR_POUTC_INVERTED	1
#define MX3_PWMCR_POUTC_OFF		2

#define MX3_PWMCR_CLKSRC		GENMASK(17, 16)
#define MX3_PWMCR_CLKSRC_OFF		0
#define MX3_PWMCR_CLKSRC_IPG		1
#define MX3_PWMCR_CLKSRC_IPG_HIGH	2
#define MX3_PWMCR_CLKSRC_IPG_32K	3

#define MX3_PWMCR_PRESCALER		GENMASK(15, 4)

#define MX3_PWMCR_SWR			BIT(3)

#define MX3_PWMCR_REPEAT		GENMASK(2, 1)
#define MX3_PWMCR_REPEAT_1X		0
#define MX3_PWMCR_REPEAT_2X		1
#define MX3_PWMCR_REPEAT_4X		2
#define MX3_PWMCR_REPEAT_8X		3

#define MX3_PWMCR_EN			BIT(0)

#define MX3_PWMSR_FWE			BIT(6)
#define MX3_PWMSR_CMP			BIT(5)
#define MX3_PWMSR_ROV			BIT(4)
#define MX3_PWMSR_FE			BIT(3)

#define MX3_PWMSR_FIFOAV		GENMASK(2, 0)
#define MX3_PWMSR_FIFOAV_EMPTY		0
#define MX3_PWMSR_FIFOAV_1WORD		1
#define MX3_PWMSR_FIFOAV_2WORDS		2
#define MX3_PWMSR_FIFOAV_3WORDS		3
#define MX3_PWMSR_FIFOAV_4WORDS		4

#define MX3_PWMCR_PRESCALER_SET(x)	FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
#define MX3_PWMCR_PRESCALER_GET(x)	(FIELD_GET(MX3_PWMCR_PRESCALER, \
						   (x)) + 1)

#define MX3_PWM_SWR_LOOP		5

/* PWMPR register value of 0xffff has the same effect as 0xfffe */
#define MX3_PWMPR_MAX			0xfffe

struct pwm_imx27_chip {
	struct clk	*clk_ipg;
	struct clk	*clk_per;
	void __iomem	*mmio_base;
	struct pwm_chip	chip;

	/*
	 * The driver cannot read the current duty cycle from the hardware if
	 * the hardware is disabled. Cache the last programmed duty cycle
	 * value to return in that case.
	 */
	unsigned int duty_cycle;
};

#define to_pwm_imx27_chip(chip)	container_of(chip, struct pwm_imx27_chip, chip)

static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
{
	int ret;

	ret = clk_prepare_enable(imx->clk_ipg);
	if (ret)
		return ret;

	ret = clk_prepare_enable(imx->clk_per);
	if (ret) {
		clk_disable_unprepare(imx->clk_ipg);
		return ret;
	}

	return 0;
}

static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
{
	clk_disable_unprepare(imx->clk_per);
	clk_disable_unprepare(imx->clk_ipg);
}

static void pwm_imx27_get_state(struct pwm_chip *chip,
				struct pwm_device *pwm, struct pwm_state *state)
{
	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
	u32 period, prescaler, pwm_clk, val;
	u64 tmp;
	int ret;

	ret = pwm_imx27_clk_prepare_enable(imx);
	if (ret < 0)
		return;

	val = readl(imx->mmio_base + MX3_PWMCR);

	if (val & MX3_PWMCR_EN)
		state->enabled = true;
	else
		state->enabled = false;

	switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
	case MX3_PWMCR_POUTC_NORMAL:
		state->polarity = PWM_POLARITY_NORMAL;
		break;
	case MX3_PWMCR_POUTC_INVERTED:
		state->polarity = PWM_POLARITY_INVERSED;
		break;
	default:
		dev_warn(chip->dev, "can't set polarity, output disconnected");
	}

	prescaler = MX3_PWMCR_PRESCALER_GET(val);
	pwm_clk = clk_get_rate(imx->clk_per);
	val = readl(imx->mmio_base + MX3_PWMPR);
	period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;

	/* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
	tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
	state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);

	/*
	 * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
	 * use the cached value.
	 */
	if (state->enabled)
		val = readl(imx->mmio_base + MX3_PWMSAR);
	else
		val = imx->duty_cycle;

	tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
	state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);

	pwm_imx27_clk_disable_unprepare(imx);
}

static void pwm_imx27_sw_reset(struct pwm_chip *chip)
{
	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
	struct device *dev = chip->dev;
	int wait_count = 0;
	u32 cr;

	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
	do {
		usleep_range(200, 1000);
		cr = readl(imx->mmio_base + MX3_PWMCR);
	} while ((cr & MX3_PWMCR_SWR) &&
		 (wait_count++ < MX3_PWM_SWR_LOOP));

	if (cr & MX3_PWMCR_SWR)
		dev_warn(dev, "software reset timeout\n");
}

static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
				     struct pwm_device *pwm)
{
	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
	struct device *dev = chip->dev;
	unsigned int period_ms;
	int fifoav;
	u32 sr;

	sr = readl(imx->mmio_base + MX3_PWMSR);
	fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
		period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
					 NSEC_PER_MSEC);
		msleep(period_ms);

		sr = readl(imx->mmio_base + MX3_PWMSR);
		if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
			dev_warn(dev, "there is no free FIFO slot\n");
	}
}

static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	unsigned long period_cycles, duty_cycles, prescale;
	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
	struct pwm_state cstate;
	unsigned long long c;
	unsigned long long clkrate;
	int ret;
	u32 cr;

	pwm_get_state(pwm, &cstate);

	clkrate = clk_get_rate(imx->clk_per);
	c = clkrate * state->period;

	do_div(c, NSEC_PER_SEC);
	period_cycles = c;

	prescale = period_cycles / 0x10000 + 1;

	period_cycles /= prescale;
	c = clkrate * state->duty_cycle;
	do_div(c, NSEC_PER_SEC * prescale);
	duty_cycles = c;

	/*
	 * according to imx pwm RM, the real period value should be PERIOD
	 * value in PWMPR plus 2.
	 */
	if (period_cycles > 2)
		period_cycles -= 2;
	else
		period_cycles = 0;

	/*
	 * Wait for a free FIFO slot if the PWM is already enabled, and flush
	 * the FIFO if the PWM was disabled and is about to be enabled.
	 */
	if (cstate.enabled) {
		pwm_imx27_wait_fifo_slot(chip, pwm);
	} else {
		ret = pwm_imx27_clk_prepare_enable(imx);
		if (ret)
			return ret;

		pwm_imx27_sw_reset(chip);
	}

	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
	writel(period_cycles, imx->mmio_base + MX3_PWMPR);

	/*
	 * Store the duty cycle for future reference in cases where the
	 * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
	 */
	imx->duty_cycle = duty_cycles;

	cr = MX3_PWMCR_PRESCALER_SET(prescale) |
	     MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
	     FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
	     MX3_PWMCR_DBGEN;

	if (state->polarity == PWM_POLARITY_INVERSED)
		cr |= FIELD_PREP(MX3_PWMCR_POUTC,
				MX3_PWMCR_POUTC_INVERTED);

	if (state->enabled)
		cr |= MX3_PWMCR_EN;

	writel(cr, imx->mmio_base + MX3_PWMCR);

	if (!state->enabled)
		pwm_imx27_clk_disable_unprepare(imx);

	return 0;
}

static const struct pwm_ops pwm_imx27_ops = {
	.apply = pwm_imx27_apply,
	.get_state = pwm_imx27_get_state,
	.owner = THIS_MODULE,
};

static const struct of_device_id pwm_imx27_dt_ids[] = {
	{ .compatible = "fsl,imx27-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);

static int pwm_imx27_probe(struct platform_device *pdev)
{
	struct pwm_imx27_chip *imx;
	int ret;
	u32 pwmcr;

	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
	if (imx == NULL)
		return -ENOMEM;

	platform_set_drvdata(pdev, imx);

	imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(imx->clk_ipg)) {
		int ret = PTR_ERR(imx->clk_ipg);

		if (ret != -EPROBE_DEFER)
			dev_err(&pdev->dev,
				"getting ipg clock failed with %d\n",
				ret);
		return ret;
	}

	imx->clk_per = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(imx->clk_per)) {
		int ret = PTR_ERR(imx->clk_per);

		if (ret != -EPROBE_DEFER)
			dev_err(&pdev->dev,
				"failed to get peripheral clock: %d\n",
				ret);

		return ret;
	}

	imx->chip.ops = &pwm_imx27_ops;
	imx->chip.dev = &pdev->dev;
	imx->chip.base = -1;
	imx->chip.npwm = 1;

	imx->chip.of_xlate = of_pwm_xlate_with_flags;
	imx->chip.of_pwm_n_cells = 3;

	imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(imx->mmio_base))
		return PTR_ERR(imx->mmio_base);

	ret = pwm_imx27_clk_prepare_enable(imx);
	if (ret)
		return ret;

	/* keep clks on if pwm is running */
	pwmcr = readl(imx->mmio_base + MX3_PWMCR);
	if (!(pwmcr & MX3_PWMCR_EN))
		pwm_imx27_clk_disable_unprepare(imx);

	return pwmchip_add(&imx->chip);
}

static int pwm_imx27_remove(struct platform_device *pdev)
{
	struct pwm_imx27_chip *imx;

	imx = platform_get_drvdata(pdev);

	return pwmchip_remove(&imx->chip);
}

static struct platform_driver imx_pwm_driver = {
	.driver = {
		.name = "pwm-imx27",
		.of_match_table = pwm_imx27_dt_ids,
	},
	.probe = pwm_imx27_probe,
	.remove = pwm_imx27_remove,
};
module_platform_driver(imx_pwm_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Commit	Line	Data
a99290c5	1	// SPDX-License-Identifier: GPL-2.0
166091b1 SH	2	/*
	3	* simple driver for PWM (Pulse Width Modulator) controller
	4	*
166091b1	5	* Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
f6960976 UKK	6	*
	7	* Limitations:
	8	* - When disabled the output is driven to 0 independent of the configured
	9	* polarity.
166091b1 SH	10	*/
166091b1 SH	11
9f617ada MV	12	#include <linux/bitfield.h>
9f617ada MV	13	#include <linux/bitops.h>
166091b1	14	#include <linux/clk.h>
137fd45f	15	#include <linux/delay.h>
e3adc7ef	16	#include <linux/err.h>
166091b1	17	#include <linux/io.h>
e3adc7ef MV	18	#include <linux/kernel.h>
e3adc7ef MV	19	#include <linux/module.h>
2a8876cf	20	#include <linux/of.h>
e3adc7ef MV	21	#include <linux/platform_device.h>
	22	#include <linux/pwm.h>
	23	#include <linux/slab.h>
c010dba8	24
40f260c2	25	#define MX3_PWMCR 0x00 /* PWM Control Register */
137fd45f	26	#define MX3_PWMSR 0x04 /* PWM Status Register */
40f260c2 LY	27	#define MX3_PWMSAR 0x0C /* PWM Sample Register */
40f260c2 LY	28	#define MX3_PWMPR 0x10 /* PWM Period Register */
9f617ada MV	29
	30	#define MX3_PWMCR_FWM GENMASK(27, 26)
	31	#define MX3_PWMCR_STOPEN BIT(25)
	32	#define MX3_PWMCR_DOZEN BIT(24)
	33	#define MX3_PWMCR_WAITEN BIT(23)
	34	#define MX3_PWMCR_DBGEN BIT(22)
	35	#define MX3_PWMCR_BCTR BIT(21)
	36	#define MX3_PWMCR_HCTR BIT(20)
	37
	38	#define MX3_PWMCR_POUTC GENMASK(19, 18)
	39	#define MX3_PWMCR_POUTC_NORMAL 0
	40	#define MX3_PWMCR_POUTC_INVERTED 1
	41	#define MX3_PWMCR_POUTC_OFF 2
	42
	43	#define MX3_PWMCR_CLKSRC GENMASK(17, 16)
	44	#define MX3_PWMCR_CLKSRC_OFF 0
	45	#define MX3_PWMCR_CLKSRC_IPG 1
	46	#define MX3_PWMCR_CLKSRC_IPG_HIGH 2
	47	#define MX3_PWMCR_CLKSRC_IPG_32K 3
	48
	49	#define MX3_PWMCR_PRESCALER GENMASK(15, 4)
	50
	51	#define MX3_PWMCR_SWR BIT(3)
	52
	53	#define MX3_PWMCR_REPEAT GENMASK(2, 1)
	54	#define MX3_PWMCR_REPEAT_1X 0
	55	#define MX3_PWMCR_REPEAT_2X 1
	56	#define MX3_PWMCR_REPEAT_4X 2
	57	#define MX3_PWMCR_REPEAT_8X 3
	58
	59	#define MX3_PWMCR_EN BIT(0)
	60
	61	#define MX3_PWMSR_FWE BIT(6)
	62	#define MX3_PWMSR_CMP BIT(5)
	63	#define MX3_PWMSR_ROV BIT(4)
	64	#define MX3_PWMSR_FE BIT(3)
	65
	66	#define MX3_PWMSR_FIFOAV GENMASK(2, 0)
	67	#define MX3_PWMSR_FIFOAV_EMPTY 0
	68	#define MX3_PWMSR_FIFOAV_1WORD 1
	69	#define MX3_PWMSR_FIFOAV_2WORDS 2
	70	#define MX3_PWMSR_FIFOAV_3WORDS 3
	71	#define MX3_PWMSR_FIFOAV_4WORDS 4
	72
	73	#define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
	74	#define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \
	75	(x)) + 1)
137fd45f LY	76
137fd45f LY	77	#define MX3_PWM_SWR_LOOP 5
c010dba8	78
bf9b0b1b MV	79	/* PWMPR register value of 0xffff has the same effect as 0xfffe */
	80	#define MX3_PWMPR_MAX 0xfffe
	81
d80f8206	82	struct pwm_imx27_chip {
9f4c8f96	83	struct clk *clk_ipg;
7b27c160	84	struct clk *clk_per;
166091b1	85	void __iomem *mmio_base;
29693248	86	struct pwm_chip chip;
a3597d6c TR	87
	88	/*
	89	* The driver cannot read the current duty cycle from the hardware if
	90	* the hardware is disabled. Cache the last programmed duty cycle
	91	* value to return in that case.
	92	*/
	93	unsigned int duty_cycle;
166091b1 SH	94	};
166091b1 SH	95
d80f8206	96	#define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip)
29693248	97
aad4e530	98	static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
9f4c8f96	99	{
9f4c8f96 AH	100	int ret;
	101
	102	ret = clk_prepare_enable(imx->clk_ipg);
	103	if (ret)
	104	return ret;
	105
	106	ret = clk_prepare_enable(imx->clk_per);
	107	if (ret) {
	108	clk_disable_unprepare(imx->clk_ipg);
	109	return ret;
	110	}
	111
	112	return 0;
	113	}
	114
aad4e530	115	static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
9f4c8f96	116	{
9f4c8f96 AH	117	clk_disable_unprepare(imx->clk_per);
	118	clk_disable_unprepare(imx->clk_ipg);
	119	}
	120
d80f8206 UKK	121	static void pwm_imx27_get_state(struct pwm_chip *chip,
d80f8206 UKK	122	struct pwm_device pwm, struct pwm_state state)
bf9b0b1b	123	{
d80f8206	124	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
7ca17b20	125	u32 period, prescaler, pwm_clk, val;
bf9b0b1b	126	u64 tmp;
7ca17b20	127	int ret;
bf9b0b1b	128
aad4e530	129	ret = pwm_imx27_clk_prepare_enable(imx);
9f4c8f96 AH	130	if (ret < 0)
	131	return;
	132
bf9b0b1b MV	133	val = readl(imx->mmio_base + MX3_PWMCR);
bf9b0b1b MV	134
519ef9b5	135	if (val & MX3_PWMCR_EN)
bf9b0b1b	136	state->enabled = true;
519ef9b5	137	else
bf9b0b1b	138	state->enabled = false;
bf9b0b1b MV	139
	140	switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
	141	case MX3_PWMCR_POUTC_NORMAL:
	142	state->polarity = PWM_POLARITY_NORMAL;
	143	break;
	144	case MX3_PWMCR_POUTC_INVERTED:
	145	state->polarity = PWM_POLARITY_INVERSED;
	146	break;
	147	default:
	148	dev_warn(chip->dev, "can't set polarity, output disconnected");
	149	}
	150
	151	prescaler = MX3_PWMCR_PRESCALER_GET(val);
	152	pwm_clk = clk_get_rate(imx->clk_per);
bf9b0b1b MV	153	val = readl(imx->mmio_base + MX3_PWMPR);
	154	period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
	155
	156	/* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
aef1a379 UKK	157	tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
aef1a379 UKK	158	state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
bf9b0b1b	159
a3597d6c TR	160	/*
	161	* PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
	162	* use the cached value.
	163	*/
	164	if (state->enabled)
bf9b0b1b	165	val = readl(imx->mmio_base + MX3_PWMSAR);
a3597d6c TR	166	else
	167	val = imx->duty_cycle;
	168
aef1a379 UKK	169	tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
aef1a379 UKK	170	state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
9f4c8f96	171
2cb5cd90	172	pwm_imx27_clk_disable_unprepare(imx);
66ad6a61 SH	173	}
66ad6a61 SH	174
d80f8206	175	static void pwm_imx27_sw_reset(struct pwm_chip *chip)
19e73333	176	{
d80f8206	177	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
970247a4 LM	178	struct device *dev = chip->dev;
	179	int wait_count = 0;
	180	u32 cr;
	181
	182	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
	183	do {
	184	usleep_range(200, 1000);
	185	cr = readl(imx->mmio_base + MX3_PWMCR);
	186	} while ((cr & MX3_PWMCR_SWR) &&
	187	(wait_count++ < MX3_PWM_SWR_LOOP));
	188
	189	if (cr & MX3_PWMCR_SWR)
	190	dev_warn(dev, "software reset timeout\n");
	191	}
19e73333	192
d80f8206 UKK	193	static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
d80f8206 UKK	194	struct pwm_device *pwm)
73b1ff1f	195	{
d80f8206	196	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
73b1ff1f LM	197	struct device *dev = chip->dev;
	198	unsigned int period_ms;
	199	int fifoav;
	200	u32 sr;
7b27c160	201
73b1ff1f	202	sr = readl(imx->mmio_base + MX3_PWMSR);
9f617ada	203	fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
73b1ff1f	204	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
1689dcd4	205	period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
73b1ff1f LM	206	NSEC_PER_MSEC);
73b1ff1f LM	207	msleep(period_ms);
7b27c160	208
73b1ff1f	209	sr = readl(imx->mmio_base + MX3_PWMSR);
9f617ada	210	if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
73b1ff1f LM	211	dev_warn(dev, "there is no free FIFO slot\n");
73b1ff1f LM	212	}
19e73333 SH	213	}
19e73333 SH	214
d80f8206	215	static int pwm_imx27_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	216	const struct pwm_state *state)
166091b1	217	{
0ca1a11a	218	unsigned long period_cycles, duty_cycles, prescale;
d80f8206	219	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
0ca1a11a LM	220	struct pwm_state cstate;
0ca1a11a LM	221	unsigned long long c;
aef1a379	222	unsigned long long clkrate;
140827c1	223	int ret;
326ed314	224	u32 cr;
0ca1a11a LM	225
	226	pwm_get_state(pwm, &cstate);
	227
aef1a379 UKK	228	clkrate = clk_get_rate(imx->clk_per);
aef1a379 UKK	229	c = clkrate * state->period;
166091b1	230
aef1a379	231	do_div(c, NSEC_PER_SEC);
bd88d319 TR	232	period_cycles = c;
	233
	234	prescale = period_cycles / 0x10000 + 1;
	235
	236	period_cycles /= prescale;
aef1a379 UKK	237	c = clkrate * state->duty_cycle;
aef1a379 UKK	238	do_div(c, NSEC_PER_SEC * prescale);
bd88d319 TR	239	duty_cycles = c;
	240
	241	/*
	242	* according to imx pwm RM, the real period value should be PERIOD
	243	* value in PWMPR plus 2.
	244	*/
	245	if (period_cycles > 2)
	246	period_cycles -= 2;
	247	else
	248	period_cycles = 0;
	249
	250	/*
	251	* Wait for a free FIFO slot if the PWM is already enabled, and flush
	252	* the FIFO if the PWM was disabled and is about to be enabled.
	253	*/
	254	if (cstate.enabled) {
	255	pwm_imx27_wait_fifo_slot(chip, pwm);
	256	} else {
aad4e530	257	ret = pwm_imx27_clk_prepare_enable(imx);
bd88d319 TR	258	if (ret)
	259	return ret;
	260
	261	pwm_imx27_sw_reset(chip);
0ca1a11a	262	}
166091b1	263
bd88d319 TR	264	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
	265	writel(period_cycles, imx->mmio_base + MX3_PWMPR);
	266
	267	/*
	268	* Store the duty cycle for future reference in cases where the
	269	* MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
	270	*/
	271	imx->duty_cycle = duty_cycles;
	272
	273	cr = MX3_PWMCR_PRESCALER_SET(prescale) \|
	274	MX3_PWMCR_STOPEN \| MX3_PWMCR_DOZEN \| MX3_PWMCR_WAITEN \|
	275	FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) \|
	276	MX3_PWMCR_DBGEN;
	277
	278	if (state->polarity == PWM_POLARITY_INVERSED)
	279	cr \|= FIELD_PREP(MX3_PWMCR_POUTC,
	280	MX3_PWMCR_POUTC_INVERTED);
	281
	282	if (state->enabled)
	283	cr \|= MX3_PWMCR_EN;
	284
	285	writel(cr, imx->mmio_base + MX3_PWMCR);
	286
15d4dbd6	287	if (!state->enabled)
aad4e530	288	pwm_imx27_clk_disable_unprepare(imx);
bd88d319	289
0ca1a11a	290	return 0;
166091b1	291	}
166091b1	292
d80f8206 UKK	293	static const struct pwm_ops pwm_imx27_ops = {
	294	.apply = pwm_imx27_apply,
	295	.get_state = pwm_imx27_get_state,
29693248 SH	296	.owner = THIS_MODULE,
29693248 SH	297	};
166091b1	298
d80f8206 UKK	299	static const struct of_device_id pwm_imx27_dt_ids[] = {
d80f8206 UKK	300	{ .compatible = "fsl,imx27-pwm", },
479e2e30 PZ	301	{ /* sentinel */ }
479e2e30 PZ	302	};
d80f8206	303	MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
479e2e30	304
d80f8206	305	static int pwm_imx27_probe(struct platform_device *pdev)
166091b1	306	{
d80f8206	307	struct pwm_imx27_chip *imx;
2cb5cd90 UKK	308	int ret;
2cb5cd90 UKK	309	u32 pwmcr;
166091b1	310
a9970e3b	311	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
1cbec749	312	if (imx == NULL)
166091b1	313	return -ENOMEM;
166091b1	314
f20b187e UKK	315	platform_set_drvdata(pdev, imx);
f20b187e UKK	316
9f4c8f96 AH	317	imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
9f4c8f96 AH	318	if (IS_ERR(imx->clk_ipg)) {
a368c343 AH	319	int ret = PTR_ERR(imx->clk_ipg);
	320
	321	if (ret != -EPROBE_DEFER)
	322	dev_err(&pdev->dev,
	323	"getting ipg clock failed with %d\n",
	324	ret);
	325	return ret;
9f4c8f96 AH	326	}
9f4c8f96 AH	327
7b27c160 PZ	328	imx->clk_per = devm_clk_get(&pdev->dev, "per");
7b27c160 PZ	329	if (IS_ERR(imx->clk_per)) {
b9a5c60b UKK	330	int ret = PTR_ERR(imx->clk_per);
	331
	332	if (ret != -EPROBE_DEFER)
	333	dev_err(&pdev->dev,
	334	"failed to get peripheral clock: %d\n",
	335	ret);
	336
	337	return ret;
7b27c160	338	}
166091b1	339
d80f8206	340	imx->chip.ops = &pwm_imx27_ops;
29693248 SH	341	imx->chip.dev = &pdev->dev;
	342	imx->chip.base = -1;
	343	imx->chip.npwm = 1;
166091b1	344
d80f8206 UKK	345	imx->chip.of_xlate = of_pwm_xlate_with_flags;
d80f8206 UKK	346	imx->chip.of_pwm_n_cells = 3;
326ed314	347
1347c94f	348	imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
6d4294d1 TR	349	if (IS_ERR(imx->mmio_base))
6d4294d1 TR	350	return PTR_ERR(imx->mmio_base);
166091b1	351
2cb5cd90 UKK	352	ret = pwm_imx27_clk_prepare_enable(imx);
	353	if (ret)
	354	return ret;
	355
	356	/* keep clks on if pwm is running */
	357	pwmcr = readl(imx->mmio_base + MX3_PWMCR);
	358	if (!(pwmcr & MX3_PWMCR_EN))
	359	pwm_imx27_clk_disable_unprepare(imx);
	360
f20b187e	361	return pwmchip_add(&imx->chip);
166091b1 SH	362	}
166091b1 SH	363
d80f8206	364	static int pwm_imx27_remove(struct platform_device *pdev)
166091b1	365	{
d80f8206	366	struct pwm_imx27_chip *imx;
166091b1	367
29693248	368	imx = platform_get_drvdata(pdev);
166091b1	369
a9970e3b	370	return pwmchip_remove(&imx->chip);
166091b1 SH	371	}
166091b1 SH	372
29693248	373	static struct platform_driver imx_pwm_driver = {
d80f8206 UKK	374	.driver = {
	375	.name = "pwm-imx27",
	376	.of_match_table = pwm_imx27_dt_ids,
166091b1	377	},
d80f8206 UKK	378	.probe = pwm_imx27_probe,
d80f8206 UKK	379	.remove = pwm_imx27_remove,
166091b1	380	};
208d038f	381	module_platform_driver(imx_pwm_driver);
166091b1 SH	382
	383	MODULE_LICENSE("GPL v2");
	384	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");