Commit | Line | Data |
---|---|---|
a99290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
166091b1 SH |
2 | /* |
3 | * simple driver for PWM (Pulse Width Modulator) controller | |
4 | * | |
166091b1 | 5 | * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> |
f6960976 UKK |
6 | * |
7 | * Limitations: | |
8 | * - When disabled the output is driven to 0 independent of the configured | |
9 | * polarity. | |
166091b1 SH |
10 | */ |
11 | ||
9f617ada MV |
12 | #include <linux/bitfield.h> |
13 | #include <linux/bitops.h> | |
166091b1 | 14 | #include <linux/clk.h> |
137fd45f | 15 | #include <linux/delay.h> |
e3adc7ef | 16 | #include <linux/err.h> |
166091b1 | 17 | #include <linux/io.h> |
e3adc7ef MV |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | |
2a8876cf | 20 | #include <linux/of.h> |
e3adc7ef MV |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pwm.h> | |
23 | #include <linux/slab.h> | |
c010dba8 | 24 | |
40f260c2 | 25 | #define MX3_PWMCR 0x00 /* PWM Control Register */ |
137fd45f | 26 | #define MX3_PWMSR 0x04 /* PWM Status Register */ |
40f260c2 LY |
27 | #define MX3_PWMSAR 0x0C /* PWM Sample Register */ |
28 | #define MX3_PWMPR 0x10 /* PWM Period Register */ | |
9f617ada MV |
29 | |
30 | #define MX3_PWMCR_FWM GENMASK(27, 26) | |
31 | #define MX3_PWMCR_STOPEN BIT(25) | |
32 | #define MX3_PWMCR_DOZEN BIT(24) | |
33 | #define MX3_PWMCR_WAITEN BIT(23) | |
34 | #define MX3_PWMCR_DBGEN BIT(22) | |
35 | #define MX3_PWMCR_BCTR BIT(21) | |
36 | #define MX3_PWMCR_HCTR BIT(20) | |
37 | ||
38 | #define MX3_PWMCR_POUTC GENMASK(19, 18) | |
39 | #define MX3_PWMCR_POUTC_NORMAL 0 | |
40 | #define MX3_PWMCR_POUTC_INVERTED 1 | |
41 | #define MX3_PWMCR_POUTC_OFF 2 | |
42 | ||
43 | #define MX3_PWMCR_CLKSRC GENMASK(17, 16) | |
44 | #define MX3_PWMCR_CLKSRC_OFF 0 | |
45 | #define MX3_PWMCR_CLKSRC_IPG 1 | |
46 | #define MX3_PWMCR_CLKSRC_IPG_HIGH 2 | |
47 | #define MX3_PWMCR_CLKSRC_IPG_32K 3 | |
48 | ||
49 | #define MX3_PWMCR_PRESCALER GENMASK(15, 4) | |
50 | ||
51 | #define MX3_PWMCR_SWR BIT(3) | |
52 | ||
53 | #define MX3_PWMCR_REPEAT GENMASK(2, 1) | |
54 | #define MX3_PWMCR_REPEAT_1X 0 | |
55 | #define MX3_PWMCR_REPEAT_2X 1 | |
56 | #define MX3_PWMCR_REPEAT_4X 2 | |
57 | #define MX3_PWMCR_REPEAT_8X 3 | |
58 | ||
59 | #define MX3_PWMCR_EN BIT(0) | |
60 | ||
61 | #define MX3_PWMSR_FWE BIT(6) | |
62 | #define MX3_PWMSR_CMP BIT(5) | |
63 | #define MX3_PWMSR_ROV BIT(4) | |
64 | #define MX3_PWMSR_FE BIT(3) | |
65 | ||
66 | #define MX3_PWMSR_FIFOAV GENMASK(2, 0) | |
67 | #define MX3_PWMSR_FIFOAV_EMPTY 0 | |
68 | #define MX3_PWMSR_FIFOAV_1WORD 1 | |
69 | #define MX3_PWMSR_FIFOAV_2WORDS 2 | |
70 | #define MX3_PWMSR_FIFOAV_3WORDS 3 | |
71 | #define MX3_PWMSR_FIFOAV_4WORDS 4 | |
72 | ||
73 | #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1) | |
74 | #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \ | |
75 | (x)) + 1) | |
137fd45f LY |
76 | |
77 | #define MX3_PWM_SWR_LOOP 5 | |
c010dba8 | 78 | |
bf9b0b1b MV |
79 | /* PWMPR register value of 0xffff has the same effect as 0xfffe */ |
80 | #define MX3_PWMPR_MAX 0xfffe | |
81 | ||
d80f8206 | 82 | struct pwm_imx27_chip { |
9f4c8f96 | 83 | struct clk *clk_ipg; |
7b27c160 | 84 | struct clk *clk_per; |
166091b1 | 85 | void __iomem *mmio_base; |
29693248 | 86 | struct pwm_chip chip; |
a3597d6c TR |
87 | |
88 | /* | |
89 | * The driver cannot read the current duty cycle from the hardware if | |
90 | * the hardware is disabled. Cache the last programmed duty cycle | |
91 | * value to return in that case. | |
92 | */ | |
93 | unsigned int duty_cycle; | |
166091b1 SH |
94 | }; |
95 | ||
d80f8206 | 96 | #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip) |
29693248 | 97 | |
aad4e530 | 98 | static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx) |
9f4c8f96 | 99 | { |
9f4c8f96 AH |
100 | int ret; |
101 | ||
102 | ret = clk_prepare_enable(imx->clk_ipg); | |
103 | if (ret) | |
104 | return ret; | |
105 | ||
106 | ret = clk_prepare_enable(imx->clk_per); | |
107 | if (ret) { | |
108 | clk_disable_unprepare(imx->clk_ipg); | |
109 | return ret; | |
110 | } | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
aad4e530 | 115 | static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx) |
9f4c8f96 | 116 | { |
9f4c8f96 AH |
117 | clk_disable_unprepare(imx->clk_per); |
118 | clk_disable_unprepare(imx->clk_ipg); | |
119 | } | |
120 | ||
d80f8206 UKK |
121 | static void pwm_imx27_get_state(struct pwm_chip *chip, |
122 | struct pwm_device *pwm, struct pwm_state *state) | |
bf9b0b1b | 123 | { |
d80f8206 | 124 | struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); |
7ca17b20 | 125 | u32 period, prescaler, pwm_clk, val; |
bf9b0b1b | 126 | u64 tmp; |
7ca17b20 | 127 | int ret; |
bf9b0b1b | 128 | |
aad4e530 | 129 | ret = pwm_imx27_clk_prepare_enable(imx); |
9f4c8f96 AH |
130 | if (ret < 0) |
131 | return; | |
132 | ||
bf9b0b1b MV |
133 | val = readl(imx->mmio_base + MX3_PWMCR); |
134 | ||
519ef9b5 | 135 | if (val & MX3_PWMCR_EN) |
bf9b0b1b | 136 | state->enabled = true; |
519ef9b5 | 137 | else |
bf9b0b1b | 138 | state->enabled = false; |
bf9b0b1b MV |
139 | |
140 | switch (FIELD_GET(MX3_PWMCR_POUTC, val)) { | |
141 | case MX3_PWMCR_POUTC_NORMAL: | |
142 | state->polarity = PWM_POLARITY_NORMAL; | |
143 | break; | |
144 | case MX3_PWMCR_POUTC_INVERTED: | |
145 | state->polarity = PWM_POLARITY_INVERSED; | |
146 | break; | |
147 | default: | |
148 | dev_warn(chip->dev, "can't set polarity, output disconnected"); | |
149 | } | |
150 | ||
151 | prescaler = MX3_PWMCR_PRESCALER_GET(val); | |
152 | pwm_clk = clk_get_rate(imx->clk_per); | |
bf9b0b1b MV |
153 | val = readl(imx->mmio_base + MX3_PWMPR); |
154 | period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val; | |
155 | ||
156 | /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */ | |
aef1a379 UKK |
157 | tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler; |
158 | state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk); | |
bf9b0b1b | 159 | |
a3597d6c TR |
160 | /* |
161 | * PWMSAR can be read only if PWM is enabled. If the PWM is disabled, | |
162 | * use the cached value. | |
163 | */ | |
164 | if (state->enabled) | |
bf9b0b1b | 165 | val = readl(imx->mmio_base + MX3_PWMSAR); |
a3597d6c TR |
166 | else |
167 | val = imx->duty_cycle; | |
168 | ||
aef1a379 UKK |
169 | tmp = NSEC_PER_SEC * (u64)(val) * prescaler; |
170 | state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk); | |
9f4c8f96 | 171 | |
2cb5cd90 | 172 | pwm_imx27_clk_disable_unprepare(imx); |
66ad6a61 SH |
173 | } |
174 | ||
d80f8206 | 175 | static void pwm_imx27_sw_reset(struct pwm_chip *chip) |
19e73333 | 176 | { |
d80f8206 | 177 | struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); |
970247a4 LM |
178 | struct device *dev = chip->dev; |
179 | int wait_count = 0; | |
180 | u32 cr; | |
181 | ||
182 | writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); | |
183 | do { | |
184 | usleep_range(200, 1000); | |
185 | cr = readl(imx->mmio_base + MX3_PWMCR); | |
186 | } while ((cr & MX3_PWMCR_SWR) && | |
187 | (wait_count++ < MX3_PWM_SWR_LOOP)); | |
188 | ||
189 | if (cr & MX3_PWMCR_SWR) | |
190 | dev_warn(dev, "software reset timeout\n"); | |
191 | } | |
19e73333 | 192 | |
d80f8206 UKK |
193 | static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip, |
194 | struct pwm_device *pwm) | |
73b1ff1f | 195 | { |
d80f8206 | 196 | struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); |
73b1ff1f LM |
197 | struct device *dev = chip->dev; |
198 | unsigned int period_ms; | |
199 | int fifoav; | |
200 | u32 sr; | |
7b27c160 | 201 | |
73b1ff1f | 202 | sr = readl(imx->mmio_base + MX3_PWMSR); |
9f617ada | 203 | fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr); |
73b1ff1f | 204 | if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) { |
1689dcd4 | 205 | period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm), |
73b1ff1f LM |
206 | NSEC_PER_MSEC); |
207 | msleep(period_ms); | |
7b27c160 | 208 | |
73b1ff1f | 209 | sr = readl(imx->mmio_base + MX3_PWMSR); |
9f617ada | 210 | if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr)) |
73b1ff1f LM |
211 | dev_warn(dev, "there is no free FIFO slot\n"); |
212 | } | |
19e73333 SH |
213 | } |
214 | ||
d80f8206 | 215 | static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
71523d18 | 216 | const struct pwm_state *state) |
166091b1 | 217 | { |
0ca1a11a | 218 | unsigned long period_cycles, duty_cycles, prescale; |
d80f8206 | 219 | struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); |
0ca1a11a LM |
220 | struct pwm_state cstate; |
221 | unsigned long long c; | |
aef1a379 | 222 | unsigned long long clkrate; |
140827c1 | 223 | int ret; |
326ed314 | 224 | u32 cr; |
0ca1a11a LM |
225 | |
226 | pwm_get_state(pwm, &cstate); | |
227 | ||
aef1a379 UKK |
228 | clkrate = clk_get_rate(imx->clk_per); |
229 | c = clkrate * state->period; | |
166091b1 | 230 | |
aef1a379 | 231 | do_div(c, NSEC_PER_SEC); |
bd88d319 TR |
232 | period_cycles = c; |
233 | ||
234 | prescale = period_cycles / 0x10000 + 1; | |
235 | ||
236 | period_cycles /= prescale; | |
aef1a379 | 237 | c = clkrate * state->duty_cycle; |
1ce65396 | 238 | do_div(c, NSEC_PER_SEC); |
bd88d319 | 239 | duty_cycles = c; |
1ce65396 | 240 | duty_cycles /= prescale; |
bd88d319 TR |
241 | |
242 | /* | |
243 | * according to imx pwm RM, the real period value should be PERIOD | |
244 | * value in PWMPR plus 2. | |
245 | */ | |
246 | if (period_cycles > 2) | |
247 | period_cycles -= 2; | |
248 | else | |
249 | period_cycles = 0; | |
250 | ||
251 | /* | |
252 | * Wait for a free FIFO slot if the PWM is already enabled, and flush | |
253 | * the FIFO if the PWM was disabled and is about to be enabled. | |
254 | */ | |
255 | if (cstate.enabled) { | |
256 | pwm_imx27_wait_fifo_slot(chip, pwm); | |
257 | } else { | |
aad4e530 | 258 | ret = pwm_imx27_clk_prepare_enable(imx); |
bd88d319 TR |
259 | if (ret) |
260 | return ret; | |
261 | ||
262 | pwm_imx27_sw_reset(chip); | |
0ca1a11a | 263 | } |
166091b1 | 264 | |
bd88d319 TR |
265 | writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); |
266 | writel(period_cycles, imx->mmio_base + MX3_PWMPR); | |
267 | ||
268 | /* | |
269 | * Store the duty cycle for future reference in cases where the | |
270 | * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled). | |
271 | */ | |
272 | imx->duty_cycle = duty_cycles; | |
273 | ||
274 | cr = MX3_PWMCR_PRESCALER_SET(prescale) | | |
275 | MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | | |
276 | FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) | | |
277 | MX3_PWMCR_DBGEN; | |
278 | ||
279 | if (state->polarity == PWM_POLARITY_INVERSED) | |
280 | cr |= FIELD_PREP(MX3_PWMCR_POUTC, | |
281 | MX3_PWMCR_POUTC_INVERTED); | |
282 | ||
283 | if (state->enabled) | |
284 | cr |= MX3_PWMCR_EN; | |
285 | ||
286 | writel(cr, imx->mmio_base + MX3_PWMCR); | |
287 | ||
15d4dbd6 | 288 | if (!state->enabled) |
aad4e530 | 289 | pwm_imx27_clk_disable_unprepare(imx); |
bd88d319 | 290 | |
0ca1a11a | 291 | return 0; |
166091b1 | 292 | } |
166091b1 | 293 | |
d80f8206 UKK |
294 | static const struct pwm_ops pwm_imx27_ops = { |
295 | .apply = pwm_imx27_apply, | |
296 | .get_state = pwm_imx27_get_state, | |
29693248 SH |
297 | .owner = THIS_MODULE, |
298 | }; | |
166091b1 | 299 | |
d80f8206 UKK |
300 | static const struct of_device_id pwm_imx27_dt_ids[] = { |
301 | { .compatible = "fsl,imx27-pwm", }, | |
479e2e30 PZ |
302 | { /* sentinel */ } |
303 | }; | |
d80f8206 | 304 | MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids); |
479e2e30 | 305 | |
d80f8206 | 306 | static int pwm_imx27_probe(struct platform_device *pdev) |
166091b1 | 307 | { |
d80f8206 | 308 | struct pwm_imx27_chip *imx; |
2cb5cd90 UKK |
309 | int ret; |
310 | u32 pwmcr; | |
166091b1 | 311 | |
a9970e3b | 312 | imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL); |
1cbec749 | 313 | if (imx == NULL) |
166091b1 | 314 | return -ENOMEM; |
166091b1 | 315 | |
f20b187e UKK |
316 | platform_set_drvdata(pdev, imx); |
317 | ||
9f4c8f96 | 318 | imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
d109d74c AH |
319 | if (IS_ERR(imx->clk_ipg)) |
320 | return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg), | |
321 | "getting ipg clock failed\n"); | |
9f4c8f96 | 322 | |
7b27c160 | 323 | imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
d109d74c AH |
324 | if (IS_ERR(imx->clk_per)) |
325 | return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per), | |
326 | "failed to get peripheral clock\n"); | |
166091b1 | 327 | |
d80f8206 | 328 | imx->chip.ops = &pwm_imx27_ops; |
29693248 | 329 | imx->chip.dev = &pdev->dev; |
29693248 | 330 | imx->chip.npwm = 1; |
166091b1 | 331 | |
d80f8206 UKK |
332 | imx->chip.of_xlate = of_pwm_xlate_with_flags; |
333 | imx->chip.of_pwm_n_cells = 3; | |
326ed314 | 334 | |
1347c94f | 335 | imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); |
6d4294d1 TR |
336 | if (IS_ERR(imx->mmio_base)) |
337 | return PTR_ERR(imx->mmio_base); | |
166091b1 | 338 | |
2cb5cd90 UKK |
339 | ret = pwm_imx27_clk_prepare_enable(imx); |
340 | if (ret) | |
341 | return ret; | |
342 | ||
343 | /* keep clks on if pwm is running */ | |
344 | pwmcr = readl(imx->mmio_base + MX3_PWMCR); | |
345 | if (!(pwmcr & MX3_PWMCR_EN)) | |
346 | pwm_imx27_clk_disable_unprepare(imx); | |
347 | ||
f20b187e | 348 | return pwmchip_add(&imx->chip); |
166091b1 SH |
349 | } |
350 | ||
d80f8206 | 351 | static int pwm_imx27_remove(struct platform_device *pdev) |
166091b1 | 352 | { |
d80f8206 | 353 | struct pwm_imx27_chip *imx; |
166091b1 | 354 | |
29693248 | 355 | imx = platform_get_drvdata(pdev); |
166091b1 | 356 | |
a9970e3b | 357 | return pwmchip_remove(&imx->chip); |
166091b1 SH |
358 | } |
359 | ||
29693248 | 360 | static struct platform_driver imx_pwm_driver = { |
d80f8206 UKK |
361 | .driver = { |
362 | .name = "pwm-imx27", | |
363 | .of_match_table = pwm_imx27_dt_ids, | |
166091b1 | 364 | }, |
d80f8206 UKK |
365 | .probe = pwm_imx27_probe, |
366 | .remove = pwm_imx27_remove, | |
166091b1 | 367 | }; |
208d038f | 368 | module_platform_driver(imx_pwm_driver); |
166091b1 SH |
369 | |
370 | MODULE_LICENSE("GPL v2"); | |
371 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |