[linux-2.6-block.git] / drivers / pwm / pwm-imx.c

/*
 * simple driver for PWM (Pulse Width Modulator) controller
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/pwm.h>
#include <linux/of.h>
#include <linux/of_device.h>

/* i.MX1 and i.MX21 share the same PWM function block: */

#define MX1_PWMC			0x00   /* PWM Control Register */
#define MX1_PWMS			0x04   /* PWM Sample Register */
#define MX1_PWMP			0x08   /* PWM Period Register */

#define MX1_PWMC_EN			(1 << 4)

/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */

#define MX3_PWMCR			0x00    /* PWM Control Register */
#define MX3_PWMSR			0x04    /* PWM Status Register */
#define MX3_PWMSAR			0x0C    /* PWM Sample Register */
#define MX3_PWMPR			0x10    /* PWM Period Register */
#define MX3_PWMCR_PRESCALER(x)		((((x) - 1) & 0xFFF) << 4)
#define MX3_PWMCR_STOPEN		(1 << 25)
#define MX3_PWMCR_DOZEEN		(1 << 24)
#define MX3_PWMCR_WAITEN		(1 << 23)
#define MX3_PWMCR_DBGEN			(1 << 22)
#define MX3_PWMCR_POUTC			(1 << 18)
#define MX3_PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
#define MX3_PWMCR_CLKSRC_IPG		(1 << 16)
#define MX3_PWMCR_SWR			(1 << 3)
#define MX3_PWMCR_EN			(1 << 0)
#define MX3_PWMSR_FIFOAV_4WORDS		0x4
#define MX3_PWMSR_FIFOAV_MASK		0x7

#define MX3_PWM_SWR_LOOP		5

struct imx_chip {
	struct clk	*clk_per;

	void __iomem	*mmio_base;

	struct pwm_chip	chip;
};

#define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)

static int imx_pwm_config_v1(struct pwm_chip *chip,
		struct pwm_device *pwm, int duty_ns, int period_ns)
{
	struct imx_chip *imx = to_imx_chip(chip);

	/*
	 * The PWM subsystem allows for exact frequencies. However,
	 * I cannot connect a scope on my device to the PWM line and
	 * thus cannot provide the program the PWM controller
	 * exactly. Instead, I'm relying on the fact that the
	 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
	 * function group already. So I'll just modify the PWM sample
	 * register to follow the ratio of duty_ns vs. period_ns
	 * accordingly.
	 *
	 * This is good enough for programming the brightness of
	 * the LCD backlight.
	 *
	 * The real implementation would divide PERCLK[0] first by
	 * both the prescaler (/1 .. /128) and then by CLKSEL
	 * (/2 .. /16).
	 */
	u32 max = readl(imx->mmio_base + MX1_PWMP);
	u32 p = max * duty_ns / period_ns;
	writel(max - p, imx->mmio_base + MX1_PWMS);

	return 0;
}

static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	u32 val;
	int ret;

	ret = clk_prepare_enable(imx->clk_per);
	if (ret < 0)
		return ret;

	val = readl(imx->mmio_base + MX1_PWMC);
	val |= MX1_PWMC_EN;
	writel(val, imx->mmio_base + MX1_PWMC);

	return 0;
}

static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	u32 val;

	val = readl(imx->mmio_base + MX1_PWMC);
	val &= ~MX1_PWMC_EN;
	writel(val, imx->mmio_base + MX1_PWMC);

	clk_disable_unprepare(imx->clk_per);
}

static void imx_pwm_sw_reset(struct pwm_chip *chip)
{
	struct imx_chip *imx = to_imx_chip(chip);
	struct device *dev = chip->dev;
	int wait_count = 0;
	u32 cr;

	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
	do {
		usleep_range(200, 1000);
		cr = readl(imx->mmio_base + MX3_PWMCR);
	} while ((cr & MX3_PWMCR_SWR) &&
		 (wait_count++ < MX3_PWM_SWR_LOOP));

	if (cr & MX3_PWMCR_SWR)
		dev_warn(dev, "software reset timeout\n");
}

static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
				   struct pwm_device *pwm)
{
	struct imx_chip *imx = to_imx_chip(chip);
	struct device *dev = chip->dev;
	unsigned int period_ms;
	int fifoav;
	u32 sr;

	sr = readl(imx->mmio_base + MX3_PWMSR);
	fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
		period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
					 NSEC_PER_MSEC);
		msleep(period_ms);

		sr = readl(imx->mmio_base + MX3_PWMSR);
		if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
			dev_warn(dev, "there is no free FIFO slot\n");
	}
}

static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
			    struct pwm_state *state)
{
	unsigned long period_cycles, duty_cycles, prescale;
	struct imx_chip *imx = to_imx_chip(chip);
	struct pwm_state cstate;
	unsigned long long c;
	int ret;
	u32 cr;

	pwm_get_state(pwm, &cstate);

	if (state->enabled) {
		c = clk_get_rate(imx->clk_per);
		c *= state->period;

		do_div(c, 1000000000);
		period_cycles = c;

		prescale = period_cycles / 0x10000 + 1;

		period_cycles /= prescale;
		c = (unsigned long long)period_cycles * state->duty_cycle;
		do_div(c, state->period);
		duty_cycles = c;

		/*
		 * according to imx pwm RM, the real period value should be
		 * PERIOD value in PWMPR plus 2.
		 */
		if (period_cycles > 2)
			period_cycles -= 2;
		else
			period_cycles = 0;

		/*
		 * Wait for a free FIFO slot if the PWM is already enabled, and
		 * flush the FIFO if the PWM was disabled and is about to be
		 * enabled.
		 */
		if (cstate.enabled) {
			imx_pwm_wait_fifo_slot(chip, pwm);
		} else {
			ret = clk_prepare_enable(imx->clk_per);
			if (ret)
				return ret;

			imx_pwm_sw_reset(chip);
		}

		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
		writel(period_cycles, imx->mmio_base + MX3_PWMPR);

		cr = MX3_PWMCR_PRESCALER(prescale) |
		     MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
		     MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
		     MX3_PWMCR_EN;

		if (state->polarity == PWM_POLARITY_INVERSED)
			cr |= MX3_PWMCR_POUTC;

		writel(cr, imx->mmio_base + MX3_PWMCR);
	} else if (cstate.enabled) {
		writel(0, imx->mmio_base + MX3_PWMCR);

		clk_disable_unprepare(imx->clk_per);
	}

	return 0;
}

static const struct pwm_ops imx_pwm_ops_v1 = {
	.enable = imx_pwm_enable_v1,
	.disable = imx_pwm_disable_v1,
	.config = imx_pwm_config_v1,
	.owner = THIS_MODULE,
};

static const struct pwm_ops imx_pwm_ops_v2 = {
	.apply = imx_pwm_apply_v2,
	.owner = THIS_MODULE,
};

struct imx_pwm_data {
	bool polarity_supported;
	const struct pwm_ops *ops;
};

static struct imx_pwm_data imx_pwm_data_v1 = {
	.ops = &imx_pwm_ops_v1,
};

static struct imx_pwm_data imx_pwm_data_v2 = {
	.polarity_supported = true,
	.ops = &imx_pwm_ops_v2,
};

static const struct of_device_id imx_pwm_dt_ids[] = {
	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);

static int imx_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(imx_pwm_dt_ids, &pdev->dev);
	const struct imx_pwm_data *data;
	struct imx_chip *imx;
	struct resource *r;
	int ret = 0;

	if (!of_id)
		return -ENODEV;

	data = of_id->data;

	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
	if (imx == NULL)
		return -ENOMEM;

	imx->clk_per = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(imx->clk_per)) {
		dev_err(&pdev->dev, "getting per clock failed with %ld\n",
				PTR_ERR(imx->clk_per));
		return PTR_ERR(imx->clk_per);
	}

	imx->chip.ops = data->ops;
	imx->chip.dev = &pdev->dev;
	imx->chip.base = -1;
	imx->chip.npwm = 1;

	if (data->polarity_supported) {
		dev_dbg(&pdev->dev, "PWM supports output inversion\n");
		imx->chip.of_xlate = of_pwm_xlate_with_flags;
		imx->chip.of_pwm_n_cells = 3;
	}

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(imx->mmio_base))
		return PTR_ERR(imx->mmio_base);

	ret = pwmchip_add(&imx->chip);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, imx);
	return 0;
}

static int imx_pwm_remove(struct platform_device *pdev)
{
	struct imx_chip *imx;

	imx = platform_get_drvdata(pdev);
	if (imx == NULL)
		return -ENODEV;

	return pwmchip_remove(&imx->chip);
}

static struct platform_driver imx_pwm_driver = {
	.driver		= {
		.name	= "imx-pwm",
		.of_match_table = imx_pwm_dt_ids,
	},
	.probe		= imx_pwm_probe,
	.remove		= imx_pwm_remove,
};

module_platform_driver(imx_pwm_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Commit	Line	Data
166091b1 SH	1	/*
	2	* simple driver for PWM (Pulse Width Modulator) controller
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/platform_device.h>
5a0e3ad6	14	#include <linux/slab.h>
166091b1 SH	15	#include <linux/err.h>
166091b1 SH	16	#include <linux/clk.h>
137fd45f	17	#include <linux/delay.h>
166091b1 SH	18	#include <linux/io.h>
166091b1 SH	19	#include <linux/pwm.h>
2a8876cf	20	#include <linux/of.h>
479e2e30	21	#include <linux/of_device.h>
c010dba8	22
c010dba8 HS	23	/* i.MX1 and i.MX21 share the same PWM function block: */
c010dba8 HS	24
40f260c2 LY	25	#define MX1_PWMC 0x00 /* PWM Control Register */
	26	#define MX1_PWMS 0x04 /* PWM Sample Register */
	27	#define MX1_PWMP 0x08 /* PWM Period Register */
c010dba8	28
40f260c2	29	#define MX1_PWMC_EN (1 << 4)
c010dba8 HS	30
	31	/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
	32
40f260c2	33	#define MX3_PWMCR 0x00 /* PWM Control Register */
137fd45f	34	#define MX3_PWMSR 0x04 /* PWM Status Register */
40f260c2 LY	35	#define MX3_PWMSAR 0x0C /* PWM Sample Register */
	36	#define MX3_PWMPR 0x10 /* PWM Period Register */
	37	#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
1f6eefeb	38	#define MX3_PWMCR_STOPEN (1 << 25)
40f260c2 LY	39	#define MX3_PWMCR_DOZEEN (1 << 24)
40f260c2 LY	40	#define MX3_PWMCR_WAITEN (1 << 23)
c0d96aed	41	#define MX3_PWMCR_DBGEN (1 << 22)
326ed314	42	#define MX3_PWMCR_POUTC (1 << 18)
40f260c2 LY	43	#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
40f260c2 LY	44	#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
137fd45f	45	#define MX3_PWMCR_SWR (1 << 3)
40f260c2	46	#define MX3_PWMCR_EN (1 << 0)
137fd45f LY	47	#define MX3_PWMSR_FIFOAV_4WORDS 0x4
	48	#define MX3_PWMSR_FIFOAV_MASK 0x7
	49
	50	#define MX3_PWM_SWR_LOOP 5
c010dba8	51
29693248	52	struct imx_chip {
7b27c160	53	struct clk *clk_per;
166091b1	54
166091b1 SH	55	void __iomem *mmio_base;
166091b1 SH	56
29693248	57	struct pwm_chip chip;
166091b1 SH	58	};
166091b1 SH	59
29693248 SH	60	#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
29693248 SH	61
19e73333	62	static int imx_pwm_config_v1(struct pwm_chip *chip,
29693248	63	struct pwm_device *pwm, int duty_ns, int period_ns)
166091b1	64	{
29693248	65	struct imx_chip *imx = to_imx_chip(chip);
166091b1	66
19e73333 SH	67	/*
	68	* The PWM subsystem allows for exact frequencies. However,
	69	* I cannot connect a scope on my device to the PWM line and
	70	* thus cannot provide the program the PWM controller
	71	* exactly. Instead, I'm relying on the fact that the
	72	* Bootloader (u-boot or WinCE+haret) has programmed the PWM
	73	* function group already. So I'll just modify the PWM sample
	74	* register to follow the ratio of duty_ns vs. period_ns
	75	* accordingly.
	76	*
	77	* This is good enough for programming the brightness of
	78	* the LCD backlight.
	79	*
	80	* The real implementation would divide PERCLK[0] first by
	81	* both the prescaler (/1 .. /128) and then by CLKSEL
	82	* (/2 .. /16).
	83	*/
	84	u32 max = readl(imx->mmio_base + MX1_PWMP);
	85	u32 p = max * duty_ns / period_ns;
	86	writel(max - p, imx->mmio_base + MX1_PWMS);
	87
	88	return 0;
	89	}
	90
b3c088fe	91	static int imx_pwm_enable_v1(struct pwm_chip chip, struct pwm_device pwm)
66ad6a61 SH	92	{
	93	struct imx_chip *imx = to_imx_chip(chip);
	94	u32 val;
b3c088fe	95	int ret;
66ad6a61	96
b3c088fe LM	97	ret = clk_prepare_enable(imx->clk_per);
	98	if (ret < 0)
	99	return ret;
66ad6a61	100
66ad6a61	101	val = readl(imx->mmio_base + MX1_PWMC);
b3c088fe	102	val \|= MX1_PWMC_EN;
66ad6a61	103	writel(val, imx->mmio_base + MX1_PWMC);
166091b1 SH	104
	105	return 0;
	106	}
166091b1	107
b3c088fe	108	static void imx_pwm_disable_v1(struct pwm_chip chip, struct pwm_device pwm)
66ad6a61 SH	109	{
	110	struct imx_chip *imx = to_imx_chip(chip);
	111	u32 val;
	112
b3c088fe LM	113	val = readl(imx->mmio_base + MX1_PWMC);
b3c088fe LM	114	val &= ~MX1_PWMC_EN;
66ad6a61	115	writel(val, imx->mmio_base + MX1_PWMC);
66ad6a61	116
b3c088fe	117	clk_disable_unprepare(imx->clk_per);
66ad6a61 SH	118	}
66ad6a61 SH	119
970247a4	120	static void imx_pwm_sw_reset(struct pwm_chip *chip)
19e73333 SH	121	{
19e73333 SH	122	struct imx_chip *imx = to_imx_chip(chip);
970247a4 LM	123	struct device *dev = chip->dev;
	124	int wait_count = 0;
	125	u32 cr;
	126
	127	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
	128	do {
	129	usleep_range(200, 1000);
	130	cr = readl(imx->mmio_base + MX3_PWMCR);
	131	} while ((cr & MX3_PWMCR_SWR) &&
	132	(wait_count++ < MX3_PWM_SWR_LOOP));
	133
	134	if (cr & MX3_PWMCR_SWR)
	135	dev_warn(dev, "software reset timeout\n");
	136	}
19e73333	137
73b1ff1f LM	138	static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
	139	struct pwm_device *pwm)
	140	{
	141	struct imx_chip *imx = to_imx_chip(chip);
	142	struct device *dev = chip->dev;
	143	unsigned int period_ms;
	144	int fifoav;
	145	u32 sr;
7b27c160	146
73b1ff1f LM	147	sr = readl(imx->mmio_base + MX3_PWMSR);
	148	fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
	149	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
	150	period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
	151	NSEC_PER_MSEC);
	152	msleep(period_ms);
7b27c160	153
73b1ff1f LM	154	sr = readl(imx->mmio_base + MX3_PWMSR);
	155	if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
	156	dev_warn(dev, "there is no free FIFO slot\n");
	157	}
19e73333 SH	158	}
19e73333 SH	159
0ca1a11a LM	160	static int imx_pwm_apply_v2(struct pwm_chip chip, struct pwm_device pwm,
0ca1a11a LM	161	struct pwm_state *state)
166091b1	162	{
0ca1a11a	163	unsigned long period_cycles, duty_cycles, prescale;
29693248	164	struct imx_chip *imx = to_imx_chip(chip);
0ca1a11a LM	165	struct pwm_state cstate;
0ca1a11a LM	166	unsigned long long c;
140827c1	167	int ret;
326ed314	168	u32 cr;
0ca1a11a LM	169
	170	pwm_get_state(pwm, &cstate);
	171
	172	if (state->enabled) {
	173	c = clk_get_rate(imx->clk_per);
	174	c *= state->period;
	175
	176	do_div(c, 1000000000);
	177	period_cycles = c;
	178
	179	prescale = period_cycles / 0x10000 + 1;
	180
	181	period_cycles /= prescale;
	182	c = (unsigned long long)period_cycles * state->duty_cycle;
	183	do_div(c, state->period);
	184	duty_cycles = c;
	185
	186	/*
	187	* according to imx pwm RM, the real period value should be
	188	* PERIOD value in PWMPR plus 2.
	189	*/
	190	if (period_cycles > 2)
	191	period_cycles -= 2;
	192	else
	193	period_cycles = 0;
	194
	195	/*
	196	* Wait for a free FIFO slot if the PWM is already enabled, and
	197	* flush the FIFO if the PWM was disabled and is about to be
	198	* enabled.
	199	*/
	200	if (cstate.enabled) {
	201	imx_pwm_wait_fifo_slot(chip, pwm);
	202	} else {
	203	ret = clk_prepare_enable(imx->clk_per);
	204	if (ret)
	205	return ret;
	206
	207	imx_pwm_sw_reset(chip);
	208	}
166091b1	209
0ca1a11a LM	210	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
0ca1a11a LM	211	writel(period_cycles, imx->mmio_base + MX3_PWMPR);
140827c1	212
326ed314	213	cr = MX3_PWMCR_PRESCALER(prescale) \|
1f6eefeb	214	MX3_PWMCR_STOPEN \| MX3_PWMCR_DOZEEN \| MX3_PWMCR_WAITEN \|
326ed314 LM	215	MX3_PWMCR_DBGEN \| MX3_PWMCR_CLKSRC_IPG_HIGH \|
326ed314 LM	216	MX3_PWMCR_EN;
66ad6a61	217
326ed314 LM	218	if (state->polarity == PWM_POLARITY_INVERSED)
326ed314 LM	219	cr \|= MX3_PWMCR_POUTC;
166091b1	220
326ed314	221	writel(cr, imx->mmio_base + MX3_PWMCR);
0ca1a11a LM	222	} else if (cstate.enabled) {
0ca1a11a LM	223	writel(0, imx->mmio_base + MX3_PWMCR);
166091b1	224
0ca1a11a LM	225	clk_disable_unprepare(imx->clk_per);
0ca1a11a LM	226	}
166091b1	227
0ca1a11a	228	return 0;
166091b1	229	}
166091b1	230
00389229	231	static const struct pwm_ops imx_pwm_ops_v1 = {
b3c088fe LM	232	.enable = imx_pwm_enable_v1,
	233	.disable = imx_pwm_disable_v1,
	234	.config = imx_pwm_config_v1,
00389229 LM	235	.owner = THIS_MODULE,
	236	};
	237
	238	static const struct pwm_ops imx_pwm_ops_v2 = {
0ca1a11a	239	.apply = imx_pwm_apply_v2,
29693248 SH	240	.owner = THIS_MODULE,
29693248 SH	241	};
166091b1	242
479e2e30	243	struct imx_pwm_data {
326ed314	244	bool polarity_supported;
00389229	245	const struct pwm_ops *ops;
479e2e30 PZ	246	};
	247
	248	static struct imx_pwm_data imx_pwm_data_v1 = {
00389229	249	.ops = &imx_pwm_ops_v1,
479e2e30 PZ	250	};
	251
	252	static struct imx_pwm_data imx_pwm_data_v2 = {
326ed314	253	.polarity_supported = true,
00389229	254	.ops = &imx_pwm_ops_v2,
479e2e30 PZ	255	};
	256
	257	static const struct of_device_id imx_pwm_dt_ids[] = {
	258	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
	259	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
	260	{ /* sentinel */ }
	261	};
	262	MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
	263
3e9fe83d	264	static int imx_pwm_probe(struct platform_device *pdev)
166091b1	265	{
479e2e30 PZ	266	const struct of_device_id *of_id =
479e2e30 PZ	267	of_match_device(imx_pwm_dt_ids, &pdev->dev);
983290b0	268	const struct imx_pwm_data *data;
29693248	269	struct imx_chip *imx;
166091b1 SH	270	struct resource *r;
	271	int ret = 0;
	272
479e2e30 PZ	273	if (!of_id)
	274	return -ENODEV;
	275
00389229 LM	276	data = of_id->data;
00389229 LM	277
a9970e3b	278	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
1cbec749	279	if (imx == NULL)
166091b1	280	return -ENOMEM;
166091b1	281
7b27c160 PZ	282	imx->clk_per = devm_clk_get(&pdev->dev, "per");
	283	if (IS_ERR(imx->clk_per)) {
	284	dev_err(&pdev->dev, "getting per clock failed with %ld\n",
	285	PTR_ERR(imx->clk_per));
	286	return PTR_ERR(imx->clk_per);
	287	}
166091b1	288
00389229	289	imx->chip.ops = data->ops;
29693248 SH	290	imx->chip.dev = &pdev->dev;
	291	imx->chip.base = -1;
	292	imx->chip.npwm = 1;
166091b1	293
326ed314 LM	294	if (data->polarity_supported) {
	295	dev_dbg(&pdev->dev, "PWM supports output inversion\n");
	296	imx->chip.of_xlate = of_pwm_xlate_with_flags;
	297	imx->chip.of_pwm_n_cells = 3;
	298	}
	299
166091b1	300	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6d4294d1 TR	301	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
	302	if (IS_ERR(imx->mmio_base))
	303	return PTR_ERR(imx->mmio_base);
166091b1	304
29693248 SH	305	ret = pwmchip_add(&imx->chip);
29693248 SH	306	if (ret < 0)
a9970e3b	307	return ret;
166091b1	308
29693248	309	platform_set_drvdata(pdev, imx);
166091b1	310	return 0;
166091b1 SH	311	}
166091b1 SH	312
77f37917	313	static int imx_pwm_remove(struct platform_device *pdev)
166091b1	314	{
29693248	315	struct imx_chip *imx;
166091b1	316
29693248 SH	317	imx = platform_get_drvdata(pdev);
29693248 SH	318	if (imx == NULL)
166091b1 SH	319	return -ENODEV;
166091b1 SH	320
a9970e3b	321	return pwmchip_remove(&imx->chip);
166091b1 SH	322	}
166091b1 SH	323
29693248	324	static struct platform_driver imx_pwm_driver = {
166091b1	325	.driver = {
479e2e30	326	.name = "imx-pwm",
becbca13	327	.of_match_table = imx_pwm_dt_ids,
166091b1	328	},
29693248	329	.probe = imx_pwm_probe,
fd109112	330	.remove = imx_pwm_remove,
166091b1 SH	331	};
166091b1 SH	332
208d038f	333	module_platform_driver(imx_pwm_driver);
166091b1 SH	334
	335	MODULE_LICENSE("GPL v2");
	336	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");