[linux-2.6-block.git] / drivers / pwm / pwm-img.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Imagination Technologies Pulse Width Modulator driver
 *
 * Copyright (c) 2014-2015, Imagination Technologies
 *
 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>

/* PWM registers */
#define PWM_CTRL_CFG				0x0000
#define PWM_CTRL_CFG_NO_SUB_DIV			0
#define PWM_CTRL_CFG_SUB_DIV0			1
#define PWM_CTRL_CFG_SUB_DIV1			2
#define PWM_CTRL_CFG_SUB_DIV0_DIV1		3
#define PWM_CTRL_CFG_DIV_SHIFT(ch)		((ch) * 2 + 4)
#define PWM_CTRL_CFG_DIV_MASK			0x3

#define PWM_CH_CFG(ch)				(0x4 + (ch) * 4)
#define PWM_CH_CFG_TMBASE_SHIFT			0
#define PWM_CH_CFG_DUTY_SHIFT			16

#define PERIP_PWM_PDM_CONTROL			0x0140
#define PERIP_PWM_PDM_CONTROL_CH_MASK		0x1
#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch)	((ch) * 4)

#define IMG_PWM_PM_TIMEOUT			1000 /* ms */

/*
 * PWM period is specified with a timebase register,
 * in number of step periods. The PWM duty cycle is also
 * specified in step periods, in the [0, $timebase] range.
 * In other words, the timebase imposes the duty cycle
 * resolution. Therefore, let's constraint the timebase to
 * a minimum value to allow a sane range of duty cycle values.
 * Imposing a minimum timebase, will impose a maximum PWM frequency.
 *
 * The value chosen is completely arbitrary.
 */
#define MIN_TMBASE_STEPS			16

#define IMG_PWM_NPWM				4

struct img_pwm_soc_data {
	u32 max_timebase;
};

struct img_pwm_chip {
	struct clk	*pwm_clk;
	struct clk	*sys_clk;
	void __iomem	*base;
	struct regmap	*periph_regs;
	int		max_period_ns;
	int		min_period_ns;
	const struct img_pwm_soc_data   *data;
	u32		suspend_ctrl_cfg;
	u32		suspend_ch_cfg[IMG_PWM_NPWM];
};

static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static inline void img_pwm_writel(struct img_pwm_chip *imgchip,
				  u32 reg, u32 val)
{
	writel(val, imgchip->base + reg);
}

static inline u32 img_pwm_readl(struct img_pwm_chip *imgchip, u32 reg)
{
	return readl(imgchip->base + reg);
}

static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	u32 val, div, duty, timebase;
	unsigned long mul, output_clk_hz, input_clk_hz;
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
	unsigned int max_timebase = imgchip->data->max_timebase;
	int ret;

	if (period_ns < imgchip->min_period_ns ||
	    period_ns > imgchip->max_period_ns) {
		dev_err(pwmchip_parent(chip), "configured period not in range\n");
		return -ERANGE;
	}

	input_clk_hz = clk_get_rate(imgchip->pwm_clk);
	output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);

	mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
	if (mul <= max_timebase) {
		div = PWM_CTRL_CFG_NO_SUB_DIV;
		timebase = DIV_ROUND_UP(mul, 1);
	} else if (mul <= max_timebase * 8) {
		div = PWM_CTRL_CFG_SUB_DIV0;
		timebase = DIV_ROUND_UP(mul, 8);
	} else if (mul <= max_timebase * 64) {
		div = PWM_CTRL_CFG_SUB_DIV1;
		timebase = DIV_ROUND_UP(mul, 64);
	} else if (mul <= max_timebase * 512) {
		div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
		timebase = DIV_ROUND_UP(mul, 512);
	} else {
		dev_err(pwmchip_parent(chip),
			"failed to configure timebase steps/divider value\n");
		return -EINVAL;
	}

	duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);

	ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
	if (ret < 0)
		return ret;

	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
	val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
		PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);

	val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
	      (timebase << PWM_CH_CFG_TMBASE_SHIFT);
	img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);

	pm_runtime_mark_last_busy(pwmchip_parent(chip));
	pm_runtime_put_autosuspend(pwmchip_parent(chip));

	return 0;
}

static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	u32 val;
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
	int ret;

	ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
	if (ret < 0)
		return ret;

	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
	val |= BIT(pwm->hwpwm);
	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);

	regmap_clear_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
			  PERIP_PWM_PDM_CONTROL_CH_MASK <<
			  PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm));

	return 0;
}

static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	u32 val;
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);

	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
	val &= ~BIT(pwm->hwpwm);
	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);

	pm_runtime_mark_last_busy(pwmchip_parent(chip));
	pm_runtime_put_autosuspend(pwmchip_parent(chip));
}

static int img_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *state)
{
	int err;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (pwm->state.enabled)
			img_pwm_disable(chip, pwm);

		return 0;
	}

	err = img_pwm_config(chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!pwm->state.enabled)
		err = img_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops img_pwm_ops = {
	.apply = img_pwm_apply,
};

static const struct img_pwm_soc_data pistachio_pwm = {
	.max_timebase = 255,
};

static const struct of_device_id img_pwm_of_match[] = {
	{
		.compatible = "img,pistachio-pwm",
		.data = &pistachio_pwm,
	},
	{ }
};
MODULE_DEVICE_TABLE(of, img_pwm_of_match);

static int img_pwm_runtime_suspend(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);

	clk_disable_unprepare(imgchip->pwm_clk);
	clk_disable_unprepare(imgchip->sys_clk);

	return 0;
}

static int img_pwm_runtime_resume(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
	int ret;

	ret = clk_prepare_enable(imgchip->sys_clk);
	if (ret < 0) {
		dev_err(dev, "could not prepare or enable sys clock\n");
		return ret;
	}

	ret = clk_prepare_enable(imgchip->pwm_clk);
	if (ret < 0) {
		dev_err(dev, "could not prepare or enable pwm clock\n");
		clk_disable_unprepare(imgchip->sys_clk);
		return ret;
	}

	return 0;
}

static int img_pwm_probe(struct platform_device *pdev)
{
	int ret;
	u64 val;
	unsigned long clk_rate;
	struct pwm_chip *chip;
	struct img_pwm_chip *imgchip;

	chip = devm_pwmchip_alloc(&pdev->dev, IMG_PWM_NPWM, sizeof(*imgchip));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	imgchip = to_img_pwm_chip(chip);

	imgchip->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(imgchip->base))
		return PTR_ERR(imgchip->base);

	imgchip->data = device_get_match_data(&pdev->dev);

	imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
							       "img,cr-periph");
	if (IS_ERR(imgchip->periph_regs))
		return PTR_ERR(imgchip->periph_regs);

	imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");
	if (IS_ERR(imgchip->sys_clk)) {
		dev_err(&pdev->dev, "failed to get system clock\n");
		return PTR_ERR(imgchip->sys_clk);
	}

	imgchip->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
	if (IS_ERR(imgchip->pwm_clk)) {
		dev_err(&pdev->dev, "failed to get pwm clock\n");
		return PTR_ERR(imgchip->pwm_clk);
	}

	platform_set_drvdata(pdev, chip);

	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = img_pwm_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	clk_rate = clk_get_rate(imgchip->pwm_clk);
	if (!clk_rate) {
		dev_err(&pdev->dev, "imgchip clock has no frequency\n");
		ret = -EINVAL;
		goto err_suspend;
	}

	/* The maximum input clock divider is 512 */
	val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;
	do_div(val, clk_rate);
	imgchip->max_period_ns = val;

	val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
	do_div(val, clk_rate);
	imgchip->min_period_ns = val;

	chip->ops = &img_pwm_ops;

	ret = pwmchip_add(chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
		goto err_suspend;
	}

	return 0;

err_suspend:
	if (!pm_runtime_enabled(&pdev->dev))
		img_pwm_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_dont_use_autosuspend(&pdev->dev);
	return ret;
}

static void img_pwm_remove(struct platform_device *pdev)
{
	struct pwm_chip *chip = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		img_pwm_runtime_suspend(&pdev->dev);

	pwmchip_remove(chip);
}

#ifdef CONFIG_PM_SLEEP
static int img_pwm_suspend(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
	int i, ret;

	if (pm_runtime_status_suspended(dev)) {
		ret = img_pwm_runtime_resume(dev);
		if (ret)
			return ret;
	}

	for (i = 0; i < chip->npwm; i++)
		imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,
							   PWM_CH_CFG(i));

	imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);

	img_pwm_runtime_suspend(dev);

	return 0;
}

static int img_pwm_resume(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
	int ret;
	int i;

	ret = img_pwm_runtime_resume(dev);
	if (ret)
		return ret;

	for (i = 0; i < chip->npwm; i++)
		img_pwm_writel(imgchip, PWM_CH_CFG(i),
			       imgchip->suspend_ch_cfg[i]);

	img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);

	for (i = 0; i < chip->npwm; i++)
		if (imgchip->suspend_ctrl_cfg & BIT(i))
			regmap_clear_bits(imgchip->periph_regs,
					  PERIP_PWM_PDM_CONTROL,
					  PERIP_PWM_PDM_CONTROL_CH_MASK <<
					  PERIP_PWM_PDM_CONTROL_CH_SHIFT(i));

	if (pm_runtime_status_suspended(dev))
		img_pwm_runtime_suspend(dev);

	return 0;
}
#endif /* CONFIG_PM */

static const struct dev_pm_ops img_pwm_pm_ops = {
	SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
			   img_pwm_runtime_resume,
			   NULL)
	SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
};

static struct platform_driver img_pwm_driver = {
	.driver = {
		.name = "img-pwm",
		.pm = &img_pwm_pm_ops,
		.of_match_table = img_pwm_of_match,
	},
	.probe = img_pwm_probe,
	.remove = img_pwm_remove,
};
module_platform_driver(img_pwm_driver);

MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
84a14ae8	1	// SPDX-License-Identifier: GPL-2.0-only
277bb6a2 NT	2	/*
	3	* Imagination Technologies Pulse Width Modulator driver
	4	*
	5	* Copyright (c) 2014-2015, Imagination Technologies
	6	*
	7	* Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
277bb6a2 NT	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/err.h>
	12	#include <linux/io.h>
	13	#include <linux/mfd/syscon.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/platform_device.h>
e690ae52	17	#include <linux/pm_runtime.h>
7ee22731	18	#include <linux/property.h>
277bb6a2 NT	19	#include <linux/pwm.h>
	20	#include <linux/regmap.h>
	21	#include <linux/slab.h>
	22
	23	/* PWM registers */
	24	#define PWM_CTRL_CFG 0x0000
	25	#define PWM_CTRL_CFG_NO_SUB_DIV 0
	26	#define PWM_CTRL_CFG_SUB_DIV0 1
	27	#define PWM_CTRL_CFG_SUB_DIV1 2
	28	#define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
	29	#define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
	30	#define PWM_CTRL_CFG_DIV_MASK 0x3
	31
	32	#define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
	33	#define PWM_CH_CFG_TMBASE_SHIFT 0
	34	#define PWM_CH_CFG_DUTY_SHIFT 16
	35
	36	#define PERIP_PWM_PDM_CONTROL 0x0140
	37	#define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
	38	#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
	39
e690ae52 EB	40	#define IMG_PWM_PM_TIMEOUT 1000 /* ms */
e690ae52 EB	41
1e70897d NT	42	/*
	43	* PWM period is specified with a timebase register,
	44	* in number of step periods. The PWM duty cycle is also
	45	* specified in step periods, in the [0, $timebase] range.
	46	* In other words, the timebase imposes the duty cycle
	47	* resolution. Therefore, let's constraint the timebase to
	48	* a minimum value to allow a sane range of duty cycle values.
	49	* Imposing a minimum timebase, will impose a maximum PWM frequency.
	50	*
	51	* The value chosen is completely arbitrary.
	52	*/
	53	#define MIN_TMBASE_STEPS 16
	54
a18afce5 EB	55	#define IMG_PWM_NPWM 4
a18afce5 EB	56
1e70897d NT	57	struct img_pwm_soc_data {
	58	u32 max_timebase;
	59	};
277bb6a2 NT	60
277bb6a2 NT	61	struct img_pwm_chip {
277bb6a2 NT	62	struct clk *pwm_clk;
	63	struct clk *sys_clk;
	64	void __iomem *base;
	65	struct regmap *periph_regs;
1e70897d NT	66	int max_period_ns;
	67	int min_period_ns;
	68	const struct img_pwm_soc_data *data;
a18afce5 EB	69	u32 suspend_ctrl_cfg;
a18afce5 EB	70	u32 suspend_ch_cfg[IMG_PWM_NPWM];
277bb6a2 NT	71	};
	72
	73	static inline struct img_pwm_chip to_img_pwm_chip(struct pwm_chip chip)
	74	{
12ca0c33	75	return pwmchip_get_drvdata(chip);
277bb6a2 NT	76	}
277bb6a2 NT	77
22e8e19a	78	static inline void img_pwm_writel(struct img_pwm_chip *imgchip,
277bb6a2 NT	79	u32 reg, u32 val)
277bb6a2 NT	80	{
22e8e19a	81	writel(val, imgchip->base + reg);
277bb6a2 NT	82	}
277bb6a2 NT	83
22e8e19a	84	static inline u32 img_pwm_readl(struct img_pwm_chip *imgchip, u32 reg)
277bb6a2	85	{
22e8e19a	86	return readl(imgchip->base + reg);
277bb6a2 NT	87	}
	88
	89	static int img_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	90	int duty_ns, int period_ns)
	91	{
	92	u32 val, div, duty, timebase;
	93	unsigned long mul, output_clk_hz, input_clk_hz;
22e8e19a UKK	94	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
22e8e19a UKK	95	unsigned int max_timebase = imgchip->data->max_timebase;
e690ae52	96	int ret;
1e70897d	97
22e8e19a UKK	98	if (period_ns < imgchip->min_period_ns \|\|
22e8e19a UKK	99	period_ns > imgchip->max_period_ns) {
2231f6fe	100	dev_err(pwmchip_parent(chip), "configured period not in range\n");
1e70897d NT	101	return -ERANGE;
1e70897d NT	102	}
277bb6a2	103
22e8e19a	104	input_clk_hz = clk_get_rate(imgchip->pwm_clk);
277bb6a2 NT	105	output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
	106
	107	mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
1e70897d	108	if (mul <= max_timebase) {
277bb6a2 NT	109	div = PWM_CTRL_CFG_NO_SUB_DIV;
277bb6a2 NT	110	timebase = DIV_ROUND_UP(mul, 1);
1e70897d	111	} else if (mul <= max_timebase * 8) {
277bb6a2 NT	112	div = PWM_CTRL_CFG_SUB_DIV0;
277bb6a2 NT	113	timebase = DIV_ROUND_UP(mul, 8);
1e70897d	114	} else if (mul <= max_timebase * 64) {
277bb6a2 NT	115	div = PWM_CTRL_CFG_SUB_DIV1;
277bb6a2 NT	116	timebase = DIV_ROUND_UP(mul, 64);
1e70897d	117	} else if (mul <= max_timebase * 512) {
277bb6a2 NT	118	div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
277bb6a2 NT	119	timebase = DIV_ROUND_UP(mul, 512);
44481955	120	} else {
2231f6fe	121	dev_err(pwmchip_parent(chip),
277bb6a2 NT	122	"failed to configure timebase steps/divider value\n");
	123	return -EINVAL;
	124	}
	125
	126	duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
	127
2231f6fe	128	ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
b6ce2af8	129	if (ret < 0)
e690ae52 EB	130	return ret;
e690ae52 EB	131
22e8e19a	132	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
277bb6a2 NT	133	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
	134	val \|= (div & PWM_CTRL_CFG_DIV_MASK) <<
	135	PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
22e8e19a	136	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
277bb6a2 NT	137
	138	val = (duty << PWM_CH_CFG_DUTY_SHIFT) \|
	139	(timebase << PWM_CH_CFG_TMBASE_SHIFT);
22e8e19a	140	img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);
277bb6a2	141
2231f6fe UKK	142	pm_runtime_mark_last_busy(pwmchip_parent(chip));
2231f6fe UKK	143	pm_runtime_put_autosuspend(pwmchip_parent(chip));
e690ae52	144
277bb6a2 NT	145	return 0;
	146	}
	147
	148	static int img_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	149	{
	150	u32 val;
22e8e19a	151	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
e690ae52 EB	152	int ret;
e690ae52 EB	153
2231f6fe	154	ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
e690ae52 EB	155	if (ret < 0)
e690ae52 EB	156	return ret;
277bb6a2	157
22e8e19a	158	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
277bb6a2	159	val \|= BIT(pwm->hwpwm);
22e8e19a	160	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
277bb6a2	161
50f21510 UKK	162	regmap_clear_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
	163	PERIP_PWM_PDM_CONTROL_CH_MASK <<
	164	PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm));
277bb6a2 NT	165
	166	return 0;
	167	}
	168
	169	static void img_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	170	{
	171	u32 val;
22e8e19a	172	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
277bb6a2	173
22e8e19a	174	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
277bb6a2	175	val &= ~BIT(pwm->hwpwm);
22e8e19a	176	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
e690ae52	177
2231f6fe UKK	178	pm_runtime_mark_last_busy(pwmchip_parent(chip));
2231f6fe UKK	179	pm_runtime_put_autosuspend(pwmchip_parent(chip));
277bb6a2 NT	180	}
277bb6a2 NT	181
0ee11b87 UKK	182	static int img_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	183	const struct pwm_state *state)
	184	{
	185	int err;
	186
	187	if (state->polarity != PWM_POLARITY_NORMAL)
	188	return -EINVAL;
	189
	190	if (!state->enabled) {
	191	if (pwm->state.enabled)
	192	img_pwm_disable(chip, pwm);
	193
	194	return 0;
	195	}
	196
80943bbd	197	err = img_pwm_config(chip, pwm, state->duty_cycle, state->period);
0ee11b87 UKK	198	if (err)
	199	return err;
	200
	201	if (!pwm->state.enabled)
	202	err = img_pwm_enable(chip, pwm);
	203
	204	return err;
	205	}
	206
277bb6a2	207	static const struct pwm_ops img_pwm_ops = {
0ee11b87	208	.apply = img_pwm_apply,
277bb6a2 NT	209	};
277bb6a2 NT	210
1e70897d NT	211	static const struct img_pwm_soc_data pistachio_pwm = {
	212	.max_timebase = 255,
	213	};
	214
	215	static const struct of_device_id img_pwm_of_match[] = {
	216	{
	217	.compatible = "img,pistachio-pwm",
	218	.data = &pistachio_pwm,
	219	},
	220	{ }
	221	};
	222	MODULE_DEVICE_TABLE(of, img_pwm_of_match);
	223
e690ae52 EB	224	static int img_pwm_runtime_suspend(struct device *dev)
e690ae52 EB	225	{
b097d28e UKK	226	struct pwm_chip *chip = dev_get_drvdata(dev);
b097d28e UKK	227	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
e690ae52	228
22e8e19a UKK	229	clk_disable_unprepare(imgchip->pwm_clk);
22e8e19a UKK	230	clk_disable_unprepare(imgchip->sys_clk);
e690ae52 EB	231
	232	return 0;
	233	}
	234
	235	static int img_pwm_runtime_resume(struct device *dev)
	236	{
b097d28e UKK	237	struct pwm_chip *chip = dev_get_drvdata(dev);
b097d28e UKK	238	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
e690ae52 EB	239	int ret;
e690ae52 EB	240
22e8e19a	241	ret = clk_prepare_enable(imgchip->sys_clk);
e690ae52 EB	242	if (ret < 0) {
	243	dev_err(dev, "could not prepare or enable sys clock\n");
	244	return ret;
	245	}
	246
22e8e19a	247	ret = clk_prepare_enable(imgchip->pwm_clk);
e690ae52 EB	248	if (ret < 0) {
e690ae52 EB	249	dev_err(dev, "could not prepare or enable pwm clock\n");
22e8e19a	250	clk_disable_unprepare(imgchip->sys_clk);
e690ae52 EB	251	return ret;
	252	}
	253
	254	return 0;
	255	}
	256
277bb6a2 NT	257	static int img_pwm_probe(struct platform_device *pdev)
	258	{
	259	int ret;
1e70897d NT	260	u64 val;
1e70897d NT	261	unsigned long clk_rate;
b097d28e	262	struct pwm_chip *chip;
22e8e19a	263	struct img_pwm_chip *imgchip;
277bb6a2	264
12ca0c33 UKK	265	chip = devm_pwmchip_alloc(&pdev->dev, IMG_PWM_NPWM, sizeof(*imgchip));
	266	if (IS_ERR(chip))
	267	return PTR_ERR(chip);
	268	imgchip = to_img_pwm_chip(chip);
277bb6a2	269
22e8e19a UKK	270	imgchip->base = devm_platform_ioremap_resource(pdev, 0);
	271	if (IS_ERR(imgchip->base))
	272	return PTR_ERR(imgchip->base);
277bb6a2	273
7ee22731	274	imgchip->data = device_get_match_data(&pdev->dev);
1e70897d	275
22e8e19a UKK	276	imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
	277	"img,cr-periph");
	278	if (IS_ERR(imgchip->periph_regs))
	279	return PTR_ERR(imgchip->periph_regs);
277bb6a2	280
22e8e19a UKK	281	imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");
22e8e19a UKK	282	if (IS_ERR(imgchip->sys_clk)) {
277bb6a2	283	dev_err(&pdev->dev, "failed to get system clock\n");
22e8e19a	284	return PTR_ERR(imgchip->sys_clk);
277bb6a2 NT	285	}
277bb6a2 NT	286
9eb05877	287	imgchip->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
22e8e19a	288	if (IS_ERR(imgchip->pwm_clk)) {
9eb05877	289	dev_err(&pdev->dev, "failed to get pwm clock\n");
22e8e19a	290	return PTR_ERR(imgchip->pwm_clk);
277bb6a2 NT	291	}
277bb6a2 NT	292
b097d28e	293	platform_set_drvdata(pdev, chip);
b39c0615	294
e690ae52 EB	295	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
	296	pm_runtime_use_autosuspend(&pdev->dev);
	297	pm_runtime_enable(&pdev->dev);
	298	if (!pm_runtime_enabled(&pdev->dev)) {
	299	ret = img_pwm_runtime_resume(&pdev->dev);
	300	if (ret)
	301	goto err_pm_disable;
277bb6a2 NT	302	}
277bb6a2 NT	303
22e8e19a	304	clk_rate = clk_get_rate(imgchip->pwm_clk);
bea307c1	305	if (!clk_rate) {
22e8e19a	306	dev_err(&pdev->dev, "imgchip clock has no frequency\n");
bea307c1	307	ret = -EINVAL;
e690ae52	308	goto err_suspend;
bea307c1	309	}
1e70897d NT	310
1e70897d NT	311	/* The maximum input clock divider is 512 */
22e8e19a	312	val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;
1e70897d	313	do_div(val, clk_rate);
22e8e19a	314	imgchip->max_period_ns = val;
1e70897d NT	315
	316	val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
	317	do_div(val, clk_rate);
22e8e19a	318	imgchip->min_period_ns = val;
1e70897d	319
b097d28e	320	chip->ops = &img_pwm_ops;
277bb6a2	321
b097d28e	322	ret = pwmchip_add(chip);
277bb6a2 NT	323	if (ret < 0) {
277bb6a2 NT	324	dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
e690ae52	325	goto err_suspend;
277bb6a2 NT	326	}
277bb6a2 NT	327
277bb6a2 NT	328	return 0;
277bb6a2 NT	329
e690ae52 EB	330	err_suspend:
	331	if (!pm_runtime_enabled(&pdev->dev))
	332	img_pwm_runtime_suspend(&pdev->dev);
	333	err_pm_disable:
	334	pm_runtime_disable(&pdev->dev);
	335	pm_runtime_dont_use_autosuspend(&pdev->dev);
277bb6a2 NT	336	return ret;
	337	}
	338
f365a946	339	static void img_pwm_remove(struct platform_device *pdev)
277bb6a2	340	{
b097d28e	341	struct pwm_chip *chip = platform_get_drvdata(pdev);
277bb6a2	342
e690ae52 EB	343	pm_runtime_disable(&pdev->dev);
	344	if (!pm_runtime_status_suspended(&pdev->dev))
	345	img_pwm_runtime_suspend(&pdev->dev);
277bb6a2	346
b097d28e	347	pwmchip_remove(chip);
277bb6a2 NT	348	}
277bb6a2 NT	349
a18afce5 EB	350	#ifdef CONFIG_PM_SLEEP
	351	static int img_pwm_suspend(struct device *dev)
	352	{
b097d28e UKK	353	struct pwm_chip *chip = dev_get_drvdata(dev);
b097d28e UKK	354	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
e690ae52 EB	355	int i, ret;
	356
	357	if (pm_runtime_status_suspended(dev)) {
	358	ret = img_pwm_runtime_resume(dev);
	359	if (ret)
	360	return ret;
	361	}
a18afce5	362
b097d28e	363	for (i = 0; i < chip->npwm; i++)
22e8e19a UKK	364	imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,
22e8e19a UKK	365	PWM_CH_CFG(i));
a18afce5	366
22e8e19a	367	imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);
a18afce5	368
e690ae52	369	img_pwm_runtime_suspend(dev);
a18afce5 EB	370
	371	return 0;
	372	}
	373
	374	static int img_pwm_resume(struct device *dev)
	375	{
b097d28e UKK	376	struct pwm_chip *chip = dev_get_drvdata(dev);
b097d28e UKK	377	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
a18afce5 EB	378	int ret;
	379	int i;
	380
e690ae52 EB	381	ret = img_pwm_runtime_resume(dev);
e690ae52 EB	382	if (ret)
a18afce5	383	return ret;
a18afce5	384
b097d28e	385	for (i = 0; i < chip->npwm; i++)
22e8e19a UKK	386	img_pwm_writel(imgchip, PWM_CH_CFG(i),
22e8e19a UKK	387	imgchip->suspend_ch_cfg[i]);
a18afce5	388
22e8e19a	389	img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);
a18afce5	390
b097d28e	391	for (i = 0; i < chip->npwm; i++)
22e8e19a	392	if (imgchip->suspend_ctrl_cfg & BIT(i))
50f21510 UKK	393	regmap_clear_bits(imgchip->periph_regs,
	394	PERIP_PWM_PDM_CONTROL,
	395	PERIP_PWM_PDM_CONTROL_CH_MASK <<
	396	PERIP_PWM_PDM_CONTROL_CH_SHIFT(i));
a18afce5	397
e690ae52 EB	398	if (pm_runtime_status_suspended(dev))
	399	img_pwm_runtime_suspend(dev);
	400
a18afce5 EB	401	return 0;
	402	}
	403	#endif /* CONFIG_PM */
	404
e690ae52 EB	405	static const struct dev_pm_ops img_pwm_pm_ops = {
	406	SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
	407	img_pwm_runtime_resume,
	408	NULL)
	409	SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
	410	};
a18afce5	411
277bb6a2 NT	412	static struct platform_driver img_pwm_driver = {
	413	.driver = {
	414	.name = "img-pwm",
a18afce5	415	.pm = &img_pwm_pm_ops,
277bb6a2 NT	416	.of_match_table = img_pwm_of_match,
	417	},
	418	.probe = img_pwm_probe,
8db7fdff	419	.remove = img_pwm_remove,
277bb6a2 NT	420	};
	421	module_platform_driver(img_pwm_driver);
	422
	423	MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
	424	MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
	425	MODULE_LICENSE("GPL v2");