[linux-2.6-block.git] / drivers / pwm / pwm-img.c

/*
 * Imagination Technologies Pulse Width Modulator driver
 *
 * Copyright (c) 2014-2015, Imagination Technologies
 *
 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>

/* PWM registers */
#define PWM_CTRL_CFG				0x0000
#define PWM_CTRL_CFG_NO_SUB_DIV			0
#define PWM_CTRL_CFG_SUB_DIV0			1
#define PWM_CTRL_CFG_SUB_DIV1			2
#define PWM_CTRL_CFG_SUB_DIV0_DIV1		3
#define PWM_CTRL_CFG_DIV_SHIFT(ch)		((ch) * 2 + 4)
#define PWM_CTRL_CFG_DIV_MASK			0x3

#define PWM_CH_CFG(ch)				(0x4 + (ch) * 4)
#define PWM_CH_CFG_TMBASE_SHIFT			0
#define PWM_CH_CFG_DUTY_SHIFT			16

#define PERIP_PWM_PDM_CONTROL			0x0140
#define PERIP_PWM_PDM_CONTROL_CH_MASK		0x1
#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch)	((ch) * 4)

#define IMG_PWM_PM_TIMEOUT			1000 /* ms */

/*
 * PWM period is specified with a timebase register,
 * in number of step periods. The PWM duty cycle is also
 * specified in step periods, in the [0, $timebase] range.
 * In other words, the timebase imposes the duty cycle
 * resolution. Therefore, let's constraint the timebase to
 * a minimum value to allow a sane range of duty cycle values.
 * Imposing a minimum timebase, will impose a maximum PWM frequency.
 *
 * The value chosen is completely arbitrary.
 */
#define MIN_TMBASE_STEPS			16

#define IMG_PWM_NPWM				4

struct img_pwm_soc_data {
	u32 max_timebase;
};

struct img_pwm_chip {
	struct device	*dev;
	struct pwm_chip	chip;
	struct clk	*pwm_clk;
	struct clk	*sys_clk;
	void __iomem	*base;
	struct regmap	*periph_regs;
	int		max_period_ns;
	int		min_period_ns;
	const struct img_pwm_soc_data   *data;
	u32		suspend_ctrl_cfg;
	u32		suspend_ch_cfg[IMG_PWM_NPWM];
};

static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct img_pwm_chip, chip);
}

static inline void img_pwm_writel(struct img_pwm_chip *chip,
				  u32 reg, u32 val)
{
	writel(val, chip->base + reg);
}

static inline u32 img_pwm_readl(struct img_pwm_chip *chip,
					 u32 reg)
{
	return readl(chip->base + reg);
}

static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	u32 val, div, duty, timebase;
	unsigned long mul, output_clk_hz, input_clk_hz;
	struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
	unsigned int max_timebase = pwm_chip->data->max_timebase;
	int ret;

	if (period_ns < pwm_chip->min_period_ns ||
	    period_ns > pwm_chip->max_period_ns) {
		dev_err(chip->dev, "configured period not in range\n");
		return -ERANGE;
	}

	input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);
	output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);

	mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
	if (mul <= max_timebase) {
		div = PWM_CTRL_CFG_NO_SUB_DIV;
		timebase = DIV_ROUND_UP(mul, 1);
	} else if (mul <= max_timebase * 8) {
		div = PWM_CTRL_CFG_SUB_DIV0;
		timebase = DIV_ROUND_UP(mul, 8);
	} else if (mul <= max_timebase * 64) {
		div = PWM_CTRL_CFG_SUB_DIV1;
		timebase = DIV_ROUND_UP(mul, 64);
	} else if (mul <= max_timebase * 512) {
		div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
		timebase = DIV_ROUND_UP(mul, 512);
	} else if (mul > max_timebase * 512) {
		dev_err(chip->dev,
			"failed to configure timebase steps/divider value\n");
		return -EINVAL;
	}

	duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);

	ret = pm_runtime_get_sync(chip->dev);
	if (ret < 0)
		return ret;

	val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
	val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
		PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);

	val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
	      (timebase << PWM_CH_CFG_TMBASE_SHIFT);
	img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);

	pm_runtime_mark_last_busy(chip->dev);
	pm_runtime_put_autosuspend(chip->dev);

	return 0;
}

static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	u32 val;
	struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
	int ret;

	ret = pm_runtime_get_sync(chip->dev);
	if (ret < 0)
		return ret;

	val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
	val |= BIT(pwm->hwpwm);
	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);

	regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,
			   PERIP_PWM_PDM_CONTROL_CH_MASK <<
			   PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);

	return 0;
}

static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	u32 val;
	struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);

	val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
	val &= ~BIT(pwm->hwpwm);
	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);

	pm_runtime_mark_last_busy(chip->dev);
	pm_runtime_put_autosuspend(chip->dev);
}

static const struct pwm_ops img_pwm_ops = {
	.config = img_pwm_config,
	.enable = img_pwm_enable,
	.disable = img_pwm_disable,
	.owner = THIS_MODULE,
};

static const struct img_pwm_soc_data pistachio_pwm = {
	.max_timebase = 255,
};

static const struct of_device_id img_pwm_of_match[] = {
	{
		.compatible = "img,pistachio-pwm",
		.data = &pistachio_pwm,
	},
	{ }
};
MODULE_DEVICE_TABLE(of, img_pwm_of_match);

static int img_pwm_runtime_suspend(struct device *dev)
{
	struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);

	clk_disable_unprepare(pwm_chip->pwm_clk);
	clk_disable_unprepare(pwm_chip->sys_clk);

	return 0;
}

static int img_pwm_runtime_resume(struct device *dev)
{
	struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(pwm_chip->sys_clk);
	if (ret < 0) {
		dev_err(dev, "could not prepare or enable sys clock\n");
		return ret;
	}

	ret = clk_prepare_enable(pwm_chip->pwm_clk);
	if (ret < 0) {
		dev_err(dev, "could not prepare or enable pwm clock\n");
		clk_disable_unprepare(pwm_chip->sys_clk);
		return ret;
	}

	return 0;
}

static int img_pwm_probe(struct platform_device *pdev)
{
	int ret;
	u64 val;
	unsigned long clk_rate;
	struct resource *res;
	struct img_pwm_chip *pwm;
	const struct of_device_id *of_dev_id;

	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	if (!pwm)
		return -ENOMEM;

	pwm->dev = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pwm->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pwm->base))
		return PTR_ERR(pwm->base);

	of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
	if (!of_dev_id)
		return -ENODEV;
	pwm->data = of_dev_id->data;

	pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
							   "img,cr-periph");
	if (IS_ERR(pwm->periph_regs))
		return PTR_ERR(pwm->periph_regs);

	pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");
	if (IS_ERR(pwm->sys_clk)) {
		dev_err(&pdev->dev, "failed to get system clock\n");
		return PTR_ERR(pwm->sys_clk);
	}

	pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
	if (IS_ERR(pwm->pwm_clk)) {
		dev_err(&pdev->dev, "failed to get pwm clock\n");
		return PTR_ERR(pwm->pwm_clk);
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = img_pwm_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	clk_rate = clk_get_rate(pwm->pwm_clk);
	if (!clk_rate) {
		dev_err(&pdev->dev, "pwm clock has no frequency\n");
		ret = -EINVAL;
		goto err_suspend;
	}

	/* The maximum input clock divider is 512 */
	val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;
	do_div(val, clk_rate);
	pwm->max_period_ns = val;

	val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
	do_div(val, clk_rate);
	pwm->min_period_ns = val;

	pwm->chip.dev = &pdev->dev;
	pwm->chip.ops = &img_pwm_ops;
	pwm->chip.base = -1;
	pwm->chip.npwm = IMG_PWM_NPWM;

	ret = pwmchip_add(&pwm->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
		goto err_suspend;
	}

	platform_set_drvdata(pdev, pwm);
	return 0;

err_suspend:
	if (!pm_runtime_enabled(&pdev->dev))
		img_pwm_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_dont_use_autosuspend(&pdev->dev);
	return ret;
}

static int img_pwm_remove(struct platform_device *pdev)
{
	struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev);
	u32 val;
	unsigned int i;
	int ret;

	ret = pm_runtime_get_sync(&pdev->dev);
	if (ret < 0)
		return ret;

	for (i = 0; i < pwm_chip->chip.npwm; i++) {
		val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
		val &= ~BIT(i);
		img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
	}

	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		img_pwm_runtime_suspend(&pdev->dev);

	return pwmchip_remove(&pwm_chip->chip);
}

#ifdef CONFIG_PM_SLEEP
static int img_pwm_suspend(struct device *dev)
{
	struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
	int i, ret;

	if (pm_runtime_status_suspended(dev)) {
		ret = img_pwm_runtime_resume(dev);
		if (ret)
			return ret;
	}

	for (i = 0; i < pwm_chip->chip.npwm; i++)
		pwm_chip->suspend_ch_cfg[i] = img_pwm_readl(pwm_chip,
							    PWM_CH_CFG(i));

	pwm_chip->suspend_ctrl_cfg = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);

	img_pwm_runtime_suspend(dev);

	return 0;
}

static int img_pwm_resume(struct device *dev)
{
	struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
	int ret;
	int i;

	ret = img_pwm_runtime_resume(dev);
	if (ret)
		return ret;

	for (i = 0; i < pwm_chip->chip.npwm; i++)
		img_pwm_writel(pwm_chip, PWM_CH_CFG(i),
			       pwm_chip->suspend_ch_cfg[i]);

	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, pwm_chip->suspend_ctrl_cfg);

	for (i = 0; i < pwm_chip->chip.npwm; i++)
		if (pwm_chip->suspend_ctrl_cfg & BIT(i))
			regmap_update_bits(pwm_chip->periph_regs,
					   PERIP_PWM_PDM_CONTROL,
					   PERIP_PWM_PDM_CONTROL_CH_MASK <<
					   PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
					   0);

	if (pm_runtime_status_suspended(dev))
		img_pwm_runtime_suspend(dev);

	return 0;
}
#endif /* CONFIG_PM */

static const struct dev_pm_ops img_pwm_pm_ops = {
	SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
			   img_pwm_runtime_resume,
			   NULL)
	SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
};

static struct platform_driver img_pwm_driver = {
	.driver = {
		.name = "img-pwm",
		.pm = &img_pwm_pm_ops,
		.of_match_table = img_pwm_of_match,
	},
	.probe = img_pwm_probe,
	.remove = img_pwm_remove,
};
module_platform_driver(img_pwm_driver);

MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
277bb6a2 NT	1	/*
	2	* Imagination Technologies Pulse Width Modulator driver
	3	*
	4	* Copyright (c) 2014-2015, Imagination Technologies
	5	*
	6	* Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License.
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/err.h>
	15	#include <linux/io.h>
	16	#include <linux/mfd/syscon.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
1e70897d	19	#include <linux/of_device.h>
277bb6a2	20	#include <linux/platform_device.h>
e690ae52	21	#include <linux/pm_runtime.h>
277bb6a2 NT	22	#include <linux/pwm.h>
	23	#include <linux/regmap.h>
	24	#include <linux/slab.h>
	25
	26	/* PWM registers */
	27	#define PWM_CTRL_CFG 0x0000
	28	#define PWM_CTRL_CFG_NO_SUB_DIV 0
	29	#define PWM_CTRL_CFG_SUB_DIV0 1
	30	#define PWM_CTRL_CFG_SUB_DIV1 2
	31	#define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
	32	#define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
	33	#define PWM_CTRL_CFG_DIV_MASK 0x3
	34
	35	#define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
	36	#define PWM_CH_CFG_TMBASE_SHIFT 0
	37	#define PWM_CH_CFG_DUTY_SHIFT 16
	38
	39	#define PERIP_PWM_PDM_CONTROL 0x0140
	40	#define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
	41	#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
	42
e690ae52 EB	43	#define IMG_PWM_PM_TIMEOUT 1000 /* ms */
e690ae52 EB	44
1e70897d NT	45	/*
	46	* PWM period is specified with a timebase register,
	47	* in number of step periods. The PWM duty cycle is also
	48	* specified in step periods, in the [0, $timebase] range.
	49	* In other words, the timebase imposes the duty cycle
	50	* resolution. Therefore, let's constraint the timebase to
	51	* a minimum value to allow a sane range of duty cycle values.
	52	* Imposing a minimum timebase, will impose a maximum PWM frequency.
	53	*
	54	* The value chosen is completely arbitrary.
	55	*/
	56	#define MIN_TMBASE_STEPS 16
	57
a18afce5 EB	58	#define IMG_PWM_NPWM 4
a18afce5 EB	59
1e70897d NT	60	struct img_pwm_soc_data {
	61	u32 max_timebase;
	62	};
277bb6a2 NT	63
	64	struct img_pwm_chip {
	65	struct device *dev;
	66	struct pwm_chip chip;
	67	struct clk *pwm_clk;
	68	struct clk *sys_clk;
	69	void __iomem *base;
	70	struct regmap *periph_regs;
1e70897d NT	71	int max_period_ns;
	72	int min_period_ns;
	73	const struct img_pwm_soc_data *data;
a18afce5 EB	74	u32 suspend_ctrl_cfg;
a18afce5 EB	75	u32 suspend_ch_cfg[IMG_PWM_NPWM];
277bb6a2 NT	76	};
	77
	78	static inline struct img_pwm_chip to_img_pwm_chip(struct pwm_chip chip)
	79	{
	80	return container_of(chip, struct img_pwm_chip, chip);
	81	}
	82
	83	static inline void img_pwm_writel(struct img_pwm_chip *chip,
	84	u32 reg, u32 val)
	85	{
	86	writel(val, chip->base + reg);
	87	}
	88
	89	static inline u32 img_pwm_readl(struct img_pwm_chip *chip,
	90	u32 reg)
	91	{
	92	return readl(chip->base + reg);
	93	}
	94
	95	static int img_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	96	int duty_ns, int period_ns)
	97	{
	98	u32 val, div, duty, timebase;
	99	unsigned long mul, output_clk_hz, input_clk_hz;
	100	struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
1e70897d	101	unsigned int max_timebase = pwm_chip->data->max_timebase;
e690ae52	102	int ret;
1e70897d NT	103
	104	if (period_ns < pwm_chip->min_period_ns \|\|
	105	period_ns > pwm_chip->max_period_ns) {
	106	dev_err(chip->dev, "configured period not in range\n");
	107	return -ERANGE;
	108	}
277bb6a2 NT	109
	110	input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);
	111	output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
	112
	113	mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
1e70897d	114	if (mul <= max_timebase) {
277bb6a2 NT	115	div = PWM_CTRL_CFG_NO_SUB_DIV;
277bb6a2 NT	116	timebase = DIV_ROUND_UP(mul, 1);
1e70897d	117	} else if (mul <= max_timebase * 8) {
277bb6a2 NT	118	div = PWM_CTRL_CFG_SUB_DIV0;
277bb6a2 NT	119	timebase = DIV_ROUND_UP(mul, 8);
1e70897d	120	} else if (mul <= max_timebase * 64) {
277bb6a2 NT	121	div = PWM_CTRL_CFG_SUB_DIV1;
277bb6a2 NT	122	timebase = DIV_ROUND_UP(mul, 64);
1e70897d	123	} else if (mul <= max_timebase * 512) {
277bb6a2 NT	124	div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
277bb6a2 NT	125	timebase = DIV_ROUND_UP(mul, 512);
1e70897d	126	} else if (mul > max_timebase * 512) {
277bb6a2 NT	127	dev_err(chip->dev,
	128	"failed to configure timebase steps/divider value\n");
	129	return -EINVAL;
	130	}
	131
	132	duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
	133
e690ae52 EB	134	ret = pm_runtime_get_sync(chip->dev);
	135	if (ret < 0)
	136	return ret;
	137
277bb6a2 NT	138	val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
	139	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
	140	val \|= (div & PWM_CTRL_CFG_DIV_MASK) <<
	141	PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
	142	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
	143
	144	val = (duty << PWM_CH_CFG_DUTY_SHIFT) \|
	145	(timebase << PWM_CH_CFG_TMBASE_SHIFT);
	146	img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);
	147
e690ae52 EB	148	pm_runtime_mark_last_busy(chip->dev);
	149	pm_runtime_put_autosuspend(chip->dev);
	150
277bb6a2 NT	151	return 0;
	152	}
	153
	154	static int img_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	155	{
	156	u32 val;
	157	struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
e690ae52 EB	158	int ret;
	159
	160	ret = pm_runtime_get_sync(chip->dev);
	161	if (ret < 0)
	162	return ret;
277bb6a2 NT	163
	164	val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
	165	val \|= BIT(pwm->hwpwm);
	166	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
	167
	168	regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,
	169	PERIP_PWM_PDM_CONTROL_CH_MASK <<
	170	PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
	171
	172	return 0;
	173	}
	174
	175	static void img_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	176	{
	177	u32 val;
	178	struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
	179
	180	val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
	181	val &= ~BIT(pwm->hwpwm);
	182	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
e690ae52 EB	183
	184	pm_runtime_mark_last_busy(chip->dev);
	185	pm_runtime_put_autosuspend(chip->dev);
277bb6a2 NT	186	}
	187
	188	static const struct pwm_ops img_pwm_ops = {
	189	.config = img_pwm_config,
	190	.enable = img_pwm_enable,
	191	.disable = img_pwm_disable,
	192	.owner = THIS_MODULE,
	193	};
	194
1e70897d NT	195	static const struct img_pwm_soc_data pistachio_pwm = {
	196	.max_timebase = 255,
	197	};
	198
	199	static const struct of_device_id img_pwm_of_match[] = {
	200	{
	201	.compatible = "img,pistachio-pwm",
	202	.data = &pistachio_pwm,
	203	},
	204	{ }
	205	};
	206	MODULE_DEVICE_TABLE(of, img_pwm_of_match);
	207
e690ae52 EB	208	static int img_pwm_runtime_suspend(struct device *dev)
	209	{
	210	struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
	211
	212	clk_disable_unprepare(pwm_chip->pwm_clk);
	213	clk_disable_unprepare(pwm_chip->sys_clk);
	214
	215	return 0;
	216	}
	217
	218	static int img_pwm_runtime_resume(struct device *dev)
	219	{
	220	struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
	221	int ret;
	222
	223	ret = clk_prepare_enable(pwm_chip->sys_clk);
	224	if (ret < 0) {
	225	dev_err(dev, "could not prepare or enable sys clock\n");
	226	return ret;
	227	}
	228
	229	ret = clk_prepare_enable(pwm_chip->pwm_clk);
	230	if (ret < 0) {
	231	dev_err(dev, "could not prepare or enable pwm clock\n");
	232	clk_disable_unprepare(pwm_chip->sys_clk);
	233	return ret;
	234	}
	235
	236	return 0;
	237	}
	238
277bb6a2 NT	239	static int img_pwm_probe(struct platform_device *pdev)
	240	{
	241	int ret;
1e70897d NT	242	u64 val;
1e70897d NT	243	unsigned long clk_rate;
277bb6a2 NT	244	struct resource *res;
277bb6a2 NT	245	struct img_pwm_chip *pwm;
1e70897d	246	const struct of_device_id *of_dev_id;
277bb6a2 NT	247
	248	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	249	if (!pwm)
	250	return -ENOMEM;
	251
	252	pwm->dev = &pdev->dev;
	253
	254	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	255	pwm->base = devm_ioremap_resource(&pdev->dev, res);
	256	if (IS_ERR(pwm->base))
	257	return PTR_ERR(pwm->base);
	258
1e70897d NT	259	of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
	260	if (!of_dev_id)
	261	return -ENODEV;
	262	pwm->data = of_dev_id->data;
	263
277bb6a2 NT	264	pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
	265	"img,cr-periph");
	266	if (IS_ERR(pwm->periph_regs))
	267	return PTR_ERR(pwm->periph_regs);
	268
	269	pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");
	270	if (IS_ERR(pwm->sys_clk)) {
	271	dev_err(&pdev->dev, "failed to get system clock\n");
	272	return PTR_ERR(pwm->sys_clk);
	273	}
	274
	275	pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
	276	if (IS_ERR(pwm->pwm_clk)) {
	277	dev_err(&pdev->dev, "failed to get pwm clock\n");
	278	return PTR_ERR(pwm->pwm_clk);
	279	}
	280
e690ae52 EB	281	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
	282	pm_runtime_use_autosuspend(&pdev->dev);
	283	pm_runtime_enable(&pdev->dev);
	284	if (!pm_runtime_enabled(&pdev->dev)) {
	285	ret = img_pwm_runtime_resume(&pdev->dev);
	286	if (ret)
	287	goto err_pm_disable;
277bb6a2 NT	288	}
277bb6a2 NT	289
1e70897d	290	clk_rate = clk_get_rate(pwm->pwm_clk);
bea307c1 WS	291	if (!clk_rate) {
	292	dev_err(&pdev->dev, "pwm clock has no frequency\n");
	293	ret = -EINVAL;
e690ae52	294	goto err_suspend;
bea307c1	295	}
1e70897d NT	296
	297	/* The maximum input clock divider is 512 */
	298	val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;
	299	do_div(val, clk_rate);
	300	pwm->max_period_ns = val;
	301
	302	val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
	303	do_div(val, clk_rate);
	304	pwm->min_period_ns = val;
	305
277bb6a2 NT	306	pwm->chip.dev = &pdev->dev;
	307	pwm->chip.ops = &img_pwm_ops;
	308	pwm->chip.base = -1;
a18afce5	309	pwm->chip.npwm = IMG_PWM_NPWM;
277bb6a2 NT	310
	311	ret = pwmchip_add(&pwm->chip);
	312	if (ret < 0) {
	313	dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
e690ae52	314	goto err_suspend;
277bb6a2 NT	315	}
	316
	317	platform_set_drvdata(pdev, pwm);
	318	return 0;
	319
e690ae52 EB	320	err_suspend:
	321	if (!pm_runtime_enabled(&pdev->dev))
	322	img_pwm_runtime_suspend(&pdev->dev);
	323	err_pm_disable:
	324	pm_runtime_disable(&pdev->dev);
	325	pm_runtime_dont_use_autosuspend(&pdev->dev);
277bb6a2 NT	326	return ret;
	327	}
	328
	329	static int img_pwm_remove(struct platform_device *pdev)
	330	{
	331	struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev);
	332	u32 val;
	333	unsigned int i;
e690ae52 EB	334	int ret;
	335
	336	ret = pm_runtime_get_sync(&pdev->dev);
	337	if (ret < 0)
	338	return ret;
277bb6a2 NT	339
	340	for (i = 0; i < pwm_chip->chip.npwm; i++) {
	341	val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
	342	val &= ~BIT(i);
	343	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
	344	}
	345
e690ae52 EB	346	pm_runtime_put(&pdev->dev);
	347	pm_runtime_disable(&pdev->dev);
	348	if (!pm_runtime_status_suspended(&pdev->dev))
	349	img_pwm_runtime_suspend(&pdev->dev);
277bb6a2 NT	350
	351	return pwmchip_remove(&pwm_chip->chip);
	352	}
	353
a18afce5 EB	354	#ifdef CONFIG_PM_SLEEP
	355	static int img_pwm_suspend(struct device *dev)
	356	{
e690ae52 EB	357	struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
	358	int i, ret;
	359
	360	if (pm_runtime_status_suspended(dev)) {
	361	ret = img_pwm_runtime_resume(dev);
	362	if (ret)
	363	return ret;
	364	}
a18afce5 EB	365
	366	for (i = 0; i < pwm_chip->chip.npwm; i++)
	367	pwm_chip->suspend_ch_cfg[i] = img_pwm_readl(pwm_chip,
	368	PWM_CH_CFG(i));
	369
	370	pwm_chip->suspend_ctrl_cfg = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
	371
e690ae52	372	img_pwm_runtime_suspend(dev);
a18afce5 EB	373
	374	return 0;
	375	}
	376
	377	static int img_pwm_resume(struct device *dev)
	378	{
e690ae52	379	struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
a18afce5 EB	380	int ret;
	381	int i;
	382
e690ae52 EB	383	ret = img_pwm_runtime_resume(dev);
e690ae52 EB	384	if (ret)
a18afce5	385	return ret;
a18afce5 EB	386
	387	for (i = 0; i < pwm_chip->chip.npwm; i++)
	388	img_pwm_writel(pwm_chip, PWM_CH_CFG(i),
	389	pwm_chip->suspend_ch_cfg[i]);
	390
	391	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, pwm_chip->suspend_ctrl_cfg);
	392
	393	for (i = 0; i < pwm_chip->chip.npwm; i++)
	394	if (pwm_chip->suspend_ctrl_cfg & BIT(i))
	395	regmap_update_bits(pwm_chip->periph_regs,
	396	PERIP_PWM_PDM_CONTROL,
	397	PERIP_PWM_PDM_CONTROL_CH_MASK <<
	398	PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
	399	0);
	400
e690ae52 EB	401	if (pm_runtime_status_suspended(dev))
	402	img_pwm_runtime_suspend(dev);
	403
a18afce5 EB	404	return 0;
	405	}
	406	#endif /* CONFIG_PM */
	407
e690ae52 EB	408	static const struct dev_pm_ops img_pwm_pm_ops = {
	409	SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
	410	img_pwm_runtime_resume,
	411	NULL)
	412	SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
	413	};
a18afce5	414
277bb6a2 NT	415	static struct platform_driver img_pwm_driver = {
	416	.driver = {
	417	.name = "img-pwm",
a18afce5	418	.pm = &img_pwm_pm_ops,
277bb6a2 NT	419	.of_match_table = img_pwm_of_match,
	420	},
	421	.probe = img_pwm_probe,
	422	.remove = img_pwm_remove,
	423	};
	424	module_platform_driver(img_pwm_driver);
	425
	426	MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
	427	MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
	428	MODULE_LICENSE("GPL v2");