[linux-block.git] / drivers / pwm / pwm-img.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Imagination Technologies Pulse Width Modulator driver
 *
 * Copyright (c) 2014-2015, Imagination Technologies
 *
 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>

/* PWM registers */
#define PWM_CTRL_CFG				0x0000
#define PWM_CTRL_CFG_NO_SUB_DIV			0
#define PWM_CTRL_CFG_SUB_DIV0			1
#define PWM_CTRL_CFG_SUB_DIV1			2
#define PWM_CTRL_CFG_SUB_DIV0_DIV1		3
#define PWM_CTRL_CFG_DIV_SHIFT(ch)		((ch) * 2 + 4)
#define PWM_CTRL_CFG_DIV_MASK			0x3

#define PWM_CH_CFG(ch)				(0x4 + (ch) * 4)
#define PWM_CH_CFG_TMBASE_SHIFT			0
#define PWM_CH_CFG_DUTY_SHIFT			16

#define PERIP_PWM_PDM_CONTROL			0x0140
#define PERIP_PWM_PDM_CONTROL_CH_MASK		0x1
#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch)	((ch) * 4)

#define IMG_PWM_PM_TIMEOUT			1000 /* ms */

/*
 * PWM period is specified with a timebase register,
 * in number of step periods. The PWM duty cycle is also
 * specified in step periods, in the [0, $timebase] range.
 * In other words, the timebase imposes the duty cycle
 * resolution. Therefore, let's constraint the timebase to
 * a minimum value to allow a sane range of duty cycle values.
 * Imposing a minimum timebase, will impose a maximum PWM frequency.
 *
 * The value chosen is completely arbitrary.
 */
#define MIN_TMBASE_STEPS			16

#define IMG_PWM_NPWM				4

struct img_pwm_soc_data {
	u32 max_timebase;
};

struct img_pwm_chip {
	struct device	*dev;
	struct pwm_chip	chip;
	struct clk	*pwm_clk;
	struct clk	*sys_clk;
	void __iomem	*base;
	struct regmap	*periph_regs;
	int		max_period_ns;
	int		min_period_ns;
	const struct img_pwm_soc_data   *data;
	u32		suspend_ctrl_cfg;
	u32		suspend_ch_cfg[IMG_PWM_NPWM];
};

static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct img_pwm_chip, chip);
}

static inline void img_pwm_writel(struct img_pwm_chip *imgchip,
				  u32 reg, u32 val)
{
	writel(val, imgchip->base + reg);
}

static inline u32 img_pwm_readl(struct img_pwm_chip *imgchip, u32 reg)
{
	return readl(imgchip->base + reg);
}

static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	u32 val, div, duty, timebase;
	unsigned long mul, output_clk_hz, input_clk_hz;
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
	unsigned int max_timebase = imgchip->data->max_timebase;
	int ret;

	if (period_ns < imgchip->min_period_ns ||
	    period_ns > imgchip->max_period_ns) {
		dev_err(chip->dev, "configured period not in range\n");
		return -ERANGE;
	}

	input_clk_hz = clk_get_rate(imgchip->pwm_clk);
	output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);

	mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
	if (mul <= max_timebase) {
		div = PWM_CTRL_CFG_NO_SUB_DIV;
		timebase = DIV_ROUND_UP(mul, 1);
	} else if (mul <= max_timebase * 8) {
		div = PWM_CTRL_CFG_SUB_DIV0;
		timebase = DIV_ROUND_UP(mul, 8);
	} else if (mul <= max_timebase * 64) {
		div = PWM_CTRL_CFG_SUB_DIV1;
		timebase = DIV_ROUND_UP(mul, 64);
	} else if (mul <= max_timebase * 512) {
		div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
		timebase = DIV_ROUND_UP(mul, 512);
	} else {
		dev_err(chip->dev,
			"failed to configure timebase steps/divider value\n");
		return -EINVAL;
	}

	duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);

	ret = pm_runtime_resume_and_get(chip->dev);
	if (ret < 0)
		return ret;

	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
	val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
		PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);

	val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
	      (timebase << PWM_CH_CFG_TMBASE_SHIFT);
	img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);

	pm_runtime_mark_last_busy(chip->dev);
	pm_runtime_put_autosuspend(chip->dev);

	return 0;
}

static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	u32 val;
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
	int ret;

	ret = pm_runtime_resume_and_get(chip->dev);
	if (ret < 0)
		return ret;

	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
	val |= BIT(pwm->hwpwm);
	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);

	regmap_clear_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
			  PERIP_PWM_PDM_CONTROL_CH_MASK <<
			  PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm));

	return 0;
}

static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	u32 val;
	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);

	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
	val &= ~BIT(pwm->hwpwm);
	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);

	pm_runtime_mark_last_busy(chip->dev);
	pm_runtime_put_autosuspend(chip->dev);
}

static int img_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *state)
{
	int err;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (pwm->state.enabled)
			img_pwm_disable(chip, pwm);

		return 0;
	}

	err = img_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!pwm->state.enabled)
		err = img_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops img_pwm_ops = {
	.apply = img_pwm_apply,
	.owner = THIS_MODULE,
};

static const struct img_pwm_soc_data pistachio_pwm = {
	.max_timebase = 255,
};

static const struct of_device_id img_pwm_of_match[] = {
	{
		.compatible = "img,pistachio-pwm",
		.data = &pistachio_pwm,
	},
	{ }
};
MODULE_DEVICE_TABLE(of, img_pwm_of_match);

static int img_pwm_runtime_suspend(struct device *dev)
{
	struct img_pwm_chip *imgchip = dev_get_drvdata(dev);

	clk_disable_unprepare(imgchip->pwm_clk);
	clk_disable_unprepare(imgchip->sys_clk);

	return 0;
}

static int img_pwm_runtime_resume(struct device *dev)
{
	struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(imgchip->sys_clk);
	if (ret < 0) {
		dev_err(dev, "could not prepare or enable sys clock\n");
		return ret;
	}

	ret = clk_prepare_enable(imgchip->pwm_clk);
	if (ret < 0) {
		dev_err(dev, "could not prepare or enable pwm clock\n");
		clk_disable_unprepare(imgchip->sys_clk);
		return ret;
	}

	return 0;
}

static int img_pwm_probe(struct platform_device *pdev)
{
	int ret;
	u64 val;
	unsigned long clk_rate;
	struct img_pwm_chip *imgchip;
	const struct of_device_id *of_dev_id;

	imgchip = devm_kzalloc(&pdev->dev, sizeof(*imgchip), GFP_KERNEL);
	if (!imgchip)
		return -ENOMEM;

	imgchip->dev = &pdev->dev;

	imgchip->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(imgchip->base))
		return PTR_ERR(imgchip->base);

	of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
	if (!of_dev_id)
		return -ENODEV;
	imgchip->data = of_dev_id->data;

	imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
							       "img,cr-periph");
	if (IS_ERR(imgchip->periph_regs))
		return PTR_ERR(imgchip->periph_regs);

	imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");
	if (IS_ERR(imgchip->sys_clk)) {
		dev_err(&pdev->dev, "failed to get system clock\n");
		return PTR_ERR(imgchip->sys_clk);
	}

	imgchip->pwm_clk = devm_clk_get(&pdev->dev, "imgchip");
	if (IS_ERR(imgchip->pwm_clk)) {
		dev_err(&pdev->dev, "failed to get imgchip clock\n");
		return PTR_ERR(imgchip->pwm_clk);
	}

	platform_set_drvdata(pdev, imgchip);

	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = img_pwm_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	clk_rate = clk_get_rate(imgchip->pwm_clk);
	if (!clk_rate) {
		dev_err(&pdev->dev, "imgchip clock has no frequency\n");
		ret = -EINVAL;
		goto err_suspend;
	}

	/* The maximum input clock divider is 512 */
	val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;
	do_div(val, clk_rate);
	imgchip->max_period_ns = val;

	val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
	do_div(val, clk_rate);
	imgchip->min_period_ns = val;

	imgchip->chip.dev = &pdev->dev;
	imgchip->chip.ops = &img_pwm_ops;
	imgchip->chip.npwm = IMG_PWM_NPWM;

	ret = pwmchip_add(&imgchip->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
		goto err_suspend;
	}

	return 0;

err_suspend:
	if (!pm_runtime_enabled(&pdev->dev))
		img_pwm_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_dont_use_autosuspend(&pdev->dev);
	return ret;
}

static void img_pwm_remove(struct platform_device *pdev)
{
	struct img_pwm_chip *imgchip = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		img_pwm_runtime_suspend(&pdev->dev);

	pwmchip_remove(&imgchip->chip);
}

#ifdef CONFIG_PM_SLEEP
static int img_pwm_suspend(struct device *dev)
{
	struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
	int i, ret;

	if (pm_runtime_status_suspended(dev)) {
		ret = img_pwm_runtime_resume(dev);
		if (ret)
			return ret;
	}

	for (i = 0; i < imgchip->chip.npwm; i++)
		imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,
							   PWM_CH_CFG(i));

	imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);

	img_pwm_runtime_suspend(dev);

	return 0;
}

static int img_pwm_resume(struct device *dev)
{
	struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
	int ret;
	int i;

	ret = img_pwm_runtime_resume(dev);
	if (ret)
		return ret;

	for (i = 0; i < imgchip->chip.npwm; i++)
		img_pwm_writel(imgchip, PWM_CH_CFG(i),
			       imgchip->suspend_ch_cfg[i]);

	img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);

	for (i = 0; i < imgchip->chip.npwm; i++)
		if (imgchip->suspend_ctrl_cfg & BIT(i))
			regmap_clear_bits(imgchip->periph_regs,
					  PERIP_PWM_PDM_CONTROL,
					  PERIP_PWM_PDM_CONTROL_CH_MASK <<
					  PERIP_PWM_PDM_CONTROL_CH_SHIFT(i));

	if (pm_runtime_status_suspended(dev))
		img_pwm_runtime_suspend(dev);

	return 0;
}
#endif /* CONFIG_PM */

static const struct dev_pm_ops img_pwm_pm_ops = {
	SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
			   img_pwm_runtime_resume,
			   NULL)
	SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
};

static struct platform_driver img_pwm_driver = {
	.driver = {
		.name = "img-pwm",
		.pm = &img_pwm_pm_ops,
		.of_match_table = img_pwm_of_match,
	},
	.probe = img_pwm_probe,
	.remove_new = img_pwm_remove,
};
module_platform_driver(img_pwm_driver);

MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
84a14ae8	1	// SPDX-License-Identifier: GPL-2.0-only
277bb6a2 NT	2	/*
	3	* Imagination Technologies Pulse Width Modulator driver
	4	*
	5	* Copyright (c) 2014-2015, Imagination Technologies
	6	*
	7	* Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
277bb6a2 NT	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/err.h>
	12	#include <linux/io.h>
	13	#include <linux/mfd/syscon.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
1e70897d	16	#include <linux/of_device.h>
277bb6a2	17	#include <linux/platform_device.h>
e690ae52	18	#include <linux/pm_runtime.h>
277bb6a2 NT	19	#include <linux/pwm.h>
	20	#include <linux/regmap.h>
	21	#include <linux/slab.h>
	22
	23	/* PWM registers */
	24	#define PWM_CTRL_CFG 0x0000
	25	#define PWM_CTRL_CFG_NO_SUB_DIV 0
	26	#define PWM_CTRL_CFG_SUB_DIV0 1
	27	#define PWM_CTRL_CFG_SUB_DIV1 2
	28	#define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
	29	#define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
	30	#define PWM_CTRL_CFG_DIV_MASK 0x3
	31
	32	#define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
	33	#define PWM_CH_CFG_TMBASE_SHIFT 0
	34	#define PWM_CH_CFG_DUTY_SHIFT 16
	35
	36	#define PERIP_PWM_PDM_CONTROL 0x0140
	37	#define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
	38	#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
	39
e690ae52 EB	40	#define IMG_PWM_PM_TIMEOUT 1000 /* ms */
e690ae52 EB	41
1e70897d NT	42	/*
	43	* PWM period is specified with a timebase register,
	44	* in number of step periods. The PWM duty cycle is also
	45	* specified in step periods, in the [0, $timebase] range.
	46	* In other words, the timebase imposes the duty cycle
	47	* resolution. Therefore, let's constraint the timebase to
	48	* a minimum value to allow a sane range of duty cycle values.
	49	* Imposing a minimum timebase, will impose a maximum PWM frequency.
	50	*
	51	* The value chosen is completely arbitrary.
	52	*/
	53	#define MIN_TMBASE_STEPS 16
	54
a18afce5 EB	55	#define IMG_PWM_NPWM 4
a18afce5 EB	56
1e70897d NT	57	struct img_pwm_soc_data {
	58	u32 max_timebase;
	59	};
277bb6a2 NT	60
	61	struct img_pwm_chip {
	62	struct device *dev;
	63	struct pwm_chip chip;
	64	struct clk *pwm_clk;
	65	struct clk *sys_clk;
	66	void __iomem *base;
	67	struct regmap *periph_regs;
1e70897d NT	68	int max_period_ns;
	69	int min_period_ns;
	70	const struct img_pwm_soc_data *data;
a18afce5 EB	71	u32 suspend_ctrl_cfg;
a18afce5 EB	72	u32 suspend_ch_cfg[IMG_PWM_NPWM];
277bb6a2 NT	73	};
	74
	75	static inline struct img_pwm_chip to_img_pwm_chip(struct pwm_chip chip)
	76	{
	77	return container_of(chip, struct img_pwm_chip, chip);
	78	}
	79
22e8e19a	80	static inline void img_pwm_writel(struct img_pwm_chip *imgchip,
277bb6a2 NT	81	u32 reg, u32 val)
277bb6a2 NT	82	{
22e8e19a	83	writel(val, imgchip->base + reg);
277bb6a2 NT	84	}
277bb6a2 NT	85
22e8e19a	86	static inline u32 img_pwm_readl(struct img_pwm_chip *imgchip, u32 reg)
277bb6a2	87	{
22e8e19a	88	return readl(imgchip->base + reg);
277bb6a2 NT	89	}
	90
	91	static int img_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	92	int duty_ns, int period_ns)
	93	{
	94	u32 val, div, duty, timebase;
	95	unsigned long mul, output_clk_hz, input_clk_hz;
22e8e19a UKK	96	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
22e8e19a UKK	97	unsigned int max_timebase = imgchip->data->max_timebase;
e690ae52	98	int ret;
1e70897d	99
22e8e19a UKK	100	if (period_ns < imgchip->min_period_ns \|\|
22e8e19a UKK	101	period_ns > imgchip->max_period_ns) {
1e70897d NT	102	dev_err(chip->dev, "configured period not in range\n");
	103	return -ERANGE;
	104	}
277bb6a2	105
22e8e19a	106	input_clk_hz = clk_get_rate(imgchip->pwm_clk);
277bb6a2 NT	107	output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
	108
	109	mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
1e70897d	110	if (mul <= max_timebase) {
277bb6a2 NT	111	div = PWM_CTRL_CFG_NO_SUB_DIV;
277bb6a2 NT	112	timebase = DIV_ROUND_UP(mul, 1);
1e70897d	113	} else if (mul <= max_timebase * 8) {
277bb6a2 NT	114	div = PWM_CTRL_CFG_SUB_DIV0;
277bb6a2 NT	115	timebase = DIV_ROUND_UP(mul, 8);
1e70897d	116	} else if (mul <= max_timebase * 64) {
277bb6a2 NT	117	div = PWM_CTRL_CFG_SUB_DIV1;
277bb6a2 NT	118	timebase = DIV_ROUND_UP(mul, 64);
1e70897d	119	} else if (mul <= max_timebase * 512) {
277bb6a2 NT	120	div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
277bb6a2 NT	121	timebase = DIV_ROUND_UP(mul, 512);
44481955	122	} else {
277bb6a2 NT	123	dev_err(chip->dev,
	124	"failed to configure timebase steps/divider value\n");
	125	return -EINVAL;
	126	}
	127
	128	duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
	129
b6ce2af8 UKK	130	ret = pm_runtime_resume_and_get(chip->dev);
b6ce2af8 UKK	131	if (ret < 0)
e690ae52 EB	132	return ret;
e690ae52 EB	133
22e8e19a	134	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
277bb6a2 NT	135	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
	136	val \|= (div & PWM_CTRL_CFG_DIV_MASK) <<
	137	PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
22e8e19a	138	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
277bb6a2 NT	139
	140	val = (duty << PWM_CH_CFG_DUTY_SHIFT) \|
	141	(timebase << PWM_CH_CFG_TMBASE_SHIFT);
22e8e19a	142	img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);
277bb6a2	143
e690ae52 EB	144	pm_runtime_mark_last_busy(chip->dev);
	145	pm_runtime_put_autosuspend(chip->dev);
	146
277bb6a2 NT	147	return 0;
	148	}
	149
	150	static int img_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	151	{
	152	u32 val;
22e8e19a	153	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
e690ae52 EB	154	int ret;
e690ae52 EB	155
fde25294	156	ret = pm_runtime_resume_and_get(chip->dev);
e690ae52 EB	157	if (ret < 0)
e690ae52 EB	158	return ret;
277bb6a2	159
22e8e19a	160	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
277bb6a2	161	val \|= BIT(pwm->hwpwm);
22e8e19a	162	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
277bb6a2	163
50f21510 UKK	164	regmap_clear_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
	165	PERIP_PWM_PDM_CONTROL_CH_MASK <<
	166	PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm));
277bb6a2 NT	167
	168	return 0;
	169	}
	170
	171	static void img_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	172	{
	173	u32 val;
22e8e19a	174	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
277bb6a2	175
22e8e19a	176	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
277bb6a2	177	val &= ~BIT(pwm->hwpwm);
22e8e19a	178	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
e690ae52 EB	179
	180	pm_runtime_mark_last_busy(chip->dev);
	181	pm_runtime_put_autosuspend(chip->dev);
277bb6a2 NT	182	}
277bb6a2 NT	183
0ee11b87 UKK	184	static int img_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	185	const struct pwm_state *state)
	186	{
	187	int err;
	188
	189	if (state->polarity != PWM_POLARITY_NORMAL)
	190	return -EINVAL;
	191
	192	if (!state->enabled) {
	193	if (pwm->state.enabled)
	194	img_pwm_disable(chip, pwm);
	195
	196	return 0;
	197	}
	198
	199	err = img_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
	200	if (err)
	201	return err;
	202
	203	if (!pwm->state.enabled)
	204	err = img_pwm_enable(chip, pwm);
	205
	206	return err;
	207	}
	208
277bb6a2	209	static const struct pwm_ops img_pwm_ops = {
0ee11b87	210	.apply = img_pwm_apply,
277bb6a2 NT	211	.owner = THIS_MODULE,
	212	};
	213
1e70897d NT	214	static const struct img_pwm_soc_data pistachio_pwm = {
	215	.max_timebase = 255,
	216	};
	217
	218	static const struct of_device_id img_pwm_of_match[] = {
	219	{
	220	.compatible = "img,pistachio-pwm",
	221	.data = &pistachio_pwm,
	222	},
	223	{ }
	224	};
	225	MODULE_DEVICE_TABLE(of, img_pwm_of_match);
	226
e690ae52 EB	227	static int img_pwm_runtime_suspend(struct device *dev)
e690ae52 EB	228	{
22e8e19a	229	struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
e690ae52	230
22e8e19a UKK	231	clk_disable_unprepare(imgchip->pwm_clk);
22e8e19a UKK	232	clk_disable_unprepare(imgchip->sys_clk);
e690ae52 EB	233
	234	return 0;
	235	}
	236
	237	static int img_pwm_runtime_resume(struct device *dev)
	238	{
22e8e19a	239	struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
e690ae52 EB	240	int ret;
e690ae52 EB	241
22e8e19a	242	ret = clk_prepare_enable(imgchip->sys_clk);
e690ae52 EB	243	if (ret < 0) {
	244	dev_err(dev, "could not prepare or enable sys clock\n");
	245	return ret;
	246	}
	247
22e8e19a	248	ret = clk_prepare_enable(imgchip->pwm_clk);
e690ae52 EB	249	if (ret < 0) {
e690ae52 EB	250	dev_err(dev, "could not prepare or enable pwm clock\n");
22e8e19a	251	clk_disable_unprepare(imgchip->sys_clk);
e690ae52 EB	252	return ret;
	253	}
	254
	255	return 0;
	256	}
	257
277bb6a2 NT	258	static int img_pwm_probe(struct platform_device *pdev)
	259	{
	260	int ret;
1e70897d NT	261	u64 val;
1e70897d NT	262	unsigned long clk_rate;
22e8e19a	263	struct img_pwm_chip *imgchip;
1e70897d	264	const struct of_device_id *of_dev_id;
277bb6a2	265
22e8e19a UKK	266	imgchip = devm_kzalloc(&pdev->dev, sizeof(*imgchip), GFP_KERNEL);
22e8e19a UKK	267	if (!imgchip)
277bb6a2 NT	268	return -ENOMEM;
277bb6a2 NT	269
22e8e19a	270	imgchip->dev = &pdev->dev;
277bb6a2	271
22e8e19a UKK	272	imgchip->base = devm_platform_ioremap_resource(pdev, 0);
	273	if (IS_ERR(imgchip->base))
	274	return PTR_ERR(imgchip->base);
277bb6a2	275
1e70897d NT	276	of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
	277	if (!of_dev_id)
	278	return -ENODEV;
22e8e19a	279	imgchip->data = of_dev_id->data;
1e70897d	280
22e8e19a UKK	281	imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
	282	"img,cr-periph");
	283	if (IS_ERR(imgchip->periph_regs))
	284	return PTR_ERR(imgchip->periph_regs);
277bb6a2	285
22e8e19a UKK	286	imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");
22e8e19a UKK	287	if (IS_ERR(imgchip->sys_clk)) {
277bb6a2	288	dev_err(&pdev->dev, "failed to get system clock\n");
22e8e19a	289	return PTR_ERR(imgchip->sys_clk);
277bb6a2 NT	290	}
277bb6a2 NT	291
22e8e19a UKK	292	imgchip->pwm_clk = devm_clk_get(&pdev->dev, "imgchip");
	293	if (IS_ERR(imgchip->pwm_clk)) {
	294	dev_err(&pdev->dev, "failed to get imgchip clock\n");
	295	return PTR_ERR(imgchip->pwm_clk);
277bb6a2 NT	296	}
277bb6a2 NT	297
22e8e19a	298	platform_set_drvdata(pdev, imgchip);
b39c0615	299
e690ae52 EB	300	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
	301	pm_runtime_use_autosuspend(&pdev->dev);
	302	pm_runtime_enable(&pdev->dev);
	303	if (!pm_runtime_enabled(&pdev->dev)) {
	304	ret = img_pwm_runtime_resume(&pdev->dev);
	305	if (ret)
	306	goto err_pm_disable;
277bb6a2 NT	307	}
277bb6a2 NT	308
22e8e19a	309	clk_rate = clk_get_rate(imgchip->pwm_clk);
bea307c1	310	if (!clk_rate) {
22e8e19a	311	dev_err(&pdev->dev, "imgchip clock has no frequency\n");
bea307c1	312	ret = -EINVAL;
e690ae52	313	goto err_suspend;
bea307c1	314	}
1e70897d NT	315
1e70897d NT	316	/* The maximum input clock divider is 512 */
22e8e19a	317	val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;
1e70897d	318	do_div(val, clk_rate);
22e8e19a	319	imgchip->max_period_ns = val;
1e70897d NT	320
	321	val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
	322	do_div(val, clk_rate);
22e8e19a	323	imgchip->min_period_ns = val;
1e70897d	324
22e8e19a UKK	325	imgchip->chip.dev = &pdev->dev;
	326	imgchip->chip.ops = &img_pwm_ops;
	327	imgchip->chip.npwm = IMG_PWM_NPWM;
277bb6a2	328
22e8e19a	329	ret = pwmchip_add(&imgchip->chip);
277bb6a2 NT	330	if (ret < 0) {
277bb6a2 NT	331	dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
e690ae52	332	goto err_suspend;
277bb6a2 NT	333	}
277bb6a2 NT	334
277bb6a2 NT	335	return 0;
277bb6a2 NT	336
e690ae52 EB	337	err_suspend:
	338	if (!pm_runtime_enabled(&pdev->dev))
	339	img_pwm_runtime_suspend(&pdev->dev);
	340	err_pm_disable:
	341	pm_runtime_disable(&pdev->dev);
	342	pm_runtime_dont_use_autosuspend(&pdev->dev);
277bb6a2 NT	343	return ret;
	344	}
	345
f365a946	346	static void img_pwm_remove(struct platform_device *pdev)
277bb6a2	347	{
22e8e19a	348	struct img_pwm_chip *imgchip = platform_get_drvdata(pdev);
277bb6a2	349
e690ae52 EB	350	pm_runtime_disable(&pdev->dev);
	351	if (!pm_runtime_status_suspended(&pdev->dev))
	352	img_pwm_runtime_suspend(&pdev->dev);
277bb6a2	353
22e8e19a	354	pwmchip_remove(&imgchip->chip);
277bb6a2 NT	355	}
277bb6a2 NT	356
a18afce5 EB	357	#ifdef CONFIG_PM_SLEEP
	358	static int img_pwm_suspend(struct device *dev)
	359	{
22e8e19a	360	struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
e690ae52 EB	361	int i, ret;
	362
	363	if (pm_runtime_status_suspended(dev)) {
	364	ret = img_pwm_runtime_resume(dev);
	365	if (ret)
	366	return ret;
	367	}
a18afce5	368
22e8e19a UKK	369	for (i = 0; i < imgchip->chip.npwm; i++)
	370	imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,
	371	PWM_CH_CFG(i));
a18afce5	372
22e8e19a	373	imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);
a18afce5	374
e690ae52	375	img_pwm_runtime_suspend(dev);
a18afce5 EB	376
	377	return 0;
	378	}
	379
	380	static int img_pwm_resume(struct device *dev)
	381	{
22e8e19a	382	struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
a18afce5 EB	383	int ret;
	384	int i;
	385
e690ae52 EB	386	ret = img_pwm_runtime_resume(dev);
e690ae52 EB	387	if (ret)
a18afce5	388	return ret;
a18afce5	389
22e8e19a UKK	390	for (i = 0; i < imgchip->chip.npwm; i++)
	391	img_pwm_writel(imgchip, PWM_CH_CFG(i),
	392	imgchip->suspend_ch_cfg[i]);
a18afce5	393
22e8e19a	394	img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);
a18afce5	395
22e8e19a UKK	396	for (i = 0; i < imgchip->chip.npwm; i++)
22e8e19a UKK	397	if (imgchip->suspend_ctrl_cfg & BIT(i))
50f21510 UKK	398	regmap_clear_bits(imgchip->periph_regs,
	399	PERIP_PWM_PDM_CONTROL,
	400	PERIP_PWM_PDM_CONTROL_CH_MASK <<
	401	PERIP_PWM_PDM_CONTROL_CH_SHIFT(i));
a18afce5	402
e690ae52 EB	403	if (pm_runtime_status_suspended(dev))
	404	img_pwm_runtime_suspend(dev);
	405
a18afce5 EB	406	return 0;
	407	}
	408	#endif /* CONFIG_PM */
	409
e690ae52 EB	410	static const struct dev_pm_ops img_pwm_pm_ops = {
	411	SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
	412	img_pwm_runtime_resume,
	413	NULL)
	414	SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
	415	};
a18afce5	416
277bb6a2 NT	417	static struct platform_driver img_pwm_driver = {
	418	.driver = {
	419	.name = "img-pwm",
a18afce5	420	.pm = &img_pwm_pm_ops,
277bb6a2 NT	421	.of_match_table = img_pwm_of_match,
	422	},
	423	.probe = img_pwm_probe,
f365a946	424	.remove_new = img_pwm_remove,
277bb6a2 NT	425	};
	426	module_platform_driver(img_pwm_driver);
	427
	428	MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
	429	MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
	430	MODULE_LICENSE("GPL v2");