[linux-block.git] / drivers / pwm / pwm-fsl-ftm.c

/*
 *  Freescale FlexTimer Module (FTM) PWM Driver
 *
 *  Copyright 2012-2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/fsl/ftm.h>

#define FTM_SC_CLK(c)	(((c) + 1) << FTM_SC_CLK_MASK_SHIFT)

enum fsl_pwm_clk {
	FSL_PWM_CLK_SYS,
	FSL_PWM_CLK_FIX,
	FSL_PWM_CLK_EXT,
	FSL_PWM_CLK_CNTEN,
	FSL_PWM_CLK_MAX
};

struct fsl_ftm_soc {
	bool has_enable_bits;
};

struct fsl_pwm_periodcfg {
	enum fsl_pwm_clk clk_select;
	unsigned int clk_ps;
	unsigned int mod_period;
};

struct fsl_pwm_chip {
	struct pwm_chip chip;
	struct mutex lock;
	struct regmap *regmap;

	/* This value is valid iff a pwm is running */
	struct fsl_pwm_periodcfg period;

	struct clk *ipg_clk;
	struct clk *clk[FSL_PWM_CLK_MAX];

	const struct fsl_ftm_soc *soc;
};

static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct fsl_pwm_chip, chip);
}

static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_FMS, &val);
	if (val & FTM_FMS_WPEN)
		regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS,
				   FTM_MODE_WPDIS);
}

static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
{
	regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN);
}

static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
					const struct fsl_pwm_periodcfg *b)
{
	if (a->clk_select != b->clk_select)
		return false;
	if (a->clk_ps != b->clk_ps)
		return false;
	if (a->mod_period != b->mod_period)
		return false;
	return true;
}

static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	int ret;
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (!ret && fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
				   BIT(pwm->hwpwm + 16));
		mutex_unlock(&fpc->lock);
	}

	return ret;
}

static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	if (fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
				   0);
		mutex_unlock(&fpc->lock);
	}

	clk_disable_unprepare(fpc->ipg_clk);
}

static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
					  unsigned int ticks)
{
	unsigned long rate;
	unsigned long long exval;

	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
	exval = ticks;
	exval *= 1000000000UL;
	do_div(exval, rate >> fpc->period.clk_ps);
	return exval;
}

static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
					 unsigned int period_ns,
					 enum fsl_pwm_clk index,
					 struct fsl_pwm_periodcfg *periodcfg
					 )
{
	unsigned long long c;
	unsigned int ps;

	c = clk_get_rate(fpc->clk[index]);
	c = c * period_ns;
	do_div(c, 1000000000UL);

	if (c == 0)
		return false;

	for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
		if (c <= 0x10000) {
			periodcfg->clk_select = index;
			periodcfg->clk_ps = ps;
			periodcfg->mod_period = c - 1;
			return true;
		}
	}
	return false;
}

static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
				     unsigned int period_ns,
				     struct fsl_pwm_periodcfg *periodcfg)
{
	enum fsl_pwm_clk m0, m1;
	unsigned long fix_rate, ext_rate;
	bool ret;

	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
					   periodcfg);
	if (ret)
		return true;

	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);

	if (fix_rate > ext_rate) {
		m0 = FSL_PWM_CLK_FIX;
		m1 = FSL_PWM_CLK_EXT;
	} else {
		m0 = FSL_PWM_CLK_EXT;
		m1 = FSL_PWM_CLK_FIX;
	}

	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
	if (ret)
		return true;

	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
}

static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
					   unsigned int duty_ns)
{
	unsigned long long duty;

	unsigned int period = fpc->period.mod_period + 1;
	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);

	duty = (unsigned long long)duty_ns * period;
	do_div(duty, period_ns);

	return (unsigned int)duty;
}

static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
				       struct pwm_device *pwm)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	if (~val & 0xFF)
		return true;
	else
		return false;
}

static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
					 struct pwm_device *pwm)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	if (~(val | BIT(pwm->hwpwm)) & 0xFF)
		return true;
	else
		return false;
}

static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
				struct pwm_device *pwm,
				struct pwm_state *newstate)
{
	unsigned int duty;
	u32 reg_polarity;

	struct fsl_pwm_periodcfg periodcfg;
	bool do_write_period = false;

	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
		dev_err(fpc->chip.dev, "failed to calculate new period\n");
		return -EINVAL;
	}

	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
		do_write_period = true;
	/*
	 * The Freescale FTM controller supports only a single period for
	 * all PWM channels, therefore verify if the newly computed period
	 * is different than the current period being used. In such case
	 * we allow to change the period only if no other pwm is running.
	 */
	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
		if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
			dev_err(fpc->chip.dev,
				"Cannot change period for PWM %u, disable other PWMs first\n",
				pwm->hwpwm);
			return -EBUSY;
		}
		if (fpc->period.clk_select != periodcfg.clk_select) {
			int ret;
			enum fsl_pwm_clk oldclk = fpc->period.clk_select;
			enum fsl_pwm_clk newclk = periodcfg.clk_select;

			ret = clk_prepare_enable(fpc->clk[newclk]);
			if (ret)
				return ret;
			clk_disable_unprepare(fpc->clk[oldclk]);
		}
		do_write_period = true;
	}

	ftm_clear_write_protection(fpc);

	if (do_write_period) {
		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
				   FTM_SC_CLK(periodcfg.clk_select));
		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
				   periodcfg.clk_ps);
		regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);

		fpc->period = periodcfg;
	}

	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);

	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
		     FTM_CSC_MSB | FTM_CSC_ELSB);
	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);

	reg_polarity = 0;
	if (newstate->polarity == PWM_POLARITY_INVERSED)
		reg_polarity = BIT(pwm->hwpwm);

	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);

	newstate->period = fsl_pwm_ticks_to_ns(fpc,
					       fpc->period.mod_period + 1);
	newstate->duty_cycle = fsl_pwm_ticks_to_ns(fpc, duty);

	ftm_set_write_protection(fpc);

	return 0;
}

static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 struct pwm_state *newstate)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	struct pwm_state *oldstate = &pwm->state;
	int ret = 0;

	/*
	 * oldstate to newstate : action
	 *
	 * disabled to disabled : ignore
	 * enabled to disabled : disable
	 * enabled to enabled : update settings
	 * disabled to enabled : update settings + enable
	 */

	mutex_lock(&fpc->lock);

	if (!newstate->enabled) {
		if (oldstate->enabled) {
			regmap_update_bits(fpc->regmap, FTM_OUTMASK,
					   BIT(pwm->hwpwm), BIT(pwm->hwpwm));
			clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
		}

		goto end_mutex;
	}

	ret = fsl_pwm_apply_config(fpc, pwm, newstate);
	if (ret)
		goto end_mutex;

	/* check if need to enable */
	if (!oldstate->enabled) {
		ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
		if (ret)
			return ret;

		ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
		if (ret) {
			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
			return ret;
		}

		regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
				   0);
	}

end_mutex:
	mutex_unlock(&fpc->lock);
	return ret;
}

static const struct pwm_ops fsl_pwm_ops = {
	.request = fsl_pwm_request,
	.free = fsl_pwm_free,
	.apply = fsl_pwm_apply,
	.owner = THIS_MODULE,
};

static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
{
	int ret;

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (ret)
		return ret;

	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);

	clk_disable_unprepare(fpc->ipg_clk);

	return 0;
}

static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case FTM_FMS:
	case FTM_MODE:
	case FTM_CNT:
		return true;
	}
	return false;
}

static const struct regmap_config fsl_pwm_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,

	.max_register = FTM_PWMLOAD,
	.volatile_reg = fsl_pwm_volatile_reg,
	.cache_type = REGCACHE_FLAT,
};

static int fsl_pwm_probe(struct platform_device *pdev)
{
	struct fsl_pwm_chip *fpc;
	struct resource *res;
	void __iomem *base;
	int ret;

	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
	if (!fpc)
		return -ENOMEM;

	mutex_init(&fpc->lock);

	fpc->soc = of_device_get_match_data(&pdev->dev);
	fpc->chip.dev = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
						&fsl_pwm_regmap_config);
	if (IS_ERR(fpc->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(fpc->regmap);
	}

	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
		dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	}

	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);

	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);

	fpc->clk[FSL_PWM_CLK_CNTEN] =
				devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);

	/*
	 * ipg_clk is the interface clock for the IP. If not provided, use the
	 * ftm_sys clock as the default.
	 */
	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(fpc->ipg_clk))
		fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];


	fpc->chip.ops = &fsl_pwm_ops;
	fpc->chip.of_xlate = of_pwm_xlate_with_flags;
	fpc->chip.of_pwm_n_cells = 3;
	fpc->chip.base = -1;
	fpc->chip.npwm = 8;

	ret = pwmchip_add(&fpc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, fpc);

	return fsl_pwm_init(fpc);
}

static int fsl_pwm_remove(struct platform_device *pdev)
{
	struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);

	return pwmchip_remove(&fpc->chip);
}

#ifdef CONFIG_PM_SLEEP
static int fsl_pwm_suspend(struct device *dev)
{
	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
	int i;

	regcache_cache_only(fpc->regmap, true);
	regcache_mark_dirty(fpc->regmap);

	for (i = 0; i < fpc->chip.npwm; i++) {
		struct pwm_device *pwm = &fpc->chip.pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_disable_unprepare(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
		clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	}

	return 0;
}

static int fsl_pwm_resume(struct device *dev)
{
	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
	int i;

	for (i = 0; i < fpc->chip.npwm; i++) {
		struct pwm_device *pwm = &fpc->chip.pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_prepare_enable(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	}

	/* restore all registers from cache */
	regcache_cache_only(fpc->regmap, false);
	regcache_sync(fpc->regmap);

	return 0;
}
#endif

static const struct dev_pm_ops fsl_pwm_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
};

static const struct fsl_ftm_soc vf610_ftm_pwm = {
	.has_enable_bits = false,
};

static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	.has_enable_bits = true,
};

static const struct of_device_id fsl_pwm_dt_ids[] = {
	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);

static struct platform_driver fsl_pwm_driver = {
	.driver = {
		.name = "fsl-ftm-pwm",
		.of_match_table = fsl_pwm_dt_ids,
		.pm = &fsl_pwm_pm_ops,
	},
	.probe = fsl_pwm_probe,
	.remove = fsl_pwm_remove,
};
module_platform_driver(fsl_pwm_driver);

MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
MODULE_ALIAS("platform:fsl-ftm-pwm");
MODULE_LICENSE("GPL");
Commit	Line	Data
b505183b XL	1	/*
	2	* Freescale FlexTimer Module (FTM) PWM Driver
	3	*
	4	* Copyright 2012-2013 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/err.h>
	14	#include <linux/io.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/mutex.h>
	18	#include <linux/of_address.h>
db6c51ab	19	#include <linux/of_device.h>
b505183b	20	#include <linux/platform_device.h>
97d0b42e	21	#include <linux/pm.h>
b505183b	22	#include <linux/pwm.h>
42fa98a9	23	#include <linux/regmap.h>
b505183b	24	#include <linux/slab.h>
e590eb40	25	#include <linux/fsl/ftm.h>
b505183b	26
cd6d92d2	27	#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
b505183b XL	28
	29	enum fsl_pwm_clk {
	30	FSL_PWM_CLK_SYS,
	31	FSL_PWM_CLK_FIX,
	32	FSL_PWM_CLK_EXT,
	33	FSL_PWM_CLK_CNTEN,
	34	FSL_PWM_CLK_MAX
	35	};
	36
db6c51ab	37	struct fsl_ftm_soc {
	38	bool has_enable_bits;
	39	};
	40
3479bbd1 PH	41	struct fsl_pwm_periodcfg {
	42	enum fsl_pwm_clk clk_select;
	43	unsigned int clk_ps;
	44	unsigned int mod_period;
	45	};
	46
b505183b XL	47	struct fsl_pwm_chip {
b505183b XL	48	struct pwm_chip chip;
b505183b	49	struct mutex lock;
42fa98a9	50	struct regmap *regmap;
b505183b	51
3479bbd1 PH	52	/* This value is valid iff a pwm is running */
3479bbd1 PH	53	struct fsl_pwm_periodcfg period;
b505183b	54
82a9c55a	55	struct clk *ipg_clk;
b505183b	56	struct clk *clk[FSL_PWM_CLK_MAX];
db6c51ab	57
db6c51ab	58	const struct fsl_ftm_soc *soc;
b505183b XL	59	};
	60
	61	static inline struct fsl_pwm_chip to_fsl_chip(struct pwm_chip chip)
	62	{
	63	return container_of(chip, struct fsl_pwm_chip, chip);
	64	}
	65
a2a28229 PH	66	static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
	67	{
	68	u32 val;
	69
	70	regmap_read(fpc->regmap, FTM_FMS, &val);
	71	if (val & FTM_FMS_WPEN)
	72	regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS,
	73	FTM_MODE_WPDIS);
	74	}
	75
	76	static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
	77	{
	78	regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN);
	79	}
	80
3479bbd1 PH	81	static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
	82	const struct fsl_pwm_periodcfg *b)
	83	{
	84	if (a->clk_select != b->clk_select)
	85	return false;
	86	if (a->clk_ps != b->clk_ps)
	87	return false;
	88	if (a->mod_period != b->mod_period)
	89	return false;
	90	return true;
	91	}
	92
b505183b XL	93	static int fsl_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
b505183b XL	94	{
db6c51ab	95	int ret;
b505183b XL	96	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
b505183b XL	97
db6c51ab	98	ret = clk_prepare_enable(fpc->ipg_clk);
	99	if (!ret && fpc->soc->has_enable_bits) {
	100	mutex_lock(&fpc->lock);
	101	regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
	102	BIT(pwm->hwpwm + 16));
	103	mutex_unlock(&fpc->lock);
	104	}
	105
	106	return ret;
b505183b XL	107	}
	108
	109	static void fsl_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	110	{
	111	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	112
db6c51ab	113	if (fpc->soc->has_enable_bits) {
	114	mutex_lock(&fpc->lock);
	115	regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
	116	0);
	117	mutex_unlock(&fpc->lock);
	118	}
	119
82a9c55a	120	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	121	}
b505183b XL	122
3479bbd1 PH	123	static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
3479bbd1 PH	124	unsigned int ticks)
b505183b	125	{
3479bbd1 PH	126	unsigned long rate;
	127	unsigned long long exval;
	128
	129	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
	130	exval = ticks;
	131	exval *= 1000000000UL;
	132	do_div(exval, rate >> fpc->period.clk_ps);
	133	return exval;
b505183b XL	134	}
b505183b XL	135
3479bbd1 PH	136	static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
	137	unsigned int period_ns,
	138	enum fsl_pwm_clk index,
	139	struct fsl_pwm_periodcfg *periodcfg
	140	)
b505183b	141	{
3479bbd1 PH	142	unsigned long long c;
3479bbd1 PH	143	unsigned int ps;
b505183b	144
3479bbd1	145	c = clk_get_rate(fpc->clk[index]);
b505183b XL	146	c = c * period_ns;
	147	do_div(c, 1000000000UL);
	148
3479bbd1 PH	149	if (c == 0)
3479bbd1 PH	150	return false;
b505183b	151
3479bbd1 PH	152	for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
	153	if (c <= 0x10000) {
	154	periodcfg->clk_select = index;
	155	periodcfg->clk_ps = ps;
	156	periodcfg->mod_period = c - 1;
	157	return true;
	158	}
b505183b	159	}
3479bbd1	160	return false;
b505183b XL	161	}
b505183b XL	162
3479bbd1 PH	163	static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
	164	unsigned int period_ns,
	165	struct fsl_pwm_periodcfg *periodcfg)
b505183b XL	166	{
b505183b XL	167	enum fsl_pwm_clk m0, m1;
3479bbd1 PH	168	unsigned long fix_rate, ext_rate;
3479bbd1 PH	169	bool ret;
b505183b	170
3479bbd1 PH	171	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
	172	periodcfg);
	173	if (ret)
	174	return true;
b505183b XL	175
	176	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
	177	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
	178
	179	if (fix_rate > ext_rate) {
	180	m0 = FSL_PWM_CLK_FIX;
	181	m1 = FSL_PWM_CLK_EXT;
	182	} else {
	183	m0 = FSL_PWM_CLK_EXT;
	184	m1 = FSL_PWM_CLK_FIX;
	185	}
	186
3479bbd1 PH	187	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
	188	if (ret)
	189	return true;
b505183b	190
3479bbd1	191	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
b505183b XL	192	}
b505183b XL	193
3479bbd1 PH	194	static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
3479bbd1 PH	195	unsigned int duty_ns)
b505183b	196	{
42fa98a9	197	unsigned long long duty;
b505183b	198
3479bbd1 PH	199	unsigned int period = fpc->period.mod_period + 1;
	200	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
	201
	202	duty = (unsigned long long)duty_ns * period;
b505183b XL	203	do_div(duty, period_ns);
b505183b XL	204
3479bbd1	205	return (unsigned int)duty;
b505183b XL	206	}
b505183b XL	207
3479bbd1 PH	208	static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
3479bbd1 PH	209	struct pwm_device *pwm)
b505183b	210	{
3479bbd1	211	u32 val;
b505183b	212
3479bbd1 PH	213	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	214	if (~val & 0xFF)
	215	return true;
	216	else
	217	return false;
	218	}
	219
	220	static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
	221	struct pwm_device *pwm)
	222	{
	223	u32 val;
	224
	225	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	226	if (~(val \| BIT(pwm->hwpwm)) & 0xFF)
	227	return true;
	228	else
	229	return false;
	230	}
	231
	232	static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
	233	struct pwm_device *pwm,
	234	struct pwm_state *newstate)
	235	{
	236	unsigned int duty;
	237	u32 reg_polarity;
b505183b	238
3479bbd1 PH	239	struct fsl_pwm_periodcfg periodcfg;
	240	bool do_write_period = false;
	241
	242	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
	243	dev_err(fpc->chip.dev, "failed to calculate new period\n");
	244	return -EINVAL;
	245	}
	246
	247	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
	248	do_write_period = true;
b505183b XL	249	/*
b505183b XL	250	* The Freescale FTM controller supports only a single period for
3479bbd1 PH	251	* all PWM channels, therefore verify if the newly computed period
	252	* is different than the current period being used. In such case
	253	* we allow to change the period only if no other pwm is running.
b505183b	254	*/
3479bbd1 PH	255	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
	256	if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
	257	dev_err(fpc->chip.dev,
	258	"Cannot change period for PWM %u, disable other PWMs first\n",
	259	pwm->hwpwm);
	260	return -EBUSY;
b505183b	261	}
3479bbd1 PH	262	if (fpc->period.clk_select != periodcfg.clk_select) {
	263	int ret;
	264	enum fsl_pwm_clk oldclk = fpc->period.clk_select;
	265	enum fsl_pwm_clk newclk = periodcfg.clk_select;
	266
	267	ret = clk_prepare_enable(fpc->clk[newclk]);
	268	if (ret)
	269	return ret;
	270	clk_disable_unprepare(fpc->clk[oldclk]);
	271	}
	272	do_write_period = true;
	273	}
b505183b	274
a2a28229 PH	275	ftm_clear_write_protection(fpc);
a2a28229 PH	276
3479bbd1 PH	277	if (do_write_period) {
	278	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
	279	FTM_SC_CLK(periodcfg.clk_select));
42fa98a9	280	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
3479bbd1 PH	281	periodcfg.clk_ps);
3479bbd1 PH	282	regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
b505183b	283
3479bbd1	284	fpc->period = periodcfg;
b505183b XL	285	}
b505183b XL	286
3479bbd1	287	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
b505183b	288
42fa98a9 XL	289	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
	290	FTM_CSC_MSB \| FTM_CSC_ELSB);
	291	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
b505183b	292
3479bbd1 PH	293	reg_polarity = 0;
	294	if (newstate->polarity == PWM_POLARITY_INVERSED)
	295	reg_polarity = BIT(pwm->hwpwm);
b505183b	296
3479bbd1	297	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
b505183b	298
3479bbd1 PH	299	newstate->period = fsl_pwm_ticks_to_ns(fpc,
	300	fpc->period.mod_period + 1);
	301	newstate->duty_cycle = fsl_pwm_ticks_to_ns(fpc, duty);
b505183b	302
a2a28229 PH	303	ftm_set_write_protection(fpc);
a2a28229 PH	304
b505183b XL	305	return 0;
	306	}
	307
3479bbd1 PH	308	static int fsl_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
3479bbd1 PH	309	struct pwm_state *newstate)
b505183b XL	310	{
b505183b XL	311	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
3479bbd1 PH	312	struct pwm_state *oldstate = &pwm->state;
3479bbd1 PH	313	int ret = 0;
b505183b	314
3479bbd1 PH	315	/*
	316	* oldstate to newstate : action
	317	*
	318	* disabled to disabled : ignore
	319	* enabled to disabled : disable
	320	* enabled to enabled : update settings
	321	* disabled to enabled : update settings + enable
	322	*/
b505183b	323
3479bbd1	324	mutex_lock(&fpc->lock);
b505183b	325
3479bbd1 PH	326	if (!newstate->enabled) {
	327	if (oldstate->enabled) {
	328	regmap_update_bits(fpc->regmap, FTM_OUTMASK,
	329	BIT(pwm->hwpwm), BIT(pwm->hwpwm));
	330	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
	331	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	332	}
b505183b	333
3479bbd1 PH	334	goto end_mutex;
3479bbd1 PH	335	}
b505183b	336
3479bbd1 PH	337	ret = fsl_pwm_apply_config(fpc, pwm, newstate);
	338	if (ret)
	339	goto end_mutex;
	340
	341	/* check if need to enable */
	342	if (!oldstate->enabled) {
	343	ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
	344	if (ret)
	345	return ret;
	346
	347	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	348	if (ret) {
	349	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	350	return ret;
	351	}
b505183b	352
3479bbd1 PH	353	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
	354	0);
	355	}
b505183b	356
3479bbd1	357	end_mutex:
b505183b	358	mutex_unlock(&fpc->lock);
3479bbd1	359	return ret;
b505183b XL	360	}
	361
	362	static const struct pwm_ops fsl_pwm_ops = {
	363	.request = fsl_pwm_request,
	364	.free = fsl_pwm_free,
3479bbd1	365	.apply = fsl_pwm_apply,
b505183b XL	366	.owner = THIS_MODULE,
	367	};
	368
	369	static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
	370	{
	371	int ret;
	372
82a9c55a	373	ret = clk_prepare_enable(fpc->ipg_clk);
b505183b XL	374	if (ret)
	375	return ret;
	376
42fa98a9 XL	377	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	378	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	379	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
b505183b	380
82a9c55a	381	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	382
	383	return 0;
	384	}
	385
49599cf6 XL	386	static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
	387	{
	388	switch (reg) {
a2a28229 PH	389	case FTM_FMS:
a2a28229 PH	390	case FTM_MODE:
49599cf6 XL	391	case FTM_CNT:
	392	return true;
	393	}
	394	return false;
	395	}
	396
42fa98a9 XL	397	static const struct regmap_config fsl_pwm_regmap_config = {
	398	.reg_bits = 32,
	399	.reg_stride = 4,
	400	.val_bits = 32,
	401
	402	.max_register = FTM_PWMLOAD,
49599cf6	403	.volatile_reg = fsl_pwm_volatile_reg,
ad06fdee	404	.cache_type = REGCACHE_FLAT,
42fa98a9 XL	405	};
42fa98a9 XL	406
b505183b XL	407	static int fsl_pwm_probe(struct platform_device *pdev)
	408	{
	409	struct fsl_pwm_chip *fpc;
	410	struct resource *res;
42fa98a9	411	void __iomem *base;
b505183b XL	412	int ret;
	413
	414	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
	415	if (!fpc)
	416	return -ENOMEM;
	417
	418	mutex_init(&fpc->lock);
	419
db6c51ab	420	fpc->soc = of_device_get_match_data(&pdev->dev);
b505183b XL	421	fpc->chip.dev = &pdev->dev;
	422
	423	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
42fa98a9 XL	424	base = devm_ioremap_resource(&pdev->dev, res);
	425	if (IS_ERR(base))
	426	return PTR_ERR(base);
	427
97d0b42e	428	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
42fa98a9 XL	429	&fsl_pwm_regmap_config);
	430	if (IS_ERR(fpc->regmap)) {
	431	dev_err(&pdev->dev, "regmap init failed\n");
	432	return PTR_ERR(fpc->regmap);
	433	}
b505183b XL	434
	435	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	436	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
	437	dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
	438	return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	439	}
	440
	441	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
	442	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
	443	return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
	444
	445	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
	446	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
	447	return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
	448
	449	fpc->clk[FSL_PWM_CLK_CNTEN] =
	450	devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
	451	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
	452	return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
	453
82a9c55a	454	/*
	455	* ipg_clk is the interface clock for the IP. If not provided, use the
	456	* ftm_sys clock as the default.
	457	*/
	458	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	459	if (IS_ERR(fpc->ipg_clk))
	460	fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
	461
	462
b505183b XL	463	fpc->chip.ops = &fsl_pwm_ops;
	464	fpc->chip.of_xlate = of_pwm_xlate_with_flags;
	465	fpc->chip.of_pwm_n_cells = 3;
	466	fpc->chip.base = -1;
	467	fpc->chip.npwm = 8;
	468
	469	ret = pwmchip_add(&fpc->chip);
	470	if (ret < 0) {
	471	dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
	472	return ret;
	473	}
	474
	475	platform_set_drvdata(pdev, fpc);
	476
	477	return fsl_pwm_init(fpc);
	478	}
	479
	480	static int fsl_pwm_remove(struct platform_device *pdev)
	481	{
	482	struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);
	483
	484	return pwmchip_remove(&fpc->chip);
	485	}
	486
97d0b42e XL	487	#ifdef CONFIG_PM_SLEEP
	488	static int fsl_pwm_suspend(struct device *dev)
	489	{
	490	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
816aec23	491	int i;
97d0b42e XL	492
	493	regcache_cache_only(fpc->regmap, true);
	494	regcache_mark_dirty(fpc->regmap);
	495
816aec23 SA	496	for (i = 0; i < fpc->chip.npwm; i++) {
	497	struct pwm_device *pwm = &fpc->chip.pwms[i];
	498
	499	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	500	continue;
	501
82a9c55a	502	clk_disable_unprepare(fpc->ipg_clk);
816aec23 SA	503
	504	if (!pwm_is_enabled(pwm))
	505	continue;
	506
97d0b42e	507	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
3479bbd1	508	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
97d0b42e XL	509	}
	510
	511	return 0;
	512	}
	513
	514	static int fsl_pwm_resume(struct device *dev)
	515	{
	516	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
816aec23 SA	517	int i;
	518
	519	for (i = 0; i < fpc->chip.npwm; i++) {
	520	struct pwm_device *pwm = &fpc->chip.pwms[i];
	521
	522	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	523	continue;
97d0b42e	524
82a9c55a	525	clk_prepare_enable(fpc->ipg_clk);
816aec23 SA	526
	527	if (!pwm_is_enabled(pwm))
	528	continue;
	529
3479bbd1	530	clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
97d0b42e XL	531	clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	532	}
	533
	534	/* restore all registers from cache */
	535	regcache_cache_only(fpc->regmap, false);
	536	regcache_sync(fpc->regmap);
	537
	538	return 0;
	539	}
	540	#endif
	541
	542	static const struct dev_pm_ops fsl_pwm_pm_ops = {
	543	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
	544	};
	545
db6c51ab	546	static const struct fsl_ftm_soc vf610_ftm_pwm = {
	547	.has_enable_bits = false,
	548	};
	549
2c4f2e32	550	static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	551	.has_enable_bits = true,
	552	};
	553
b505183b	554	static const struct of_device_id fsl_pwm_dt_ids[] = {
db6c51ab	555	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
2c4f2e32	556	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
b505183b XL	557	{ /* sentinel */ }
	558	};
	559	MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
	560
	561	static struct platform_driver fsl_pwm_driver = {
	562	.driver = {
	563	.name = "fsl-ftm-pwm",
	564	.of_match_table = fsl_pwm_dt_ids,
97d0b42e	565	.pm = &fsl_pwm_pm_ops,
b505183b XL	566	},
	567	.probe = fsl_pwm_probe,
	568	.remove = fsl_pwm_remove,
	569	};
	570	module_platform_driver(fsl_pwm_driver);
	571
	572	MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
	573	MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
	574	MODULE_ALIAS("platform:fsl-ftm-pwm");
	575	MODULE_LICENSE("GPL");