[linux-2.6-block.git] / drivers / pwm / pwm-fsl-ftm.c

/*
 *  Freescale FlexTimer Module (FTM) PWM Driver
 *
 *  Copyright 2012-2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/fsl/ftm.h>

#define FTM_SC_CLK(c)	(((c) + 1) << FTM_SC_CLK_MASK_SHIFT)

enum fsl_pwm_clk {
	FSL_PWM_CLK_SYS,
	FSL_PWM_CLK_FIX,
	FSL_PWM_CLK_EXT,
	FSL_PWM_CLK_CNTEN,
	FSL_PWM_CLK_MAX
};

struct fsl_ftm_soc {
	bool has_enable_bits;
};

struct fsl_pwm_chip {
	struct pwm_chip chip;

	struct mutex lock;

	unsigned int cnt_select;
	unsigned int clk_ps;

	struct regmap *regmap;

	int period_ns;

	struct clk *ipg_clk;
	struct clk *clk[FSL_PWM_CLK_MAX];

	const struct fsl_ftm_soc *soc;
};

static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct fsl_pwm_chip, chip);
}

static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	int ret;
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (!ret && fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
				   BIT(pwm->hwpwm + 16));
		mutex_unlock(&fpc->lock);
	}

	return ret;
}

static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	if (fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
				   0);
		mutex_unlock(&fpc->lock);
	}

	clk_disable_unprepare(fpc->ipg_clk);
}

static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc,
					enum fsl_pwm_clk index)
{
	unsigned long sys_rate, cnt_rate;
	unsigned long long ratio;

	sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]);
	if (!sys_rate)
		return -EINVAL;

	cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]);
	if (!cnt_rate)
		return -EINVAL;

	switch (index) {
	case FSL_PWM_CLK_SYS:
		fpc->clk_ps = 1;
		break;
	case FSL_PWM_CLK_FIX:
		ratio = 2 * cnt_rate - 1;
		do_div(ratio, sys_rate);
		fpc->clk_ps = ratio;
		break;
	case FSL_PWM_CLK_EXT:
		ratio = 4 * cnt_rate - 1;
		do_div(ratio, sys_rate);
		fpc->clk_ps = ratio;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc,
					      unsigned long period_ns)
{
	unsigned long long c, c0;

	c = clk_get_rate(fpc->clk[fpc->cnt_select]);
	c = c * period_ns;
	do_div(c, 1000000000UL);

	do {
		c0 = c;
		do_div(c0, (1 << fpc->clk_ps));
		if (c0 <= 0xFFFF)
			return (unsigned long)c0;
	} while (++fpc->clk_ps < 8);

	return 0;
}

static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc,
						     unsigned long period_ns,
						     enum fsl_pwm_clk index)
{
	int ret;

	ret = fsl_pwm_calculate_default_ps(fpc, index);
	if (ret) {
		dev_err(fpc->chip.dev,
			"failed to calculate default prescaler: %d\n",
			ret);
		return 0;
	}

	return fsl_pwm_calculate_cycles(fpc, period_ns);
}

static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
					      unsigned long period_ns)
{
	enum fsl_pwm_clk m0, m1;
	unsigned long fix_rate, ext_rate, cycles;

	cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns,
			FSL_PWM_CLK_SYS);
	if (cycles) {
		fpc->cnt_select = FSL_PWM_CLK_SYS;
		return cycles;
	}

	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);

	if (fix_rate > ext_rate) {
		m0 = FSL_PWM_CLK_FIX;
		m1 = FSL_PWM_CLK_EXT;
	} else {
		m0 = FSL_PWM_CLK_EXT;
		m1 = FSL_PWM_CLK_FIX;
	}

	cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0);
	if (cycles) {
		fpc->cnt_select = m0;
		return cycles;
	}

	fpc->cnt_select = m1;

	return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1);
}

static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
					    unsigned long period_ns,
					    unsigned long duty_ns)
{
	unsigned long long duty;
	u32 val;

	regmap_read(fpc->regmap, FTM_MOD, &val);
	duty = (unsigned long long)duty_ns * (val + 1);
	do_div(duty, period_ns);

	return (unsigned long)duty;
}

static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	u32 period, duty;

	mutex_lock(&fpc->lock);

	/*
	 * The Freescale FTM controller supports only a single period for
	 * all PWM channels, therefore incompatible changes need to be
	 * refused.
	 */
	if (fpc->period_ns && fpc->period_ns != period_ns) {
		dev_err(fpc->chip.dev,
			"conflicting period requested for PWM %u\n",
			pwm->hwpwm);
		mutex_unlock(&fpc->lock);
		return -EBUSY;
	}

	if (!fpc->period_ns && duty_ns) {
		period = fsl_pwm_calculate_period(fpc, period_ns);
		if (!period) {
			dev_err(fpc->chip.dev, "failed to calculate period\n");
			mutex_unlock(&fpc->lock);
			return -EINVAL;
		}

		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
				   fpc->clk_ps);
		regmap_write(fpc->regmap, FTM_MOD, period - 1);

		fpc->period_ns = period_ns;
	}

	mutex_unlock(&fpc->lock);

	duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns);

	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
		     FTM_CSC_MSB | FTM_CSC_ELSB);
	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);

	return 0;
}

static int fsl_pwm_set_polarity(struct pwm_chip *chip,
				struct pwm_device *pwm,
				enum pwm_polarity polarity)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	u32 val;

	regmap_read(fpc->regmap, FTM_POL, &val);

	if (polarity == PWM_POLARITY_INVERSED)
		val |= BIT(pwm->hwpwm);
	else
		val &= ~BIT(pwm->hwpwm);

	regmap_write(fpc->regmap, FTM_POL, val);

	return 0;
}

static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)
{
	int ret;

	/* select counter clock source */
	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
			   FTM_SC_CLK(fpc->cnt_select));

	ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]);
	if (ret)
		return ret;

	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	if (ret) {
		clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
		return ret;
	}

	return 0;
}

static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	int ret;

	mutex_lock(&fpc->lock);
	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0);

	ret = fsl_counter_clock_enable(fpc);
	mutex_unlock(&fpc->lock);

	return ret;
}

static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	u32 val;

	mutex_lock(&fpc->lock);
	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
			   BIT(pwm->hwpwm));

	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
	clk_disable_unprepare(fpc->clk[fpc->cnt_select]);

	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	if ((val & 0xFF) == 0xFF)
		fpc->period_ns = 0;

	mutex_unlock(&fpc->lock);
}

static const struct pwm_ops fsl_pwm_ops = {
	.request = fsl_pwm_request,
	.free = fsl_pwm_free,
	.config = fsl_pwm_config,
	.set_polarity = fsl_pwm_set_polarity,
	.enable = fsl_pwm_enable,
	.disable = fsl_pwm_disable,
	.owner = THIS_MODULE,
};

static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
{
	int ret;

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (ret)
		return ret;

	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);

	clk_disable_unprepare(fpc->ipg_clk);

	return 0;
}

static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case FTM_CNT:
		return true;
	}
	return false;
}

static const struct regmap_config fsl_pwm_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,

	.max_register = FTM_PWMLOAD,
	.volatile_reg = fsl_pwm_volatile_reg,
	.cache_type = REGCACHE_FLAT,
};

static int fsl_pwm_probe(struct platform_device *pdev)
{
	struct fsl_pwm_chip *fpc;
	struct resource *res;
	void __iomem *base;
	int ret;

	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
	if (!fpc)
		return -ENOMEM;

	mutex_init(&fpc->lock);

	fpc->soc = of_device_get_match_data(&pdev->dev);
	fpc->chip.dev = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
						&fsl_pwm_regmap_config);
	if (IS_ERR(fpc->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(fpc->regmap);
	}

	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
		dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	}

	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);

	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);

	fpc->clk[FSL_PWM_CLK_CNTEN] =
				devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);

	/*
	 * ipg_clk is the interface clock for the IP. If not provided, use the
	 * ftm_sys clock as the default.
	 */
	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(fpc->ipg_clk))
		fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];


	fpc->chip.ops = &fsl_pwm_ops;
	fpc->chip.of_xlate = of_pwm_xlate_with_flags;
	fpc->chip.of_pwm_n_cells = 3;
	fpc->chip.base = -1;
	fpc->chip.npwm = 8;

	ret = pwmchip_add(&fpc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, fpc);

	return fsl_pwm_init(fpc);
}

static int fsl_pwm_remove(struct platform_device *pdev)
{
	struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);

	return pwmchip_remove(&fpc->chip);
}

#ifdef CONFIG_PM_SLEEP
static int fsl_pwm_suspend(struct device *dev)
{
	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
	int i;

	regcache_cache_only(fpc->regmap, true);
	regcache_mark_dirty(fpc->regmap);

	for (i = 0; i < fpc->chip.npwm; i++) {
		struct pwm_device *pwm = &fpc->chip.pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_disable_unprepare(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
		clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
	}

	return 0;
}

static int fsl_pwm_resume(struct device *dev)
{
	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
	int i;

	for (i = 0; i < fpc->chip.npwm; i++) {
		struct pwm_device *pwm = &fpc->chip.pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_prepare_enable(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_prepare_enable(fpc->clk[fpc->cnt_select]);
		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	}

	/* restore all registers from cache */
	regcache_cache_only(fpc->regmap, false);
	regcache_sync(fpc->regmap);

	return 0;
}
#endif

static const struct dev_pm_ops fsl_pwm_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
};

static const struct fsl_ftm_soc vf610_ftm_pwm = {
	.has_enable_bits = false,
};

static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	.has_enable_bits = true,
};

static const struct of_device_id fsl_pwm_dt_ids[] = {
	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);

static struct platform_driver fsl_pwm_driver = {
	.driver = {
		.name = "fsl-ftm-pwm",
		.of_match_table = fsl_pwm_dt_ids,
		.pm = &fsl_pwm_pm_ops,
	},
	.probe = fsl_pwm_probe,
	.remove = fsl_pwm_remove,
};
module_platform_driver(fsl_pwm_driver);

MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
MODULE_ALIAS("platform:fsl-ftm-pwm");
MODULE_LICENSE("GPL");
Commit	Line	Data
b505183b XL	1	/*
	2	* Freescale FlexTimer Module (FTM) PWM Driver
	3	*
	4	* Copyright 2012-2013 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/err.h>
	14	#include <linux/io.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/mutex.h>
	18	#include <linux/of_address.h>
db6c51ab	19	#include <linux/of_device.h>
b505183b	20	#include <linux/platform_device.h>
97d0b42e	21	#include <linux/pm.h>
b505183b	22	#include <linux/pwm.h>
42fa98a9	23	#include <linux/regmap.h>
b505183b	24	#include <linux/slab.h>
e590eb40	25	#include <linux/fsl/ftm.h>
b505183b	26
cd6d92d2	27	#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
b505183b XL	28
	29	enum fsl_pwm_clk {
	30	FSL_PWM_CLK_SYS,
	31	FSL_PWM_CLK_FIX,
	32	FSL_PWM_CLK_EXT,
	33	FSL_PWM_CLK_CNTEN,
	34	FSL_PWM_CLK_MAX
	35	};
	36
db6c51ab	37	struct fsl_ftm_soc {
	38	bool has_enable_bits;
	39	};
	40
b505183b XL	41	struct fsl_pwm_chip {
	42	struct pwm_chip chip;
	43
	44	struct mutex lock;
	45
b505183b XL	46	unsigned int cnt_select;
	47	unsigned int clk_ps;
	48
42fa98a9	49	struct regmap *regmap;
b505183b XL	50
	51	int period_ns;
	52
82a9c55a	53	struct clk *ipg_clk;
b505183b	54	struct clk *clk[FSL_PWM_CLK_MAX];
db6c51ab	55
db6c51ab	56	const struct fsl_ftm_soc *soc;
b505183b XL	57	};
	58
	59	static inline struct fsl_pwm_chip to_fsl_chip(struct pwm_chip chip)
	60	{
	61	return container_of(chip, struct fsl_pwm_chip, chip);
	62	}
	63
	64	static int fsl_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	65	{
db6c51ab	66	int ret;
b505183b XL	67	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
b505183b XL	68
db6c51ab	69	ret = clk_prepare_enable(fpc->ipg_clk);
	70	if (!ret && fpc->soc->has_enable_bits) {
	71	mutex_lock(&fpc->lock);
	72	regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
	73	BIT(pwm->hwpwm + 16));
	74	mutex_unlock(&fpc->lock);
	75	}
	76
	77	return ret;
b505183b XL	78	}
	79
	80	static void fsl_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	81	{
	82	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	83
db6c51ab	84	if (fpc->soc->has_enable_bits) {
	85	mutex_lock(&fpc->lock);
	86	regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
	87	0);
	88	mutex_unlock(&fpc->lock);
	89	}
	90
82a9c55a	91	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	92	}
	93
	94	static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc,
	95	enum fsl_pwm_clk index)
	96	{
	97	unsigned long sys_rate, cnt_rate;
	98	unsigned long long ratio;
	99
	100	sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]);
	101	if (!sys_rate)
	102	return -EINVAL;
	103
	104	cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]);
	105	if (!cnt_rate)
	106	return -EINVAL;
	107
	108	switch (index) {
	109	case FSL_PWM_CLK_SYS:
	110	fpc->clk_ps = 1;
	111	break;
	112	case FSL_PWM_CLK_FIX:
	113	ratio = 2 * cnt_rate - 1;
	114	do_div(ratio, sys_rate);
	115	fpc->clk_ps = ratio;
	116	break;
	117	case FSL_PWM_CLK_EXT:
	118	ratio = 4 * cnt_rate - 1;
	119	do_div(ratio, sys_rate);
	120	fpc->clk_ps = ratio;
	121	break;
	122	default:
	123	return -EINVAL;
	124	}
	125
	126	return 0;
	127	}
	128
	129	static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc,
	130	unsigned long period_ns)
	131	{
	132	unsigned long long c, c0;
	133
	134	c = clk_get_rate(fpc->clk[fpc->cnt_select]);
	135	c = c * period_ns;
	136	do_div(c, 1000000000UL);
	137
	138	do {
	139	c0 = c;
	140	do_div(c0, (1 << fpc->clk_ps));
	141	if (c0 <= 0xFFFF)
	142	return (unsigned long)c0;
	143	} while (++fpc->clk_ps < 8);
	144
	145	return 0;
	146	}
	147
	148	static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc,
	149	unsigned long period_ns,
	150	enum fsl_pwm_clk index)
	151	{
	152	int ret;
	153
	154	ret = fsl_pwm_calculate_default_ps(fpc, index);
	155	if (ret) {
156	dev_err(fpc->chip.dev,
157	"failed to calculate default prescaler: %d\n",
158	ret);
159	return 0;
160	}
161
162	return fsl_pwm_calculate_cycles(fpc, period_ns);
163	}
164
165	static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
166	unsigned long period_ns)
167	{
168	enum fsl_pwm_clk m0, m1;
169	unsigned long fix_rate, ext_rate, cycles;
170
171	cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns,
172	FSL_PWM_CLK_SYS);
173	if (cycles) {
174	fpc->cnt_select = FSL_PWM_CLK_SYS;
175	return cycles;
176	}
177
178	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
179	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
180
181	if (fix_rate > ext_rate) {
182	m0 = FSL_PWM_CLK_FIX;
183	m1 = FSL_PWM_CLK_EXT;
184	} else {
185	m0 = FSL_PWM_CLK_EXT;
186	m1 = FSL_PWM_CLK_FIX;
187	}
188
189	cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0);
190	if (cycles) {
191	fpc->cnt_select = m0;
192	return cycles;
193	}
194
195	fpc->cnt_select = m1;
196
197	return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1);
198	}
199
200	static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
201	unsigned long period_ns,
202	unsigned long duty_ns)
203	{
42fa98a9 XL	204	unsigned long long duty;
42fa98a9 XL	205	u32 val;
b505183b	206
42fa98a9 XL	207	regmap_read(fpc->regmap, FTM_MOD, &val);
42fa98a9 XL	208	duty = (unsigned long long)duty_ns * (val + 1);
b505183b XL	209	do_div(duty, period_ns);
	210
	211	return (unsigned long)duty;
	212	}
	213
	214	static int fsl_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	215	int duty_ns, int period_ns)
	216	{
	217	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
42fa98a9	218	u32 period, duty;
b505183b XL	219
	220	mutex_lock(&fpc->lock);
	221
	222	/*
	223	* The Freescale FTM controller supports only a single period for
	224	* all PWM channels, therefore incompatible changes need to be
	225	* refused.
	226	*/
	227	if (fpc->period_ns && fpc->period_ns != period_ns) {
	228	dev_err(fpc->chip.dev,
	229	"conflicting period requested for PWM %u\n",
	230	pwm->hwpwm);
	231	mutex_unlock(&fpc->lock);
	232	return -EBUSY;
	233	}
	234
	235	if (!fpc->period_ns && duty_ns) {
	236	period = fsl_pwm_calculate_period(fpc, period_ns);
	237	if (!period) {
	238	dev_err(fpc->chip.dev, "failed to calculate period\n");
	239	mutex_unlock(&fpc->lock);
	240	return -EINVAL;
	241	}
	242
42fa98a9 XL	243	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
	244	fpc->clk_ps);
	245	regmap_write(fpc->regmap, FTM_MOD, period - 1);
b505183b XL	246
	247	fpc->period_ns = period_ns;
	248	}
	249
	250	mutex_unlock(&fpc->lock);
	251
	252	duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns);
	253
42fa98a9 XL	254	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
	255	FTM_CSC_MSB \| FTM_CSC_ELSB);
	256	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
b505183b XL	257
	258	return 0;
	259	}
	260
	261	static int fsl_pwm_set_polarity(struct pwm_chip *chip,
	262	struct pwm_device *pwm,
	263	enum pwm_polarity polarity)
	264	{
	265	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	266	u32 val;
	267
42fa98a9	268	regmap_read(fpc->regmap, FTM_POL, &val);
b505183b XL	269
	270	if (polarity == PWM_POLARITY_INVERSED)
	271	val \|= BIT(pwm->hwpwm);
	272	else
	273	val &= ~BIT(pwm->hwpwm);
	274
42fa98a9	275	regmap_write(fpc->regmap, FTM_POL, val);
b505183b XL	276
	277	return 0;
	278	}
	279
	280	static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)
	281	{
b505183b XL	282	int ret;
b505183b XL	283
b505183b	284	/* select counter clock source */
42fa98a9 XL	285	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
42fa98a9 XL	286	FTM_SC_CLK(fpc->cnt_select));
b505183b XL	287
	288	ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]);
	289	if (ret)
	290	return ret;
	291
	292	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	293	if (ret) {
	294	clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
	295	return ret;
	296	}
	297
b505183b XL	298	return 0;
	299	}
	300
	301	static int fsl_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	302	{
	303	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
b505183b XL	304	int ret;
	305
	306	mutex_lock(&fpc->lock);
42fa98a9	307	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0);
b505183b XL	308
	309	ret = fsl_counter_clock_enable(fpc);
	310	mutex_unlock(&fpc->lock);
	311
	312	return ret;
	313	}
	314
b505183b XL	315	static void fsl_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	316	{
	317	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	318	u32 val;
	319
	320	mutex_lock(&fpc->lock);
42fa98a9 XL	321	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
42fa98a9 XL	322	BIT(pwm->hwpwm));
b505183b	323
816aec23 SA	324	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
816aec23 SA	325	clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
b505183b	326
42fa98a9	327	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
b505183b XL	328	if ((val & 0xFF) == 0xFF)
	329	fpc->period_ns = 0;
	330
	331	mutex_unlock(&fpc->lock);
	332	}
	333
	334	static const struct pwm_ops fsl_pwm_ops = {
	335	.request = fsl_pwm_request,
	336	.free = fsl_pwm_free,
	337	.config = fsl_pwm_config,
	338	.set_polarity = fsl_pwm_set_polarity,
	339	.enable = fsl_pwm_enable,
	340	.disable = fsl_pwm_disable,
	341	.owner = THIS_MODULE,
	342	};
	343
	344	static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
	345	{
	346	int ret;
	347
82a9c55a	348	ret = clk_prepare_enable(fpc->ipg_clk);
b505183b XL	349	if (ret)
	350	return ret;
	351
42fa98a9 XL	352	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	353	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	354	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
b505183b	355
82a9c55a	356	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	357
	358	return 0;
	359	}
	360
49599cf6 XL	361	static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
	362	{
	363	switch (reg) {
	364	case FTM_CNT:
	365	return true;
	366	}
	367	return false;
	368	}
	369
42fa98a9 XL	370	static const struct regmap_config fsl_pwm_regmap_config = {
	371	.reg_bits = 32,
	372	.reg_stride = 4,
	373	.val_bits = 32,
	374
	375	.max_register = FTM_PWMLOAD,
49599cf6	376	.volatile_reg = fsl_pwm_volatile_reg,
ad06fdee	377	.cache_type = REGCACHE_FLAT,
42fa98a9 XL	378	};
42fa98a9 XL	379
b505183b XL	380	static int fsl_pwm_probe(struct platform_device *pdev)
	381	{
	382	struct fsl_pwm_chip *fpc;
	383	struct resource *res;
42fa98a9	384	void __iomem *base;
b505183b XL	385	int ret;
	386
	387	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
	388	if (!fpc)
	389	return -ENOMEM;
	390
	391	mutex_init(&fpc->lock);
	392
db6c51ab	393	fpc->soc = of_device_get_match_data(&pdev->dev);
b505183b XL	394	fpc->chip.dev = &pdev->dev;
	395
	396	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
42fa98a9 XL	397	base = devm_ioremap_resource(&pdev->dev, res);
	398	if (IS_ERR(base))
	399	return PTR_ERR(base);
	400
97d0b42e	401	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
42fa98a9 XL	402	&fsl_pwm_regmap_config);
	403	if (IS_ERR(fpc->regmap)) {
	404	dev_err(&pdev->dev, "regmap init failed\n");
	405	return PTR_ERR(fpc->regmap);
	406	}
b505183b XL	407
	408	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	409	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
	410	dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
	411	return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	412	}
	413
	414	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
	415	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
	416	return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
	417
	418	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
	419	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
	420	return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
	421
	422	fpc->clk[FSL_PWM_CLK_CNTEN] =
	423	devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
	424	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
	425	return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
	426
82a9c55a	427	/*
	428	* ipg_clk is the interface clock for the IP. If not provided, use the
	429	* ftm_sys clock as the default.
	430	*/
	431	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	432	if (IS_ERR(fpc->ipg_clk))
	433	fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
	434
	435
b505183b XL	436	fpc->chip.ops = &fsl_pwm_ops;
	437	fpc->chip.of_xlate = of_pwm_xlate_with_flags;
	438	fpc->chip.of_pwm_n_cells = 3;
	439	fpc->chip.base = -1;
	440	fpc->chip.npwm = 8;
	441
	442	ret = pwmchip_add(&fpc->chip);
	443	if (ret < 0) {
	444	dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
	445	return ret;
	446	}
	447
	448	platform_set_drvdata(pdev, fpc);
	449
	450	return fsl_pwm_init(fpc);
	451	}
	452
	453	static int fsl_pwm_remove(struct platform_device *pdev)
	454	{
	455	struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);
	456
	457	return pwmchip_remove(&fpc->chip);
	458	}
	459
97d0b42e XL	460	#ifdef CONFIG_PM_SLEEP
	461	static int fsl_pwm_suspend(struct device *dev)
	462	{
	463	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
816aec23	464	int i;
97d0b42e XL	465
	466	regcache_cache_only(fpc->regmap, true);
	467	regcache_mark_dirty(fpc->regmap);
	468
816aec23 SA	469	for (i = 0; i < fpc->chip.npwm; i++) {
	470	struct pwm_device *pwm = &fpc->chip.pwms[i];
	471
	472	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	473	continue;
	474
82a9c55a	475	clk_disable_unprepare(fpc->ipg_clk);
816aec23 SA	476
	477	if (!pwm_is_enabled(pwm))
	478	continue;
	479
97d0b42e XL	480	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
97d0b42e XL	481	clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
97d0b42e XL	482	}
	483
	484	return 0;
	485	}
	486
	487	static int fsl_pwm_resume(struct device *dev)
	488	{
	489	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
816aec23 SA	490	int i;
	491
	492	for (i = 0; i < fpc->chip.npwm; i++) {
	493	struct pwm_device *pwm = &fpc->chip.pwms[i];
	494
	495	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	496	continue;
97d0b42e	497
82a9c55a	498	clk_prepare_enable(fpc->ipg_clk);
816aec23 SA	499
	500	if (!pwm_is_enabled(pwm))
	501	continue;
	502
97d0b42e XL	503	clk_prepare_enable(fpc->clk[fpc->cnt_select]);
	504	clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	505	}
	506
	507	/* restore all registers from cache */
	508	regcache_cache_only(fpc->regmap, false);
	509	regcache_sync(fpc->regmap);
	510
	511	return 0;
	512	}
	513	#endif
	514
	515	static const struct dev_pm_ops fsl_pwm_pm_ops = {
	516	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
	517	};
	518
db6c51ab	519	static const struct fsl_ftm_soc vf610_ftm_pwm = {
	520	.has_enable_bits = false,
	521	};
	522
2c4f2e32	523	static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	524	.has_enable_bits = true,
	525	};
	526
b505183b	527	static const struct of_device_id fsl_pwm_dt_ids[] = {
db6c51ab	528	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
2c4f2e32	529	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
b505183b XL	530	{ /* sentinel */ }
	531	};
	532	MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
	533
	534	static struct platform_driver fsl_pwm_driver = {
	535	.driver = {
	536	.name = "fsl-ftm-pwm",
	537	.of_match_table = fsl_pwm_dt_ids,
97d0b42e	538	.pm = &fsl_pwm_pm_ops,
b505183b XL	539	},
	540	.probe = fsl_pwm_probe,
	541	.remove = fsl_pwm_remove,
	542	};
	543	module_platform_driver(fsl_pwm_driver);
	544
	545	MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
	546	MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
	547	MODULE_ALIAS("platform:fsl-ftm-pwm");
	548	MODULE_LICENSE("GPL");