[linux-block.git] / drivers / pwm / pwm-fsl-ftm.c

/*
 *  Freescale FlexTimer Module (FTM) PWM Driver
 *
 *  Copyright 2012-2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/fsl/ftm.h>

#define FTM_SC_CLK(c)	(((c) + 1) << FTM_SC_CLK_MASK_SHIFT)

enum fsl_pwm_clk {
	FSL_PWM_CLK_SYS,
	FSL_PWM_CLK_FIX,
	FSL_PWM_CLK_EXT,
	FSL_PWM_CLK_CNTEN,
	FSL_PWM_CLK_MAX
};

struct fsl_ftm_soc {
	bool has_enable_bits;
};

struct fsl_pwm_periodcfg {
	enum fsl_pwm_clk clk_select;
	unsigned int clk_ps;
	unsigned int mod_period;
};

struct fsl_pwm_chip {
	struct pwm_chip chip;
	struct mutex lock;
	struct regmap *regmap;

	/* This value is valid iff a pwm is running */
	struct fsl_pwm_periodcfg period;

	struct clk *ipg_clk;
	struct clk *clk[FSL_PWM_CLK_MAX];

	const struct fsl_ftm_soc *soc;
};

static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct fsl_pwm_chip, chip);
}

static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
					const struct fsl_pwm_periodcfg *b)
{
	if (a->clk_select != b->clk_select)
		return false;
	if (a->clk_ps != b->clk_ps)
		return false;
	if (a->mod_period != b->mod_period)
		return false;
	return true;
}

static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	int ret;
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (!ret && fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
				   BIT(pwm->hwpwm + 16));
		mutex_unlock(&fpc->lock);
	}

	return ret;
}

static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	if (fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
				   0);
		mutex_unlock(&fpc->lock);
	}

	clk_disable_unprepare(fpc->ipg_clk);
}

static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
					  unsigned int ticks)
{
	unsigned long rate;
	unsigned long long exval;

	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
	exval = ticks;
	exval *= 1000000000UL;
	do_div(exval, rate >> fpc->period.clk_ps);
	return exval;
}

static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
					 unsigned int period_ns,
					 enum fsl_pwm_clk index,
					 struct fsl_pwm_periodcfg *periodcfg
					 )
{
	unsigned long long c;
	unsigned int ps;

	c = clk_get_rate(fpc->clk[index]);
	c = c * period_ns;
	do_div(c, 1000000000UL);

	if (c == 0)
		return false;

	for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
		if (c <= 0x10000) {
			periodcfg->clk_select = index;
			periodcfg->clk_ps = ps;
			periodcfg->mod_period = c - 1;
			return true;
		}
	}
	return false;
}

static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
				     unsigned int period_ns,
				     struct fsl_pwm_periodcfg *periodcfg)
{
	enum fsl_pwm_clk m0, m1;
	unsigned long fix_rate, ext_rate;
	bool ret;

	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
					   periodcfg);
	if (ret)
		return true;

	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);

	if (fix_rate > ext_rate) {
		m0 = FSL_PWM_CLK_FIX;
		m1 = FSL_PWM_CLK_EXT;
	} else {
		m0 = FSL_PWM_CLK_EXT;
		m1 = FSL_PWM_CLK_FIX;
	}

	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
	if (ret)
		return true;

	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
}

static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
					   unsigned int duty_ns)
{
	unsigned long long duty;

	unsigned int period = fpc->period.mod_period + 1;
	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);

	duty = (unsigned long long)duty_ns * period;
	do_div(duty, period_ns);

	return (unsigned int)duty;
}

static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
				       struct pwm_device *pwm)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	if (~val & 0xFF)
		return true;
	else
		return false;
}

static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
					 struct pwm_device *pwm)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	if (~(val | BIT(pwm->hwpwm)) & 0xFF)
		return true;
	else
		return false;
}

static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
				struct pwm_device *pwm,
				struct pwm_state *newstate)
{
	unsigned int duty;
	u32 reg_polarity;

	struct fsl_pwm_periodcfg periodcfg;
	bool do_write_period = false;

	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
		dev_err(fpc->chip.dev, "failed to calculate new period\n");
		return -EINVAL;
	}

	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
		do_write_period = true;
	/*
	 * The Freescale FTM controller supports only a single period for
	 * all PWM channels, therefore verify if the newly computed period
	 * is different than the current period being used. In such case
	 * we allow to change the period only if no other pwm is running.
	 */
	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
		if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
			dev_err(fpc->chip.dev,
				"Cannot change period for PWM %u, disable other PWMs first\n",
				pwm->hwpwm);
			return -EBUSY;
		}
		if (fpc->period.clk_select != periodcfg.clk_select) {
			int ret;
			enum fsl_pwm_clk oldclk = fpc->period.clk_select;
			enum fsl_pwm_clk newclk = periodcfg.clk_select;

			ret = clk_prepare_enable(fpc->clk[newclk]);
			if (ret)
				return ret;
			clk_disable_unprepare(fpc->clk[oldclk]);
		}
		do_write_period = true;
	}

	if (do_write_period) {
		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
				   FTM_SC_CLK(periodcfg.clk_select));
		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
				   periodcfg.clk_ps);
		regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);

		fpc->period = periodcfg;
	}

	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);

	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
		     FTM_CSC_MSB | FTM_CSC_ELSB);
	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);

	reg_polarity = 0;
	if (newstate->polarity == PWM_POLARITY_INVERSED)
		reg_polarity = BIT(pwm->hwpwm);

	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);

	newstate->period = fsl_pwm_ticks_to_ns(fpc,
					       fpc->period.mod_period + 1);
	newstate->duty_cycle = fsl_pwm_ticks_to_ns(fpc, duty);

	return 0;
}

static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 struct pwm_state *newstate)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	struct pwm_state *oldstate = &pwm->state;
	int ret = 0;

	/*
	 * oldstate to newstate : action
	 *
	 * disabled to disabled : ignore
	 * enabled to disabled : disable
	 * enabled to enabled : update settings
	 * disabled to enabled : update settings + enable
	 */

	mutex_lock(&fpc->lock);

	if (!newstate->enabled) {
		if (oldstate->enabled) {
			regmap_update_bits(fpc->regmap, FTM_OUTMASK,
					   BIT(pwm->hwpwm), BIT(pwm->hwpwm));
			clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
		}

		goto end_mutex;
	}

	ret = fsl_pwm_apply_config(fpc, pwm, newstate);
	if (ret)
		goto end_mutex;

	/* check if need to enable */
	if (!oldstate->enabled) {
		ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
		if (ret)
			return ret;

		ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
		if (ret) {
			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
			return ret;
		}

		regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
				   0);
	}

end_mutex:
	mutex_unlock(&fpc->lock);
	return ret;
}

static const struct pwm_ops fsl_pwm_ops = {
	.request = fsl_pwm_request,
	.free = fsl_pwm_free,
	.apply = fsl_pwm_apply,
	.owner = THIS_MODULE,
};

static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
{
	int ret;

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (ret)
		return ret;

	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);

	clk_disable_unprepare(fpc->ipg_clk);

	return 0;
}

static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case FTM_CNT:
		return true;
	}
	return false;
}

static const struct regmap_config fsl_pwm_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,

	.max_register = FTM_PWMLOAD,
	.volatile_reg = fsl_pwm_volatile_reg,
	.cache_type = REGCACHE_FLAT,
};

static int fsl_pwm_probe(struct platform_device *pdev)
{
	struct fsl_pwm_chip *fpc;
	struct resource *res;
	void __iomem *base;
	int ret;

	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
	if (!fpc)
		return -ENOMEM;

	mutex_init(&fpc->lock);

	fpc->soc = of_device_get_match_data(&pdev->dev);
	fpc->chip.dev = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
						&fsl_pwm_regmap_config);
	if (IS_ERR(fpc->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(fpc->regmap);
	}

	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
		dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	}

	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);

	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);

	fpc->clk[FSL_PWM_CLK_CNTEN] =
				devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);

	/*
	 * ipg_clk is the interface clock for the IP. If not provided, use the
	 * ftm_sys clock as the default.
	 */
	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(fpc->ipg_clk))
		fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];


	fpc->chip.ops = &fsl_pwm_ops;
	fpc->chip.of_xlate = of_pwm_xlate_with_flags;
	fpc->chip.of_pwm_n_cells = 3;
	fpc->chip.base = -1;
	fpc->chip.npwm = 8;

	ret = pwmchip_add(&fpc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, fpc);

	return fsl_pwm_init(fpc);
}

static int fsl_pwm_remove(struct platform_device *pdev)
{
	struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);

	return pwmchip_remove(&fpc->chip);
}

#ifdef CONFIG_PM_SLEEP
static int fsl_pwm_suspend(struct device *dev)
{
	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
	int i;

	regcache_cache_only(fpc->regmap, true);
	regcache_mark_dirty(fpc->regmap);

	for (i = 0; i < fpc->chip.npwm; i++) {
		struct pwm_device *pwm = &fpc->chip.pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_disable_unprepare(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
		clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	}

	return 0;
}

static int fsl_pwm_resume(struct device *dev)
{
	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
	int i;

	for (i = 0; i < fpc->chip.npwm; i++) {
		struct pwm_device *pwm = &fpc->chip.pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_prepare_enable(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	}

	/* restore all registers from cache */
	regcache_cache_only(fpc->regmap, false);
	regcache_sync(fpc->regmap);

	return 0;
}
#endif

static const struct dev_pm_ops fsl_pwm_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
};

static const struct fsl_ftm_soc vf610_ftm_pwm = {
	.has_enable_bits = false,
};

static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	.has_enable_bits = true,
};

static const struct of_device_id fsl_pwm_dt_ids[] = {
	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);

static struct platform_driver fsl_pwm_driver = {
	.driver = {
		.name = "fsl-ftm-pwm",
		.of_match_table = fsl_pwm_dt_ids,
		.pm = &fsl_pwm_pm_ops,
	},
	.probe = fsl_pwm_probe,
	.remove = fsl_pwm_remove,
};
module_platform_driver(fsl_pwm_driver);

MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
MODULE_ALIAS("platform:fsl-ftm-pwm");
MODULE_LICENSE("GPL");
Commit	Line	Data
b505183b XL	1	/*
	2	* Freescale FlexTimer Module (FTM) PWM Driver
	3	*
	4	* Copyright 2012-2013 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/err.h>
	14	#include <linux/io.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/mutex.h>
	18	#include <linux/of_address.h>
db6c51ab	19	#include <linux/of_device.h>
b505183b	20	#include <linux/platform_device.h>
97d0b42e	21	#include <linux/pm.h>
b505183b	22	#include <linux/pwm.h>
42fa98a9	23	#include <linux/regmap.h>
b505183b	24	#include <linux/slab.h>
e590eb40	25	#include <linux/fsl/ftm.h>
b505183b	26
cd6d92d2	27	#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
b505183b XL	28
	29	enum fsl_pwm_clk {
	30	FSL_PWM_CLK_SYS,
	31	FSL_PWM_CLK_FIX,
	32	FSL_PWM_CLK_EXT,
	33	FSL_PWM_CLK_CNTEN,
	34	FSL_PWM_CLK_MAX
	35	};
	36
db6c51ab	37	struct fsl_ftm_soc {
	38	bool has_enable_bits;
	39	};
	40
3479bbd1 PH	41	struct fsl_pwm_periodcfg {
	42	enum fsl_pwm_clk clk_select;
	43	unsigned int clk_ps;
	44	unsigned int mod_period;
	45	};
	46
b505183b XL	47	struct fsl_pwm_chip {
b505183b XL	48	struct pwm_chip chip;
b505183b	49	struct mutex lock;
42fa98a9	50	struct regmap *regmap;
b505183b	51
3479bbd1 PH	52	/* This value is valid iff a pwm is running */
3479bbd1 PH	53	struct fsl_pwm_periodcfg period;
b505183b	54
82a9c55a	55	struct clk *ipg_clk;
b505183b	56	struct clk *clk[FSL_PWM_CLK_MAX];
db6c51ab	57
db6c51ab	58	const struct fsl_ftm_soc *soc;
b505183b XL	59	};
	60
	61	static inline struct fsl_pwm_chip to_fsl_chip(struct pwm_chip chip)
	62	{
	63	return container_of(chip, struct fsl_pwm_chip, chip);
	64	}
	65
3479bbd1 PH	66	static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
	67	const struct fsl_pwm_periodcfg *b)
	68	{
	69	if (a->clk_select != b->clk_select)
	70	return false;
	71	if (a->clk_ps != b->clk_ps)
	72	return false;
	73	if (a->mod_period != b->mod_period)
	74	return false;
	75	return true;
	76	}
	77
b505183b XL	78	static int fsl_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
b505183b XL	79	{
db6c51ab	80	int ret;
b505183b XL	81	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
b505183b XL	82
db6c51ab	83	ret = clk_prepare_enable(fpc->ipg_clk);
	84	if (!ret && fpc->soc->has_enable_bits) {
	85	mutex_lock(&fpc->lock);
	86	regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
	87	BIT(pwm->hwpwm + 16));
	88	mutex_unlock(&fpc->lock);
	89	}
	90
	91	return ret;
b505183b XL	92	}
	93
	94	static void fsl_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	95	{
	96	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	97
db6c51ab	98	if (fpc->soc->has_enable_bits) {
	99	mutex_lock(&fpc->lock);
	100	regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
	101	0);
	102	mutex_unlock(&fpc->lock);
	103	}
	104
82a9c55a	105	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	106	}
b505183b XL	107
3479bbd1 PH	108	static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
3479bbd1 PH	109	unsigned int ticks)
b505183b	110	{
3479bbd1 PH	111	unsigned long rate;
	112	unsigned long long exval;
	113
	114	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
	115	exval = ticks;
	116	exval *= 1000000000UL;
	117	do_div(exval, rate >> fpc->period.clk_ps);
	118	return exval;
b505183b XL	119	}
b505183b XL	120
3479bbd1 PH	121	static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
	122	unsigned int period_ns,
	123	enum fsl_pwm_clk index,
	124	struct fsl_pwm_periodcfg *periodcfg
	125	)
b505183b	126	{
3479bbd1 PH	127	unsigned long long c;
3479bbd1 PH	128	unsigned int ps;
b505183b	129
3479bbd1	130	c = clk_get_rate(fpc->clk[index]);
b505183b XL	131	c = c * period_ns;
	132	do_div(c, 1000000000UL);
	133
3479bbd1 PH	134	if (c == 0)
3479bbd1 PH	135	return false;
b505183b	136
3479bbd1 PH	137	for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
	138	if (c <= 0x10000) {
	139	periodcfg->clk_select = index;
	140	periodcfg->clk_ps = ps;
	141	periodcfg->mod_period = c - 1;
	142	return true;
	143	}
b505183b	144	}
3479bbd1	145	return false;
b505183b XL	146	}
b505183b XL	147
3479bbd1 PH	148	static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
	149	unsigned int period_ns,
	150	struct fsl_pwm_periodcfg *periodcfg)
b505183b XL	151	{
b505183b XL	152	enum fsl_pwm_clk m0, m1;
3479bbd1 PH	153	unsigned long fix_rate, ext_rate;
3479bbd1 PH	154	bool ret;
b505183b	155
3479bbd1 PH	156	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
	157	periodcfg);
	158	if (ret)
	159	return true;
b505183b XL	160
	161	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
	162	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
	163
	164	if (fix_rate > ext_rate) {
	165	m0 = FSL_PWM_CLK_FIX;
	166	m1 = FSL_PWM_CLK_EXT;
	167	} else {
	168	m0 = FSL_PWM_CLK_EXT;
	169	m1 = FSL_PWM_CLK_FIX;
	170	}
	171
3479bbd1 PH	172	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
	173	if (ret)
	174	return true;
b505183b	175
3479bbd1	176	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
b505183b XL	177	}
b505183b XL	178
3479bbd1 PH	179	static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
3479bbd1 PH	180	unsigned int duty_ns)
b505183b	181	{
42fa98a9	182	unsigned long long duty;
b505183b	183
3479bbd1 PH	184	unsigned int period = fpc->period.mod_period + 1;
	185	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
	186
	187	duty = (unsigned long long)duty_ns * period;
b505183b XL	188	do_div(duty, period_ns);
b505183b XL	189
3479bbd1	190	return (unsigned int)duty;
b505183b XL	191	}
b505183b XL	192
3479bbd1 PH	193	static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
3479bbd1 PH	194	struct pwm_device *pwm)
b505183b	195	{
3479bbd1	196	u32 val;
b505183b	197
3479bbd1 PH	198	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	199	if (~val & 0xFF)
	200	return true;
	201	else
	202	return false;
	203	}
	204
	205	static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
	206	struct pwm_device *pwm)
	207	{
	208	u32 val;
	209
	210	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	211	if (~(val \| BIT(pwm->hwpwm)) & 0xFF)
	212	return true;
	213	else
	214	return false;
	215	}
	216
	217	static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
	218	struct pwm_device *pwm,
	219	struct pwm_state *newstate)
	220	{
	221	unsigned int duty;
	222	u32 reg_polarity;
b505183b	223
3479bbd1 PH	224	struct fsl_pwm_periodcfg periodcfg;
	225	bool do_write_period = false;
	226
	227	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
	228	dev_err(fpc->chip.dev, "failed to calculate new period\n");
	229	return -EINVAL;
	230	}
	231
	232	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
	233	do_write_period = true;
b505183b XL	234	/*
b505183b XL	235	* The Freescale FTM controller supports only a single period for
3479bbd1 PH	236	* all PWM channels, therefore verify if the newly computed period
	237	* is different than the current period being used. In such case
	238	* we allow to change the period only if no other pwm is running.
b505183b	239	*/
3479bbd1 PH	240	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
	241	if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
	242	dev_err(fpc->chip.dev,
	243	"Cannot change period for PWM %u, disable other PWMs first\n",
	244	pwm->hwpwm);
	245	return -EBUSY;
b505183b	246	}
3479bbd1 PH	247	if (fpc->period.clk_select != periodcfg.clk_select) {
	248	int ret;
	249	enum fsl_pwm_clk oldclk = fpc->period.clk_select;
	250	enum fsl_pwm_clk newclk = periodcfg.clk_select;
	251
	252	ret = clk_prepare_enable(fpc->clk[newclk]);
	253	if (ret)
	254	return ret;
	255	clk_disable_unprepare(fpc->clk[oldclk]);
	256	}
	257	do_write_period = true;
	258	}
b505183b	259
3479bbd1 PH	260	if (do_write_period) {
	261	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
	262	FTM_SC_CLK(periodcfg.clk_select));
42fa98a9	263	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
3479bbd1 PH	264	periodcfg.clk_ps);
3479bbd1 PH	265	regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
b505183b	266
3479bbd1	267	fpc->period = periodcfg;
b505183b XL	268	}
b505183b XL	269
3479bbd1	270	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
b505183b	271
42fa98a9 XL	272	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
	273	FTM_CSC_MSB \| FTM_CSC_ELSB);
	274	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
b505183b	275
3479bbd1 PH	276	reg_polarity = 0;
	277	if (newstate->polarity == PWM_POLARITY_INVERSED)
	278	reg_polarity = BIT(pwm->hwpwm);
b505183b	279
3479bbd1	280	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
b505183b	281
3479bbd1 PH	282	newstate->period = fsl_pwm_ticks_to_ns(fpc,
	283	fpc->period.mod_period + 1);
	284	newstate->duty_cycle = fsl_pwm_ticks_to_ns(fpc, duty);
b505183b	285
b505183b XL	286	return 0;
	287	}
	288
3479bbd1 PH	289	static int fsl_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
3479bbd1 PH	290	struct pwm_state *newstate)
b505183b XL	291	{
b505183b XL	292	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
3479bbd1 PH	293	struct pwm_state *oldstate = &pwm->state;
3479bbd1 PH	294	int ret = 0;
b505183b	295
3479bbd1 PH	296	/*
	297	* oldstate to newstate : action
	298	*
	299	* disabled to disabled : ignore
	300	* enabled to disabled : disable
	301	* enabled to enabled : update settings
	302	* disabled to enabled : update settings + enable
	303	*/
b505183b	304
3479bbd1	305	mutex_lock(&fpc->lock);
b505183b	306
3479bbd1 PH	307	if (!newstate->enabled) {
	308	if (oldstate->enabled) {
	309	regmap_update_bits(fpc->regmap, FTM_OUTMASK,
	310	BIT(pwm->hwpwm), BIT(pwm->hwpwm));
	311	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
	312	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	313	}
b505183b	314
3479bbd1 PH	315	goto end_mutex;
3479bbd1 PH	316	}
b505183b	317
3479bbd1 PH	318	ret = fsl_pwm_apply_config(fpc, pwm, newstate);
	319	if (ret)
	320	goto end_mutex;
	321
	322	/* check if need to enable */
	323	if (!oldstate->enabled) {
	324	ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
	325	if (ret)
	326	return ret;
	327
	328	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	329	if (ret) {
	330	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	331	return ret;
	332	}
b505183b	333
3479bbd1 PH	334	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
	335	0);
	336	}
b505183b	337
3479bbd1	338	end_mutex:
b505183b	339	mutex_unlock(&fpc->lock);
3479bbd1	340	return ret;
b505183b XL	341	}
	342
	343	static const struct pwm_ops fsl_pwm_ops = {
	344	.request = fsl_pwm_request,
	345	.free = fsl_pwm_free,
3479bbd1	346	.apply = fsl_pwm_apply,
b505183b XL	347	.owner = THIS_MODULE,
	348	};
	349
	350	static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
	351	{
	352	int ret;
	353
82a9c55a	354	ret = clk_prepare_enable(fpc->ipg_clk);
b505183b XL	355	if (ret)
	356	return ret;
	357
42fa98a9 XL	358	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	359	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	360	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
b505183b	361
82a9c55a	362	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	363
	364	return 0;
	365	}
	366
49599cf6 XL	367	static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
	368	{
	369	switch (reg) {
	370	case FTM_CNT:
	371	return true;
	372	}
	373	return false;
	374	}
	375
42fa98a9 XL	376	static const struct regmap_config fsl_pwm_regmap_config = {
	377	.reg_bits = 32,
	378	.reg_stride = 4,
	379	.val_bits = 32,
	380
	381	.max_register = FTM_PWMLOAD,
49599cf6	382	.volatile_reg = fsl_pwm_volatile_reg,
ad06fdee	383	.cache_type = REGCACHE_FLAT,
42fa98a9 XL	384	};
42fa98a9 XL	385
b505183b XL	386	static int fsl_pwm_probe(struct platform_device *pdev)
	387	{
	388	struct fsl_pwm_chip *fpc;
	389	struct resource *res;
42fa98a9	390	void __iomem *base;
b505183b XL	391	int ret;
	392
	393	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
	394	if (!fpc)
	395	return -ENOMEM;
	396
	397	mutex_init(&fpc->lock);
	398
db6c51ab	399	fpc->soc = of_device_get_match_data(&pdev->dev);
b505183b XL	400	fpc->chip.dev = &pdev->dev;
	401
	402	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
42fa98a9 XL	403	base = devm_ioremap_resource(&pdev->dev, res);
	404	if (IS_ERR(base))
	405	return PTR_ERR(base);
	406
97d0b42e	407	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
42fa98a9 XL	408	&fsl_pwm_regmap_config);
	409	if (IS_ERR(fpc->regmap)) {
	410	dev_err(&pdev->dev, "regmap init failed\n");
	411	return PTR_ERR(fpc->regmap);
	412	}
b505183b XL	413
	414	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	415	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
	416	dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
	417	return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	418	}
	419
	420	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
	421	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
	422	return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
	423
	424	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
	425	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
	426	return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
	427
	428	fpc->clk[FSL_PWM_CLK_CNTEN] =
	429	devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
	430	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
	431	return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
	432
82a9c55a	433	/*
	434	* ipg_clk is the interface clock for the IP. If not provided, use the
	435	* ftm_sys clock as the default.
	436	*/
	437	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	438	if (IS_ERR(fpc->ipg_clk))
	439	fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
	440
	441
b505183b XL	442	fpc->chip.ops = &fsl_pwm_ops;
	443	fpc->chip.of_xlate = of_pwm_xlate_with_flags;
	444	fpc->chip.of_pwm_n_cells = 3;
	445	fpc->chip.base = -1;
	446	fpc->chip.npwm = 8;
	447
	448	ret = pwmchip_add(&fpc->chip);
	449	if (ret < 0) {
	450	dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
	451	return ret;
	452	}
	453
	454	platform_set_drvdata(pdev, fpc);
	455
	456	return fsl_pwm_init(fpc);
	457	}
	458
	459	static int fsl_pwm_remove(struct platform_device *pdev)
	460	{
	461	struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);
	462
	463	return pwmchip_remove(&fpc->chip);
	464	}
	465
97d0b42e XL	466	#ifdef CONFIG_PM_SLEEP
	467	static int fsl_pwm_suspend(struct device *dev)
	468	{
	469	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
816aec23	470	int i;
97d0b42e XL	471
	472	regcache_cache_only(fpc->regmap, true);
	473	regcache_mark_dirty(fpc->regmap);
	474
816aec23 SA	475	for (i = 0; i < fpc->chip.npwm; i++) {
	476	struct pwm_device *pwm = &fpc->chip.pwms[i];
	477
	478	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	479	continue;
	480
82a9c55a	481	clk_disable_unprepare(fpc->ipg_clk);
816aec23 SA	482
	483	if (!pwm_is_enabled(pwm))
	484	continue;
	485
97d0b42e	486	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
3479bbd1	487	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
97d0b42e XL	488	}
	489
	490	return 0;
	491	}
	492
	493	static int fsl_pwm_resume(struct device *dev)
	494	{
	495	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
816aec23 SA	496	int i;
	497
	498	for (i = 0; i < fpc->chip.npwm; i++) {
	499	struct pwm_device *pwm = &fpc->chip.pwms[i];
	500
	501	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	502	continue;
97d0b42e	503
82a9c55a	504	clk_prepare_enable(fpc->ipg_clk);
816aec23 SA	505
	506	if (!pwm_is_enabled(pwm))
	507	continue;
	508
3479bbd1	509	clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
97d0b42e XL	510	clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	511	}
	512
	513	/* restore all registers from cache */
	514	regcache_cache_only(fpc->regmap, false);
	515	regcache_sync(fpc->regmap);
	516
	517	return 0;
	518	}
	519	#endif
	520
	521	static const struct dev_pm_ops fsl_pwm_pm_ops = {
	522	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
	523	};
	524
db6c51ab	525	static const struct fsl_ftm_soc vf610_ftm_pwm = {
	526	.has_enable_bits = false,
	527	};
	528
2c4f2e32	529	static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	530	.has_enable_bits = true,
	531	};
	532
b505183b	533	static const struct of_device_id fsl_pwm_dt_ids[] = {
db6c51ab	534	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
2c4f2e32	535	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
b505183b XL	536	{ /* sentinel */ }
	537	};
	538	MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
	539
	540	static struct platform_driver fsl_pwm_driver = {
	541	.driver = {
	542	.name = "fsl-ftm-pwm",
	543	.of_match_table = fsl_pwm_dt_ids,
97d0b42e	544	.pm = &fsl_pwm_pm_ops,
b505183b XL	545	},
	546	.probe = fsl_pwm_probe,
	547	.remove = fsl_pwm_remove,
	548	};
	549	module_platform_driver(fsl_pwm_driver);
	550
	551	MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
	552	MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
	553	MODULE_ALIAS("platform:fsl-ftm-pwm");
	554	MODULE_LICENSE("GPL");