[linux-block.git] / drivers / pwm / pwm-fsl-ftm.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Freescale FlexTimer Module (FTM) PWM Driver
 *
 *  Copyright 2012-2013 Freescale Semiconductor, Inc.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/fsl/ftm.h>

#define FTM_SC_CLK(c)	(((c) + 1) << FTM_SC_CLK_MASK_SHIFT)

enum fsl_pwm_clk {
	FSL_PWM_CLK_SYS,
	FSL_PWM_CLK_FIX,
	FSL_PWM_CLK_EXT,
	FSL_PWM_CLK_CNTEN,
	FSL_PWM_CLK_MAX
};

struct fsl_ftm_soc {
	bool has_enable_bits;
};

struct fsl_pwm_periodcfg {
	enum fsl_pwm_clk clk_select;
	unsigned int clk_ps;
	unsigned int mod_period;
};

struct fsl_pwm_chip {
	struct pwm_chip chip;
	struct mutex lock;
	struct regmap *regmap;

	/* This value is valid iff a pwm is running */
	struct fsl_pwm_periodcfg period;

	struct clk *ipg_clk;
	struct clk *clk[FSL_PWM_CLK_MAX];

	const struct fsl_ftm_soc *soc;
};

static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct fsl_pwm_chip, chip);
}

static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_FMS, &val);
	if (val & FTM_FMS_WPEN)
		regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
}

static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
{
	regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
}

static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
					const struct fsl_pwm_periodcfg *b)
{
	if (a->clk_select != b->clk_select)
		return false;
	if (a->clk_ps != b->clk_ps)
		return false;
	if (a->mod_period != b->mod_period)
		return false;
	return true;
}

static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	int ret;
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (!ret && fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
		mutex_unlock(&fpc->lock);
	}

	return ret;
}

static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	if (fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
		mutex_unlock(&fpc->lock);
	}

	clk_disable_unprepare(fpc->ipg_clk);
}

static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
					  unsigned int ticks)
{
	unsigned long rate;
	unsigned long long exval;

	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
	exval = ticks;
	exval *= 1000000000UL;
	do_div(exval, rate >> fpc->period.clk_ps);
	return exval;
}

static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
					 unsigned int period_ns,
					 enum fsl_pwm_clk index,
					 struct fsl_pwm_periodcfg *periodcfg
					 )
{
	unsigned long long c;
	unsigned int ps;

	c = clk_get_rate(fpc->clk[index]);
	c = c * period_ns;
	do_div(c, 1000000000UL);

	if (c == 0)
		return false;

	for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
		if (c <= 0x10000) {
			periodcfg->clk_select = index;
			periodcfg->clk_ps = ps;
			periodcfg->mod_period = c - 1;
			return true;
		}
	}
	return false;
}

static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
				     unsigned int period_ns,
				     struct fsl_pwm_periodcfg *periodcfg)
{
	enum fsl_pwm_clk m0, m1;
	unsigned long fix_rate, ext_rate;
	bool ret;

	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
					   periodcfg);
	if (ret)
		return true;

	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);

	if (fix_rate > ext_rate) {
		m0 = FSL_PWM_CLK_FIX;
		m1 = FSL_PWM_CLK_EXT;
	} else {
		m0 = FSL_PWM_CLK_EXT;
		m1 = FSL_PWM_CLK_FIX;
	}

	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
	if (ret)
		return true;

	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
}

static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
					   unsigned int duty_ns)
{
	unsigned long long duty;

	unsigned int period = fpc->period.mod_period + 1;
	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);

	duty = (unsigned long long)duty_ns * period;
	do_div(duty, period_ns);

	return (unsigned int)duty;
}

static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
				       struct pwm_device *pwm)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	if (~val & 0xFF)
		return true;
	else
		return false;
}

static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
					 struct pwm_device *pwm)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	if (~(val | BIT(pwm->hwpwm)) & 0xFF)
		return true;
	else
		return false;
}

static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
				struct pwm_device *pwm,
				const struct pwm_state *newstate)
{
	unsigned int duty;
	u32 reg_polarity;

	struct fsl_pwm_periodcfg periodcfg;
	bool do_write_period = false;

	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
		dev_err(fpc->chip.dev, "failed to calculate new period\n");
		return -EINVAL;
	}

	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
		do_write_period = true;
	/*
	 * The Freescale FTM controller supports only a single period for
	 * all PWM channels, therefore verify if the newly computed period
	 * is different than the current period being used. In such case
	 * we allow to change the period only if no other pwm is running.
	 */
	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
		if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
			dev_err(fpc->chip.dev,
				"Cannot change period for PWM %u, disable other PWMs first\n",
				pwm->hwpwm);
			return -EBUSY;
		}
		if (fpc->period.clk_select != periodcfg.clk_select) {
			int ret;
			enum fsl_pwm_clk oldclk = fpc->period.clk_select;
			enum fsl_pwm_clk newclk = periodcfg.clk_select;

			ret = clk_prepare_enable(fpc->clk[newclk]);
			if (ret)
				return ret;
			clk_disable_unprepare(fpc->clk[oldclk]);
		}
		do_write_period = true;
	}

	ftm_clear_write_protection(fpc);

	if (do_write_period) {
		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
				   FTM_SC_CLK(periodcfg.clk_select));
		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
				   periodcfg.clk_ps);
		regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);

		fpc->period = periodcfg;
	}

	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);

	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
		     FTM_CSC_MSB | FTM_CSC_ELSB);
	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);

	reg_polarity = 0;
	if (newstate->polarity == PWM_POLARITY_INVERSED)
		reg_polarity = BIT(pwm->hwpwm);

	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);

	ftm_set_write_protection(fpc);

	return 0;
}

static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *newstate)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	struct pwm_state *oldstate = &pwm->state;
	int ret = 0;

	/*
	 * oldstate to newstate : action
	 *
	 * disabled to disabled : ignore
	 * enabled to disabled : disable
	 * enabled to enabled : update settings
	 * disabled to enabled : update settings + enable
	 */

	mutex_lock(&fpc->lock);

	if (!newstate->enabled) {
		if (oldstate->enabled) {
			regmap_set_bits(fpc->regmap, FTM_OUTMASK,
					BIT(pwm->hwpwm));
			clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
		}

		goto end_mutex;
	}

	ret = fsl_pwm_apply_config(fpc, pwm, newstate);
	if (ret)
		goto end_mutex;

	/* check if need to enable */
	if (!oldstate->enabled) {
		ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
		if (ret)
			goto end_mutex;

		ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
		if (ret) {
			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
			goto end_mutex;
		}

		regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
	}

end_mutex:
	mutex_unlock(&fpc->lock);
	return ret;
}

static const struct pwm_ops fsl_pwm_ops = {
	.request = fsl_pwm_request,
	.free = fsl_pwm_free,
	.apply = fsl_pwm_apply,
	.owner = THIS_MODULE,
};

static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
{
	int ret;

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (ret)
		return ret;

	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);

	clk_disable_unprepare(fpc->ipg_clk);

	return 0;
}

static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case FTM_FMS:
	case FTM_MODE:
	case FTM_CNT:
		return true;
	}
	return false;
}

static const struct regmap_config fsl_pwm_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,

	.max_register = FTM_PWMLOAD,
	.volatile_reg = fsl_pwm_volatile_reg,
	.cache_type = REGCACHE_FLAT,
};

static int fsl_pwm_probe(struct platform_device *pdev)
{
	struct fsl_pwm_chip *fpc;
	void __iomem *base;
	int ret;

	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
	if (!fpc)
		return -ENOMEM;

	mutex_init(&fpc->lock);

	fpc->soc = of_device_get_match_data(&pdev->dev);
	fpc->chip.dev = &pdev->dev;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
						&fsl_pwm_regmap_config);
	if (IS_ERR(fpc->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(fpc->regmap);
	}

	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
		dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	}

	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);

	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);

	fpc->clk[FSL_PWM_CLK_CNTEN] =
				devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);

	/*
	 * ipg_clk is the interface clock for the IP. If not provided, use the
	 * ftm_sys clock as the default.
	 */
	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(fpc->ipg_clk))
		fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];


	fpc->chip.ops = &fsl_pwm_ops;
	fpc->chip.npwm = 8;

	ret = devm_pwmchip_add(&pdev->dev, &fpc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, fpc);

	return fsl_pwm_init(fpc);
}

#ifdef CONFIG_PM_SLEEP
static int fsl_pwm_suspend(struct device *dev)
{
	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
	int i;

	regcache_cache_only(fpc->regmap, true);
	regcache_mark_dirty(fpc->regmap);

	for (i = 0; i < fpc->chip.npwm; i++) {
		struct pwm_device *pwm = &fpc->chip.pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_disable_unprepare(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
		clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	}

	return 0;
}

static int fsl_pwm_resume(struct device *dev)
{
	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
	int i;

	for (i = 0; i < fpc->chip.npwm; i++) {
		struct pwm_device *pwm = &fpc->chip.pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_prepare_enable(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	}

	/* restore all registers from cache */
	regcache_cache_only(fpc->regmap, false);
	regcache_sync(fpc->regmap);

	return 0;
}
#endif

static const struct dev_pm_ops fsl_pwm_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
};

static const struct fsl_ftm_soc vf610_ftm_pwm = {
	.has_enable_bits = false,
};

static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	.has_enable_bits = true,
};

static const struct of_device_id fsl_pwm_dt_ids[] = {
	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);

static struct platform_driver fsl_pwm_driver = {
	.driver = {
		.name = "fsl-ftm-pwm",
		.of_match_table = fsl_pwm_dt_ids,
		.pm = &fsl_pwm_pm_ops,
	},
	.probe = fsl_pwm_probe,
};
module_platform_driver(fsl_pwm_driver);

MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
MODULE_ALIAS("platform:fsl-ftm-pwm");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
b505183b XL	2	/*
	3	* Freescale FlexTimer Module (FTM) PWM Driver
	4	*
	5	* Copyright 2012-2013 Freescale Semiconductor, Inc.
b505183b XL	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/err.h>
	10	#include <linux/io.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/mutex.h>
	14	#include <linux/of_address.h>
db6c51ab	15	#include <linux/of_device.h>
b505183b	16	#include <linux/platform_device.h>
97d0b42e	17	#include <linux/pm.h>
b505183b	18	#include <linux/pwm.h>
42fa98a9	19	#include <linux/regmap.h>
b505183b	20	#include <linux/slab.h>
e590eb40	21	#include <linux/fsl/ftm.h>
b505183b	22
cd6d92d2	23	#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
b505183b XL	24
	25	enum fsl_pwm_clk {
	26	FSL_PWM_CLK_SYS,
	27	FSL_PWM_CLK_FIX,
	28	FSL_PWM_CLK_EXT,
	29	FSL_PWM_CLK_CNTEN,
	30	FSL_PWM_CLK_MAX
	31	};
	32
db6c51ab	33	struct fsl_ftm_soc {
	34	bool has_enable_bits;
	35	};
	36
3479bbd1 PH	37	struct fsl_pwm_periodcfg {
	38	enum fsl_pwm_clk clk_select;
	39	unsigned int clk_ps;
	40	unsigned int mod_period;
	41	};
	42
b505183b XL	43	struct fsl_pwm_chip {
b505183b XL	44	struct pwm_chip chip;
b505183b	45	struct mutex lock;
42fa98a9	46	struct regmap *regmap;
b505183b	47
3479bbd1 PH	48	/* This value is valid iff a pwm is running */
3479bbd1 PH	49	struct fsl_pwm_periodcfg period;
b505183b	50
82a9c55a	51	struct clk *ipg_clk;
b505183b	52	struct clk *clk[FSL_PWM_CLK_MAX];
db6c51ab	53
db6c51ab	54	const struct fsl_ftm_soc *soc;
b505183b XL	55	};
	56
	57	static inline struct fsl_pwm_chip to_fsl_chip(struct pwm_chip chip)
	58	{
	59	return container_of(chip, struct fsl_pwm_chip, chip);
	60	}
	61
a2a28229 PH	62	static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
	63	{
	64	u32 val;
	65
	66	regmap_read(fpc->regmap, FTM_FMS, &val);
	67	if (val & FTM_FMS_WPEN)
c637d87a	68	regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
a2a28229 PH	69	}
	70
	71	static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
	72	{
c637d87a	73	regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
a2a28229 PH	74	}
a2a28229 PH	75
3479bbd1 PH	76	static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
	77	const struct fsl_pwm_periodcfg *b)
	78	{
	79	if (a->clk_select != b->clk_select)
	80	return false;
	81	if (a->clk_ps != b->clk_ps)
	82	return false;
	83	if (a->mod_period != b->mod_period)
	84	return false;
	85	return true;
	86	}
	87
b505183b XL	88	static int fsl_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
b505183b XL	89	{
db6c51ab	90	int ret;
b505183b XL	91	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
b505183b XL	92
db6c51ab	93	ret = clk_prepare_enable(fpc->ipg_clk);
	94	if (!ret && fpc->soc->has_enable_bits) {
	95	mutex_lock(&fpc->lock);
c637d87a	96	regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
db6c51ab	97	mutex_unlock(&fpc->lock);
	98	}
	99
	100	return ret;
b505183b XL	101	}
	102
	103	static void fsl_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	104	{
	105	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	106
db6c51ab	107	if (fpc->soc->has_enable_bits) {
db6c51ab	108	mutex_lock(&fpc->lock);
c637d87a	109	regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
db6c51ab	110	mutex_unlock(&fpc->lock);
	111	}
	112
82a9c55a	113	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	114	}
b505183b XL	115
3479bbd1 PH	116	static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
3479bbd1 PH	117	unsigned int ticks)
b505183b	118	{
3479bbd1 PH	119	unsigned long rate;
	120	unsigned long long exval;
	121
	122	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
	123	exval = ticks;
	124	exval *= 1000000000UL;
	125	do_div(exval, rate >> fpc->period.clk_ps);
	126	return exval;
b505183b XL	127	}
b505183b XL	128
3479bbd1 PH	129	static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
	130	unsigned int period_ns,
	131	enum fsl_pwm_clk index,
	132	struct fsl_pwm_periodcfg *periodcfg
	133	)
b505183b	134	{
3479bbd1 PH	135	unsigned long long c;
3479bbd1 PH	136	unsigned int ps;
b505183b	137
3479bbd1	138	c = clk_get_rate(fpc->clk[index]);
b505183b XL	139	c = c * period_ns;
	140	do_div(c, 1000000000UL);
	141
3479bbd1 PH	142	if (c == 0)
3479bbd1 PH	143	return false;
b505183b	144
3479bbd1 PH	145	for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
	146	if (c <= 0x10000) {
	147	periodcfg->clk_select = index;
	148	periodcfg->clk_ps = ps;
	149	periodcfg->mod_period = c - 1;
	150	return true;
	151	}
b505183b	152	}
3479bbd1	153	return false;
b505183b XL	154	}
b505183b XL	155
3479bbd1 PH	156	static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
	157	unsigned int period_ns,
	158	struct fsl_pwm_periodcfg *periodcfg)
b505183b XL	159	{
b505183b XL	160	enum fsl_pwm_clk m0, m1;
3479bbd1 PH	161	unsigned long fix_rate, ext_rate;
3479bbd1 PH	162	bool ret;
b505183b	163
3479bbd1 PH	164	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
	165	periodcfg);
	166	if (ret)
	167	return true;
b505183b XL	168
	169	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
	170	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
	171
	172	if (fix_rate > ext_rate) {
	173	m0 = FSL_PWM_CLK_FIX;
	174	m1 = FSL_PWM_CLK_EXT;
	175	} else {
	176	m0 = FSL_PWM_CLK_EXT;
	177	m1 = FSL_PWM_CLK_FIX;
	178	}
	179
3479bbd1 PH	180	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
	181	if (ret)
	182	return true;
b505183b	183
3479bbd1	184	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
b505183b XL	185	}
b505183b XL	186
3479bbd1 PH	187	static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
3479bbd1 PH	188	unsigned int duty_ns)
b505183b	189	{
42fa98a9	190	unsigned long long duty;
b505183b	191
3479bbd1 PH	192	unsigned int period = fpc->period.mod_period + 1;
	193	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
	194
	195	duty = (unsigned long long)duty_ns * period;
b505183b XL	196	do_div(duty, period_ns);
b505183b XL	197
3479bbd1	198	return (unsigned int)duty;
b505183b XL	199	}
b505183b XL	200
3479bbd1 PH	201	static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
3479bbd1 PH	202	struct pwm_device *pwm)
b505183b	203	{
3479bbd1	204	u32 val;
b505183b	205
3479bbd1 PH	206	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	207	if (~val & 0xFF)
	208	return true;
	209	else
	210	return false;
	211	}
	212
	213	static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
	214	struct pwm_device *pwm)
	215	{
	216	u32 val;
b505183b	217
3479bbd1 PH	218	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	219	if (~(val \| BIT(pwm->hwpwm)) & 0xFF)
	220	return true;
	221	else
	222	return false;
	223	}
	224
	225	static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
	226	struct pwm_device *pwm,
71523d18	227	const struct pwm_state *newstate)
3479bbd1 PH	228	{
	229	unsigned int duty;
	230	u32 reg_polarity;
b505183b	231
3479bbd1 PH	232	struct fsl_pwm_periodcfg periodcfg;
	233	bool do_write_period = false;
	234
	235	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
	236	dev_err(fpc->chip.dev, "failed to calculate new period\n");
	237	return -EINVAL;
	238	}
	239
	240	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
	241	do_write_period = true;
b505183b XL	242	/*
b505183b XL	243	* The Freescale FTM controller supports only a single period for
3479bbd1 PH	244	* all PWM channels, therefore verify if the newly computed period
	245	* is different than the current period being used. In such case
	246	* we allow to change the period only if no other pwm is running.
b505183b	247	*/
3479bbd1 PH	248	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
	249	if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
	250	dev_err(fpc->chip.dev,
	251	"Cannot change period for PWM %u, disable other PWMs first\n",
	252	pwm->hwpwm);
	253	return -EBUSY;
b505183b	254	}
3479bbd1 PH	255	if (fpc->period.clk_select != periodcfg.clk_select) {
	256	int ret;
	257	enum fsl_pwm_clk oldclk = fpc->period.clk_select;
	258	enum fsl_pwm_clk newclk = periodcfg.clk_select;
	259
	260	ret = clk_prepare_enable(fpc->clk[newclk]);
	261	if (ret)
	262	return ret;
	263	clk_disable_unprepare(fpc->clk[oldclk]);
	264	}
	265	do_write_period = true;
b505183b XL	266	}
b505183b XL	267
a2a28229	268	ftm_clear_write_protection(fpc);
b505183b	269
3479bbd1 PH	270	if (do_write_period) {
	271	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
	272	FTM_SC_CLK(periodcfg.clk_select));
42fa98a9	273	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
3479bbd1 PH	274	periodcfg.clk_ps);
3479bbd1 PH	275	regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
b505183b	276
3479bbd1	277	fpc->period = periodcfg;
b505183b XL	278	}
b505183b XL	279
3479bbd1	280	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
b505183b	281
42fa98a9 XL	282	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
	283	FTM_CSC_MSB \| FTM_CSC_ELSB);
	284	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
b505183b	285
3479bbd1 PH	286	reg_polarity = 0;
	287	if (newstate->polarity == PWM_POLARITY_INVERSED)
	288	reg_polarity = BIT(pwm->hwpwm);
b505183b	289
3479bbd1	290	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
b505183b	291
a2a28229	292	ftm_set_write_protection(fpc);
b505183b XL	293
	294	return 0;
	295	}
	296
3479bbd1	297	static int fsl_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	298	const struct pwm_state *newstate)
b505183b XL	299	{
b505183b XL	300	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
3479bbd1 PH	301	struct pwm_state *oldstate = &pwm->state;
3479bbd1 PH	302	int ret = 0;
b505183b	303
3479bbd1 PH	304	/*
	305	* oldstate to newstate : action
	306	*
	307	* disabled to disabled : ignore
	308	* enabled to disabled : disable
	309	* enabled to enabled : update settings
	310	* disabled to enabled : update settings + enable
	311	*/
b505183b	312
3479bbd1	313	mutex_lock(&fpc->lock);
b505183b	314
3479bbd1 PH	315	if (!newstate->enabled) {
3479bbd1 PH	316	if (oldstate->enabled) {
c637d87a UKK	317	regmap_set_bits(fpc->regmap, FTM_OUTMASK,
c637d87a UKK	318	BIT(pwm->hwpwm));
3479bbd1 PH	319	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
	320	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	321	}
b505183b	322
3479bbd1 PH	323	goto end_mutex;
3479bbd1 PH	324	}
b505183b	325
3479bbd1 PH	326	ret = fsl_pwm_apply_config(fpc, pwm, newstate);
	327	if (ret)
	328	goto end_mutex;
	329
	330	/* check if need to enable */
	331	if (!oldstate->enabled) {
	332	ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
	333	if (ret)
3d25025c	334	goto end_mutex;
3479bbd1 PH	335
	336	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	337	if (ret) {
	338	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
3d25025c	339	goto end_mutex;
3479bbd1	340	}
b505183b	341
c637d87a	342	regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
3479bbd1	343	}
b505183b	344
3479bbd1	345	end_mutex:
b505183b	346	mutex_unlock(&fpc->lock);
3479bbd1	347	return ret;
b505183b XL	348	}
	349
	350	static const struct pwm_ops fsl_pwm_ops = {
	351	.request = fsl_pwm_request,
	352	.free = fsl_pwm_free,
3479bbd1	353	.apply = fsl_pwm_apply,
b505183b XL	354	.owner = THIS_MODULE,
	355	};
	356
	357	static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
	358	{
	359	int ret;
	360
82a9c55a	361	ret = clk_prepare_enable(fpc->ipg_clk);
b505183b XL	362	if (ret)
	363	return ret;
	364
42fa98a9 XL	365	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	366	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	367	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
b505183b	368
82a9c55a	369	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	370
	371	return 0;
	372	}
	373
49599cf6 XL	374	static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
	375	{
	376	switch (reg) {
a2a28229 PH	377	case FTM_FMS:
a2a28229 PH	378	case FTM_MODE:
49599cf6 XL	379	case FTM_CNT:
	380	return true;
	381	}
	382	return false;
	383	}
	384
42fa98a9 XL	385	static const struct regmap_config fsl_pwm_regmap_config = {
	386	.reg_bits = 32,
	387	.reg_stride = 4,
	388	.val_bits = 32,
	389
	390	.max_register = FTM_PWMLOAD,
49599cf6	391	.volatile_reg = fsl_pwm_volatile_reg,
ad06fdee	392	.cache_type = REGCACHE_FLAT,
42fa98a9 XL	393	};
42fa98a9 XL	394
b505183b XL	395	static int fsl_pwm_probe(struct platform_device *pdev)
	396	{
	397	struct fsl_pwm_chip *fpc;
42fa98a9	398	void __iomem *base;
b505183b XL	399	int ret;
	400
	401	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
	402	if (!fpc)
	403	return -ENOMEM;
	404
	405	mutex_init(&fpc->lock);
	406
db6c51ab	407	fpc->soc = of_device_get_match_data(&pdev->dev);
b505183b XL	408	fpc->chip.dev = &pdev->dev;
b505183b XL	409
e9534031	410	base = devm_platform_ioremap_resource(pdev, 0);
42fa98a9 XL	411	if (IS_ERR(base))
	412	return PTR_ERR(base);
	413
97d0b42e	414	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
42fa98a9 XL	415	&fsl_pwm_regmap_config);
	416	if (IS_ERR(fpc->regmap)) {
	417	dev_err(&pdev->dev, "regmap init failed\n");
	418	return PTR_ERR(fpc->regmap);
	419	}
b505183b XL	420
	421	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	422	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
	423	dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
	424	return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	425	}
	426
	427	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
	428	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
	429	return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
	430
	431	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
	432	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
	433	return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
	434
	435	fpc->clk[FSL_PWM_CLK_CNTEN] =
	436	devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
	437	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
	438	return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
	439
82a9c55a	440	/*
	441	* ipg_clk is the interface clock for the IP. If not provided, use the
	442	* ftm_sys clock as the default.
	443	*/
	444	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	445	if (IS_ERR(fpc->ipg_clk))
	446	fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
	447
	448
b505183b	449	fpc->chip.ops = &fsl_pwm_ops;
b505183b XL	450	fpc->chip.npwm = 8;
b505183b XL	451
5ba3eb4b	452	ret = devm_pwmchip_add(&pdev->dev, &fpc->chip);
b505183b XL	453	if (ret < 0) {
	454	dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
	455	return ret;
	456	}
	457
	458	platform_set_drvdata(pdev, fpc);
	459
	460	return fsl_pwm_init(fpc);
	461	}
	462
97d0b42e XL	463	#ifdef CONFIG_PM_SLEEP
	464	static int fsl_pwm_suspend(struct device *dev)
	465	{
	466	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
816aec23	467	int i;
97d0b42e XL	468
	469	regcache_cache_only(fpc->regmap, true);
	470	regcache_mark_dirty(fpc->regmap);
	471
816aec23 SA	472	for (i = 0; i < fpc->chip.npwm; i++) {
	473	struct pwm_device *pwm = &fpc->chip.pwms[i];
	474
	475	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	476	continue;
	477
82a9c55a	478	clk_disable_unprepare(fpc->ipg_clk);
816aec23 SA	479
	480	if (!pwm_is_enabled(pwm))
	481	continue;
	482
97d0b42e	483	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
3479bbd1	484	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
97d0b42e XL	485	}
	486
	487	return 0;
	488	}
	489
	490	static int fsl_pwm_resume(struct device *dev)
	491	{
	492	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
816aec23 SA	493	int i;
	494
	495	for (i = 0; i < fpc->chip.npwm; i++) {
	496	struct pwm_device *pwm = &fpc->chip.pwms[i];
	497
	498	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	499	continue;
97d0b42e	500
82a9c55a	501	clk_prepare_enable(fpc->ipg_clk);
816aec23 SA	502
	503	if (!pwm_is_enabled(pwm))
	504	continue;
	505
3479bbd1	506	clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
97d0b42e XL	507	clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	508	}
	509
	510	/* restore all registers from cache */
	511	regcache_cache_only(fpc->regmap, false);
	512	regcache_sync(fpc->regmap);
	513
	514	return 0;
	515	}
	516	#endif
	517
	518	static const struct dev_pm_ops fsl_pwm_pm_ops = {
	519	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
	520	};
	521
db6c51ab	522	static const struct fsl_ftm_soc vf610_ftm_pwm = {
	523	.has_enable_bits = false,
	524	};
	525
2c4f2e32	526	static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	527	.has_enable_bits = true,
	528	};
	529
b505183b	530	static const struct of_device_id fsl_pwm_dt_ids[] = {
db6c51ab	531	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
2c4f2e32	532	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
b505183b XL	533	{ /* sentinel */ }
	534	};
	535	MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
	536
	537	static struct platform_driver fsl_pwm_driver = {
	538	.driver = {
	539	.name = "fsl-ftm-pwm",
	540	.of_match_table = fsl_pwm_dt_ids,
97d0b42e	541	.pm = &fsl_pwm_pm_ops,
b505183b XL	542	},
b505183b XL	543	.probe = fsl_pwm_probe,
b505183b XL	544	};
	545	module_platform_driver(fsl_pwm_driver);
	546
	547	MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
	548	MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
	549	MODULE_ALIAS("platform:fsl-ftm-pwm");
	550	MODULE_LICENSE("GPL");