[linux-block.git] / drivers / pwm / pwm-fsl-ftm.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Freescale FlexTimer Module (FTM) PWM Driver
 *
 *  Copyright 2012-2013 Freescale Semiconductor, Inc.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/fsl/ftm.h>

#define FTM_SC_CLK(c)	(((c) + 1) << FTM_SC_CLK_MASK_SHIFT)

enum fsl_pwm_clk {
	FSL_PWM_CLK_SYS,
	FSL_PWM_CLK_FIX,
	FSL_PWM_CLK_EXT,
	FSL_PWM_CLK_CNTEN,
	FSL_PWM_CLK_MAX
};

struct fsl_ftm_soc {
	bool has_enable_bits;
};

struct fsl_pwm_periodcfg {
	enum fsl_pwm_clk clk_select;
	unsigned int clk_ps;
	unsigned int mod_period;
};

struct fsl_pwm_chip {
	struct mutex lock;
	struct regmap *regmap;

	/* This value is valid iff a pwm is running */
	struct fsl_pwm_periodcfg period;

	struct clk *ipg_clk;
	struct clk *clk[FSL_PWM_CLK_MAX];

	const struct fsl_ftm_soc *soc;
};

static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_FMS, &val);
	if (val & FTM_FMS_WPEN)
		regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
}

static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
{
	regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
}

static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
					const struct fsl_pwm_periodcfg *b)
{
	if (a->clk_select != b->clk_select)
		return false;
	if (a->clk_ps != b->clk_ps)
		return false;
	if (a->mod_period != b->mod_period)
		return false;
	return true;
}

static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	int ret;
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (!ret && fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
		mutex_unlock(&fpc->lock);
	}

	return ret;
}

static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);

	if (fpc->soc->has_enable_bits) {
		mutex_lock(&fpc->lock);
		regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
		mutex_unlock(&fpc->lock);
	}

	clk_disable_unprepare(fpc->ipg_clk);
}

static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
					  unsigned int ticks)
{
	unsigned long rate;
	unsigned long long exval;

	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
	exval = ticks;
	exval *= 1000000000UL;
	do_div(exval, rate >> fpc->period.clk_ps);
	return exval;
}

static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
					 unsigned int period_ns,
					 enum fsl_pwm_clk index,
					 struct fsl_pwm_periodcfg *periodcfg
					 )
{
	unsigned long long c;
	unsigned int ps;

	c = clk_get_rate(fpc->clk[index]);
	c = c * period_ns;
	do_div(c, 1000000000UL);

	if (c == 0)
		return false;

	for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
		if (c <= 0x10000) {
			periodcfg->clk_select = index;
			periodcfg->clk_ps = ps;
			periodcfg->mod_period = c - 1;
			return true;
		}
	}
	return false;
}

static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
				     unsigned int period_ns,
				     struct fsl_pwm_periodcfg *periodcfg)
{
	enum fsl_pwm_clk m0, m1;
	unsigned long fix_rate, ext_rate;
	bool ret;

	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
					   periodcfg);
	if (ret)
		return true;

	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);

	if (fix_rate > ext_rate) {
		m0 = FSL_PWM_CLK_FIX;
		m1 = FSL_PWM_CLK_EXT;
	} else {
		m0 = FSL_PWM_CLK_EXT;
		m1 = FSL_PWM_CLK_FIX;
	}

	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
	if (ret)
		return true;

	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
}

static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
					   unsigned int duty_ns)
{
	unsigned long long duty;

	unsigned int period = fpc->period.mod_period + 1;
	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);

	duty = (unsigned long long)duty_ns * period;
	do_div(duty, period_ns);

	return (unsigned int)duty;
}

static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
				       struct pwm_device *pwm)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	if (~val & 0xFF)
		return true;
	else
		return false;
}

static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
					 struct pwm_device *pwm)
{
	u32 val;

	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	if (~(val | BIT(pwm->hwpwm)) & 0xFF)
		return true;
	else
		return false;
}

static int fsl_pwm_apply_config(struct pwm_chip *chip,
				struct pwm_device *pwm,
				const struct pwm_state *newstate)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	unsigned int duty;
	u32 reg_polarity;

	struct fsl_pwm_periodcfg periodcfg;
	bool do_write_period = false;

	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
		dev_err(pwmchip_parent(chip), "failed to calculate new period\n");
		return -EINVAL;
	}

	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
		do_write_period = true;
	/*
	 * The Freescale FTM controller supports only a single period for
	 * all PWM channels, therefore verify if the newly computed period
	 * is different than the current period being used. In such case
	 * we allow to change the period only if no other pwm is running.
	 */
	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
		if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
			dev_err(pwmchip_parent(chip),
				"Cannot change period for PWM %u, disable other PWMs first\n",
				pwm->hwpwm);
			return -EBUSY;
		}
		if (fpc->period.clk_select != periodcfg.clk_select) {
			int ret;
			enum fsl_pwm_clk oldclk = fpc->period.clk_select;
			enum fsl_pwm_clk newclk = periodcfg.clk_select;

			ret = clk_prepare_enable(fpc->clk[newclk]);
			if (ret)
				return ret;
			clk_disable_unprepare(fpc->clk[oldclk]);
		}
		do_write_period = true;
	}

	ftm_clear_write_protection(fpc);

	if (do_write_period) {
		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
				   FTM_SC_CLK(periodcfg.clk_select));
		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
				   periodcfg.clk_ps);
		regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);

		fpc->period = periodcfg;
	}

	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);

	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
		     FTM_CSC_MSB | FTM_CSC_ELSB);
	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);

	reg_polarity = 0;
	if (newstate->polarity == PWM_POLARITY_INVERSED)
		reg_polarity = BIT(pwm->hwpwm);

	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);

	ftm_set_write_protection(fpc);

	return 0;
}

static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *newstate)
{
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	struct pwm_state *oldstate = &pwm->state;
	int ret = 0;

	/*
	 * oldstate to newstate : action
	 *
	 * disabled to disabled : ignore
	 * enabled to disabled : disable
	 * enabled to enabled : update settings
	 * disabled to enabled : update settings + enable
	 */

	mutex_lock(&fpc->lock);

	if (!newstate->enabled) {
		if (oldstate->enabled) {
			regmap_set_bits(fpc->regmap, FTM_OUTMASK,
					BIT(pwm->hwpwm));
			clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
		}

		goto end_mutex;
	}

	ret = fsl_pwm_apply_config(chip, pwm, newstate);
	if (ret)
		goto end_mutex;

	/* check if need to enable */
	if (!oldstate->enabled) {
		ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
		if (ret)
			goto end_mutex;

		ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
		if (ret) {
			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
			goto end_mutex;
		}

		regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
	}

end_mutex:
	mutex_unlock(&fpc->lock);
	return ret;
}

static const struct pwm_ops fsl_pwm_ops = {
	.request = fsl_pwm_request,
	.free = fsl_pwm_free,
	.apply = fsl_pwm_apply,
};

static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
{
	int ret;

	ret = clk_prepare_enable(fpc->ipg_clk);
	if (ret)
		return ret;

	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);

	clk_disable_unprepare(fpc->ipg_clk);

	return 0;
}

static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case FTM_FMS:
	case FTM_MODE:
	case FTM_CNT:
		return true;
	}
	return false;
}

static const struct regmap_config fsl_pwm_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,

	.max_register = FTM_PWMLOAD,
	.volatile_reg = fsl_pwm_volatile_reg,
	.cache_type = REGCACHE_FLAT,
};

static int fsl_pwm_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	struct fsl_pwm_chip *fpc;
	void __iomem *base;
	int ret;

	chip = devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*fpc));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	fpc = to_fsl_chip(chip);

	mutex_init(&fpc->lock);

	fpc->soc = of_device_get_match_data(&pdev->dev);

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
						&fsl_pwm_regmap_config);
	if (IS_ERR(fpc->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(fpc->regmap);
	}

	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
		dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	}

	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(&pdev->dev, "ftm_fix");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);

	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(&pdev->dev, "ftm_ext");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);

	fpc->clk[FSL_PWM_CLK_CNTEN] =
				devm_clk_get(&pdev->dev, "ftm_cnt_clk_en");
	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);

	/*
	 * ipg_clk is the interface clock for the IP. If not provided, use the
	 * ftm_sys clock as the default.
	 */
	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(fpc->ipg_clk))
		fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];

	chip->ops = &fsl_pwm_ops;

	ret = devm_pwmchip_add(&pdev->dev, chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, chip);

	return fsl_pwm_init(fpc);
}

#ifdef CONFIG_PM_SLEEP
static int fsl_pwm_suspend(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	int i;

	regcache_cache_only(fpc->regmap, true);
	regcache_mark_dirty(fpc->regmap);

	for (i = 0; i < chip->npwm; i++) {
		struct pwm_device *pwm = &chip->pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_disable_unprepare(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
		clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	}

	return 0;
}

static int fsl_pwm_resume(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	int i;

	for (i = 0; i < chip->npwm; i++) {
		struct pwm_device *pwm = &chip->pwms[i];

		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
			continue;

		clk_prepare_enable(fpc->ipg_clk);

		if (!pwm_is_enabled(pwm))
			continue;

		clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	}

	/* restore all registers from cache */
	regcache_cache_only(fpc->regmap, false);
	regcache_sync(fpc->regmap);

	return 0;
}
#endif

static const struct dev_pm_ops fsl_pwm_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
};

static const struct fsl_ftm_soc vf610_ftm_pwm = {
	.has_enable_bits = false,
};

static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	.has_enable_bits = true,
};

static const struct of_device_id fsl_pwm_dt_ids[] = {
	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);

static struct platform_driver fsl_pwm_driver = {
	.driver = {
		.name = "fsl-ftm-pwm",
		.of_match_table = fsl_pwm_dt_ids,
		.pm = &fsl_pwm_pm_ops,
	},
	.probe = fsl_pwm_probe,
};
module_platform_driver(fsl_pwm_driver);

MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
MODULE_ALIAS("platform:fsl-ftm-pwm");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
b505183b XL	2	/*
	3	* Freescale FlexTimer Module (FTM) PWM Driver
	4	*
	5	* Copyright 2012-2013 Freescale Semiconductor, Inc.
b505183b XL	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/err.h>
	10	#include <linux/io.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/mutex.h>
0a41b0c5	14	#include <linux/of.h>
b505183b	15	#include <linux/platform_device.h>
97d0b42e	16	#include <linux/pm.h>
b505183b	17	#include <linux/pwm.h>
42fa98a9	18	#include <linux/regmap.h>
b505183b	19	#include <linux/slab.h>
e590eb40	20	#include <linux/fsl/ftm.h>
b505183b	21
cd6d92d2	22	#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
b505183b XL	23
	24	enum fsl_pwm_clk {
	25	FSL_PWM_CLK_SYS,
	26	FSL_PWM_CLK_FIX,
	27	FSL_PWM_CLK_EXT,
	28	FSL_PWM_CLK_CNTEN,
	29	FSL_PWM_CLK_MAX
	30	};
	31
db6c51ab	32	struct fsl_ftm_soc {
	33	bool has_enable_bits;
	34	};
	35
3479bbd1 PH	36	struct fsl_pwm_periodcfg {
	37	enum fsl_pwm_clk clk_select;
	38	unsigned int clk_ps;
	39	unsigned int mod_period;
	40	};
	41
b505183b	42	struct fsl_pwm_chip {
b505183b	43	struct mutex lock;
42fa98a9	44	struct regmap *regmap;
b505183b	45
3479bbd1 PH	46	/* This value is valid iff a pwm is running */
3479bbd1 PH	47	struct fsl_pwm_periodcfg period;
b505183b	48
82a9c55a	49	struct clk *ipg_clk;
b505183b	50	struct clk *clk[FSL_PWM_CLK_MAX];
db6c51ab	51
db6c51ab	52	const struct fsl_ftm_soc *soc;
b505183b XL	53	};
	54
	55	static inline struct fsl_pwm_chip to_fsl_chip(struct pwm_chip chip)
	56	{
2e8d68c0	57	return pwmchip_get_drvdata(chip);
b505183b XL	58	}
b505183b XL	59
a2a28229 PH	60	static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
	61	{
	62	u32 val;
	63
	64	regmap_read(fpc->regmap, FTM_FMS, &val);
	65	if (val & FTM_FMS_WPEN)
c637d87a	66	regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
a2a28229 PH	67	}
	68
	69	static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
	70	{
c637d87a	71	regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
a2a28229 PH	72	}
a2a28229 PH	73
3479bbd1 PH	74	static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
	75	const struct fsl_pwm_periodcfg *b)
	76	{
	77	if (a->clk_select != b->clk_select)
	78	return false;
	79	if (a->clk_ps != b->clk_ps)
	80	return false;
	81	if (a->mod_period != b->mod_period)
	82	return false;
	83	return true;
	84	}
	85
b505183b XL	86	static int fsl_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
b505183b XL	87	{
db6c51ab	88	int ret;
b505183b XL	89	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
b505183b XL	90
db6c51ab	91	ret = clk_prepare_enable(fpc->ipg_clk);
	92	if (!ret && fpc->soc->has_enable_bits) {
	93	mutex_lock(&fpc->lock);
c637d87a	94	regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
db6c51ab	95	mutex_unlock(&fpc->lock);
	96	}
	97
	98	return ret;
b505183b XL	99	}
	100
	101	static void fsl_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	102	{
	103	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
	104
db6c51ab	105	if (fpc->soc->has_enable_bits) {
db6c51ab	106	mutex_lock(&fpc->lock);
c637d87a	107	regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
db6c51ab	108	mutex_unlock(&fpc->lock);
	109	}
	110
82a9c55a	111	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	112	}
b505183b XL	113
3479bbd1 PH	114	static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
3479bbd1 PH	115	unsigned int ticks)
b505183b	116	{
3479bbd1 PH	117	unsigned long rate;
	118	unsigned long long exval;
	119
	120	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
	121	exval = ticks;
	122	exval *= 1000000000UL;
	123	do_div(exval, rate >> fpc->period.clk_ps);
	124	return exval;
b505183b XL	125	}
b505183b XL	126
3479bbd1 PH	127	static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
	128	unsigned int period_ns,
	129	enum fsl_pwm_clk index,
	130	struct fsl_pwm_periodcfg *periodcfg
	131	)
b505183b	132	{
3479bbd1 PH	133	unsigned long long c;
3479bbd1 PH	134	unsigned int ps;
b505183b	135
3479bbd1	136	c = clk_get_rate(fpc->clk[index]);
b505183b XL	137	c = c * period_ns;
	138	do_div(c, 1000000000UL);
	139
3479bbd1 PH	140	if (c == 0)
3479bbd1 PH	141	return false;
b505183b	142
3479bbd1 PH	143	for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
	144	if (c <= 0x10000) {
	145	periodcfg->clk_select = index;
	146	periodcfg->clk_ps = ps;
	147	periodcfg->mod_period = c - 1;
	148	return true;
	149	}
b505183b	150	}
3479bbd1	151	return false;
b505183b XL	152	}
b505183b XL	153
3479bbd1 PH	154	static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
	155	unsigned int period_ns,
	156	struct fsl_pwm_periodcfg *periodcfg)
b505183b XL	157	{
b505183b XL	158	enum fsl_pwm_clk m0, m1;
3479bbd1 PH	159	unsigned long fix_rate, ext_rate;
3479bbd1 PH	160	bool ret;
b505183b	161
3479bbd1 PH	162	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
	163	periodcfg);
	164	if (ret)
	165	return true;
b505183b XL	166
	167	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
	168	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
	169
	170	if (fix_rate > ext_rate) {
	171	m0 = FSL_PWM_CLK_FIX;
	172	m1 = FSL_PWM_CLK_EXT;
	173	} else {
	174	m0 = FSL_PWM_CLK_EXT;
	175	m1 = FSL_PWM_CLK_FIX;
	176	}
	177
3479bbd1 PH	178	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
	179	if (ret)
	180	return true;
b505183b	181
3479bbd1	182	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
b505183b XL	183	}
b505183b XL	184
3479bbd1 PH	185	static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
3479bbd1 PH	186	unsigned int duty_ns)
b505183b	187	{
42fa98a9	188	unsigned long long duty;
b505183b	189
3479bbd1 PH	190	unsigned int period = fpc->period.mod_period + 1;
	191	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
	192
	193	duty = (unsigned long long)duty_ns * period;
b505183b XL	194	do_div(duty, period_ns);
b505183b XL	195
3479bbd1	196	return (unsigned int)duty;
b505183b XL	197	}
b505183b XL	198
3479bbd1 PH	199	static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
3479bbd1 PH	200	struct pwm_device *pwm)
b505183b	201	{
3479bbd1	202	u32 val;
b505183b	203
3479bbd1 PH	204	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	205	if (~val & 0xFF)
	206	return true;
	207	else
	208	return false;
	209	}
	210
	211	static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
	212	struct pwm_device *pwm)
	213	{
	214	u32 val;
b505183b	215
3479bbd1 PH	216	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
	217	if (~(val \| BIT(pwm->hwpwm)) & 0xFF)
	218	return true;
	219	else
	220	return false;
	221	}
	222
e80c1aa6	223	static int fsl_pwm_apply_config(struct pwm_chip *chip,
3479bbd1	224	struct pwm_device *pwm,
71523d18	225	const struct pwm_state *newstate)
3479bbd1	226	{
e80c1aa6	227	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
3479bbd1 PH	228	unsigned int duty;
3479bbd1 PH	229	u32 reg_polarity;
b505183b	230
3479bbd1 PH	231	struct fsl_pwm_periodcfg periodcfg;
	232	bool do_write_period = false;
	233
	234	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
74836319	235	dev_err(pwmchip_parent(chip), "failed to calculate new period\n");
3479bbd1 PH	236	return -EINVAL;
	237	}
	238
	239	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
	240	do_write_period = true;
b505183b XL	241	/*
b505183b XL	242	* The Freescale FTM controller supports only a single period for
3479bbd1 PH	243	* all PWM channels, therefore verify if the newly computed period
	244	* is different than the current period being used. In such case
	245	* we allow to change the period only if no other pwm is running.
b505183b	246	*/
3479bbd1 PH	247	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
3479bbd1 PH	248	if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
74836319	249	dev_err(pwmchip_parent(chip),
3479bbd1 PH	250	"Cannot change period for PWM %u, disable other PWMs first\n",
	251	pwm->hwpwm);
	252	return -EBUSY;
b505183b	253	}
3479bbd1 PH	254	if (fpc->period.clk_select != periodcfg.clk_select) {
	255	int ret;
	256	enum fsl_pwm_clk oldclk = fpc->period.clk_select;
	257	enum fsl_pwm_clk newclk = periodcfg.clk_select;
	258
	259	ret = clk_prepare_enable(fpc->clk[newclk]);
	260	if (ret)
	261	return ret;
	262	clk_disable_unprepare(fpc->clk[oldclk]);
	263	}
	264	do_write_period = true;
b505183b XL	265	}
b505183b XL	266
a2a28229	267	ftm_clear_write_protection(fpc);
b505183b	268
3479bbd1 PH	269	if (do_write_period) {
	270	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
	271	FTM_SC_CLK(periodcfg.clk_select));
42fa98a9	272	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
3479bbd1 PH	273	periodcfg.clk_ps);
3479bbd1 PH	274	regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
b505183b	275
3479bbd1	276	fpc->period = periodcfg;
b505183b XL	277	}
b505183b XL	278
3479bbd1	279	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
b505183b	280
42fa98a9 XL	281	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
	282	FTM_CSC_MSB \| FTM_CSC_ELSB);
	283	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
b505183b	284
3479bbd1 PH	285	reg_polarity = 0;
	286	if (newstate->polarity == PWM_POLARITY_INVERSED)
	287	reg_polarity = BIT(pwm->hwpwm);
b505183b	288
3479bbd1	289	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
b505183b	290
a2a28229	291	ftm_set_write_protection(fpc);
b505183b XL	292
	293	return 0;
	294	}
	295
3479bbd1	296	static int fsl_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	297	const struct pwm_state *newstate)
b505183b XL	298	{
b505183b XL	299	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
3479bbd1 PH	300	struct pwm_state *oldstate = &pwm->state;
3479bbd1 PH	301	int ret = 0;
b505183b	302
3479bbd1 PH	303	/*
	304	* oldstate to newstate : action
	305	*
	306	* disabled to disabled : ignore
	307	* enabled to disabled : disable
	308	* enabled to enabled : update settings
	309	* disabled to enabled : update settings + enable
	310	*/
b505183b	311
3479bbd1	312	mutex_lock(&fpc->lock);
b505183b	313
3479bbd1 PH	314	if (!newstate->enabled) {
3479bbd1 PH	315	if (oldstate->enabled) {
c637d87a UKK	316	regmap_set_bits(fpc->regmap, FTM_OUTMASK,
c637d87a UKK	317	BIT(pwm->hwpwm));
3479bbd1 PH	318	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
	319	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
	320	}
b505183b	321
3479bbd1 PH	322	goto end_mutex;
3479bbd1 PH	323	}
b505183b	324
e80c1aa6	325	ret = fsl_pwm_apply_config(chip, pwm, newstate);
3479bbd1 PH	326	if (ret)
	327	goto end_mutex;
	328
	329	/* check if need to enable */
	330	if (!oldstate->enabled) {
	331	ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
	332	if (ret)
3d25025c	333	goto end_mutex;
3479bbd1 PH	334
	335	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	336	if (ret) {
	337	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
3d25025c	338	goto end_mutex;
3479bbd1	339	}
b505183b	340
c637d87a	341	regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
3479bbd1	342	}
b505183b	343
3479bbd1	344	end_mutex:
b505183b	345	mutex_unlock(&fpc->lock);
3479bbd1	346	return ret;
b505183b XL	347	}
	348
	349	static const struct pwm_ops fsl_pwm_ops = {
	350	.request = fsl_pwm_request,
	351	.free = fsl_pwm_free,
3479bbd1	352	.apply = fsl_pwm_apply,
b505183b XL	353	};
	354
	355	static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
	356	{
	357	int ret;
	358
82a9c55a	359	ret = clk_prepare_enable(fpc->ipg_clk);
b505183b XL	360	if (ret)
	361	return ret;
	362
42fa98a9 XL	363	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
	364	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
	365	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
b505183b	366
82a9c55a	367	clk_disable_unprepare(fpc->ipg_clk);
b505183b XL	368
	369	return 0;
	370	}
	371
49599cf6 XL	372	static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
	373	{
	374	switch (reg) {
a2a28229 PH	375	case FTM_FMS:
a2a28229 PH	376	case FTM_MODE:
49599cf6 XL	377	case FTM_CNT:
	378	return true;
	379	}
	380	return false;
	381	}
	382
42fa98a9 XL	383	static const struct regmap_config fsl_pwm_regmap_config = {
	384	.reg_bits = 32,
	385	.reg_stride = 4,
	386	.val_bits = 32,
	387
	388	.max_register = FTM_PWMLOAD,
49599cf6	389	.volatile_reg = fsl_pwm_volatile_reg,
ad06fdee	390	.cache_type = REGCACHE_FLAT,
42fa98a9 XL	391	};
42fa98a9 XL	392
b505183b XL	393	static int fsl_pwm_probe(struct platform_device *pdev)
b505183b XL	394	{
097779f1	395	struct pwm_chip *chip;
b505183b	396	struct fsl_pwm_chip *fpc;
42fa98a9	397	void __iomem *base;
b505183b XL	398	int ret;
b505183b XL	399
2e8d68c0 UKK	400	chip = devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*fpc));
	401	if (IS_ERR(chip))
	402	return PTR_ERR(chip);
	403	fpc = to_fsl_chip(chip);
b505183b XL	404
	405	mutex_init(&fpc->lock);
	406
db6c51ab	407	fpc->soc = of_device_get_match_data(&pdev->dev);
b505183b	408
e9534031	409	base = devm_platform_ioremap_resource(pdev, 0);
42fa98a9 XL	410	if (IS_ERR(base))
	411	return PTR_ERR(base);
	412
97d0b42e	413	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
42fa98a9 XL	414	&fsl_pwm_regmap_config);
	415	if (IS_ERR(fpc->regmap)) {
	416	dev_err(&pdev->dev, "regmap init failed\n");
	417	return PTR_ERR(fpc->regmap);
	418	}
b505183b XL	419
	420	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
	421	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
	422	dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
	423	return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
	424	}
	425
097779f1	426	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(&pdev->dev, "ftm_fix");
b505183b XL	427	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
	428	return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
	429
097779f1	430	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(&pdev->dev, "ftm_ext");
b505183b XL	431	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
	432	return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
	433
	434	fpc->clk[FSL_PWM_CLK_CNTEN] =
097779f1	435	devm_clk_get(&pdev->dev, "ftm_cnt_clk_en");
b505183b XL	436	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
	437	return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
	438
82a9c55a	439	/*
	440	* ipg_clk is the interface clock for the IP. If not provided, use the
	441	* ftm_sys clock as the default.
	442	*/
	443	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	444	if (IS_ERR(fpc->ipg_clk))
	445	fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
	446
097779f1	447	chip->ops = &fsl_pwm_ops;
b505183b	448
097779f1	449	ret = devm_pwmchip_add(&pdev->dev, chip);
b505183b XL	450	if (ret < 0) {
	451	dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
	452	return ret;
	453	}
	454
097779f1	455	platform_set_drvdata(pdev, chip);
b505183b XL	456
	457	return fsl_pwm_init(fpc);
	458	}
	459
97d0b42e XL	460	#ifdef CONFIG_PM_SLEEP
	461	static int fsl_pwm_suspend(struct device *dev)
	462	{
097779f1 UKK	463	struct pwm_chip *chip = dev_get_drvdata(dev);
097779f1 UKK	464	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
816aec23	465	int i;
97d0b42e XL	466
	467	regcache_cache_only(fpc->regmap, true);
	468	regcache_mark_dirty(fpc->regmap);
	469
097779f1 UKK	470	for (i = 0; i < chip->npwm; i++) {
097779f1 UKK	471	struct pwm_device *pwm = &chip->pwms[i];
816aec23 SA	472
	473	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	474	continue;
	475
82a9c55a	476	clk_disable_unprepare(fpc->ipg_clk);
816aec23 SA	477
	478	if (!pwm_is_enabled(pwm))
	479	continue;
	480
97d0b42e	481	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
3479bbd1	482	clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
97d0b42e XL	483	}
	484
	485	return 0;
	486	}
	487
	488	static int fsl_pwm_resume(struct device *dev)
	489	{
097779f1 UKK	490	struct pwm_chip *chip = dev_get_drvdata(dev);
097779f1 UKK	491	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
816aec23 SA	492	int i;
816aec23 SA	493
097779f1 UKK	494	for (i = 0; i < chip->npwm; i++) {
097779f1 UKK	495	struct pwm_device *pwm = &chip->pwms[i];
816aec23 SA	496
	497	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
	498	continue;
97d0b42e	499
82a9c55a	500	clk_prepare_enable(fpc->ipg_clk);
816aec23 SA	501
	502	if (!pwm_is_enabled(pwm))
	503	continue;
	504
3479bbd1	505	clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
97d0b42e XL	506	clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
	507	}
	508
	509	/* restore all registers from cache */
	510	regcache_cache_only(fpc->regmap, false);
	511	regcache_sync(fpc->regmap);
	512
	513	return 0;
	514	}
	515	#endif
	516
	517	static const struct dev_pm_ops fsl_pwm_pm_ops = {
	518	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
	519	};
	520
db6c51ab	521	static const struct fsl_ftm_soc vf610_ftm_pwm = {
	522	.has_enable_bits = false,
	523	};
	524
2c4f2e32	525	static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
	526	.has_enable_bits = true,
	527	};
	528
b505183b	529	static const struct of_device_id fsl_pwm_dt_ids[] = {
db6c51ab	530	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
2c4f2e32	531	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
b505183b XL	532	{ /* sentinel */ }
	533	};
	534	MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
	535
	536	static struct platform_driver fsl_pwm_driver = {
	537	.driver = {
	538	.name = "fsl-ftm-pwm",
	539	.of_match_table = fsl_pwm_dt_ids,
97d0b42e	540	.pm = &fsl_pwm_pm_ops,
b505183b XL	541	},
b505183b XL	542	.probe = fsl_pwm_probe,
b505183b XL	543	};
	544	module_platform_driver(fsl_pwm_driver);
	545
	546	MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
	547	MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
	548	MODULE_ALIAS("platform:fsl-ftm-pwm");
	549	MODULE_LICENSE("GPL");