[linux-block.git] / drivers / pwm / pwm-ep93xx.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * PWM framework driver for Cirrus Logic EP93xx
 *
 * Copyright (c) 2009        Matthieu Crapet <mcrapet@gmail.com>
 * Copyright (c) 2009, 2013  H Hartley Sweeten <hsweeten@visionengravers.com>
 *
 * EP9301/02 have only one channel:
 *   platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
 *
 * EP9307 has only one channel:
 *   platform device ep93xx-pwm.0 - PWMOUT
 *
 * EP9312/15 have two channels:
 *   platform device ep93xx-pwm.0 - PWMOUT
 *   platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pwm.h>

#include <asm/div64.h>

#include <linux/soc/cirrus/ep93xx.h>	/* for ep93xx_pwm_{acquire,release}_gpio() */

#define EP93XX_PWMx_TERM_COUNT	0x00
#define EP93XX_PWMx_DUTY_CYCLE	0x04
#define EP93XX_PWMx_ENABLE	0x08
#define EP93XX_PWMx_INVERT	0x0c

struct ep93xx_pwm {
	void __iomem *base;
	struct clk *clk;
	struct pwm_chip chip;
};

static inline struct ep93xx_pwm *to_ep93xx_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct ep93xx_pwm, chip);
}

static int ep93xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct platform_device *pdev = to_platform_device(chip->dev);

	return ep93xx_pwm_acquire_gpio(pdev);
}

static void ep93xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct platform_device *pdev = to_platform_device(chip->dev);

	ep93xx_pwm_release_gpio(pdev);
}

static int ep93xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			    const struct pwm_state *state)
{
	int ret;
	struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
	bool enabled = state->enabled;
	void __iomem *base = ep93xx_pwm->base;
	unsigned long long c;
	unsigned long period_cycles;
	unsigned long duty_cycles;
	unsigned long term;

	if (state->polarity != pwm->state.polarity) {
		if (enabled) {
			writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
			clk_disable_unprepare(ep93xx_pwm->clk);
			enabled = false;
		}

		/*
		 * The clock needs to be enabled to access the PWM registers.
		 * Polarity can only be changed when the PWM is disabled.
		 */
		ret = clk_prepare_enable(ep93xx_pwm->clk);
		if (ret)
			return ret;

		if (state->polarity == PWM_POLARITY_INVERSED)
			writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
		else
			writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_INVERT);

		clk_disable_unprepare(ep93xx_pwm->clk);
	}

	if (!state->enabled) {
		if (enabled) {
			writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
			clk_disable_unprepare(ep93xx_pwm->clk);
		}

		return 0;
	}

	/*
	 * The clock needs to be enabled to access the PWM registers.
	 * Configuration can be changed at any time.
	 */
	if (!pwm_is_enabled(pwm)) {
		ret = clk_prepare_enable(ep93xx_pwm->clk);
		if (ret)
			return ret;
	}

	c = clk_get_rate(ep93xx_pwm->clk);
	c *= state->period;
	do_div(c, 1000000000);
	period_cycles = c;

	c = period_cycles;
	c *= state->duty_cycle;
	do_div(c, state->period);
	duty_cycles = c;

	if (period_cycles < 0x10000 && duty_cycles < 0x10000) {
		term = readw(base + EP93XX_PWMx_TERM_COUNT);

		/* Order is important if PWM is running */
		if (period_cycles > term) {
			writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
			writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
		} else {
			writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
			writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
		}
		ret = 0;
	} else {
		ret = -EINVAL;
	}

	if (!pwm_is_enabled(pwm))
		clk_disable_unprepare(ep93xx_pwm->clk);

	if (ret)
		return ret;

	if (!enabled) {
		ret = clk_prepare_enable(ep93xx_pwm->clk);
		if (ret)
			return ret;

		writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
	}

	return 0;
}

static const struct pwm_ops ep93xx_pwm_ops = {
	.request = ep93xx_pwm_request,
	.free = ep93xx_pwm_free,
	.apply = ep93xx_pwm_apply,
	.owner = THIS_MODULE,
};

static int ep93xx_pwm_probe(struct platform_device *pdev)
{
	struct ep93xx_pwm *ep93xx_pwm;
	int ret;

	ep93xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*ep93xx_pwm), GFP_KERNEL);
	if (!ep93xx_pwm)
		return -ENOMEM;

	ep93xx_pwm->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(ep93xx_pwm->base))
		return PTR_ERR(ep93xx_pwm->base);

	ep93xx_pwm->clk = devm_clk_get(&pdev->dev, "pwm_clk");
	if (IS_ERR(ep93xx_pwm->clk))
		return PTR_ERR(ep93xx_pwm->clk);

	ep93xx_pwm->chip.dev = &pdev->dev;
	ep93xx_pwm->chip.ops = &ep93xx_pwm_ops;
	ep93xx_pwm->chip.npwm = 1;

	ret = devm_pwmchip_add(&pdev->dev, &ep93xx_pwm->chip);
	if (ret < 0)
		return ret;

	return 0;
}

static struct platform_driver ep93xx_pwm_driver = {
	.driver = {
		.name = "ep93xx-pwm",
	},
	.probe = ep93xx_pwm_probe,
};
module_platform_driver(ep93xx_pwm_driver);

MODULE_DESCRIPTION("Cirrus Logic EP93xx PWM driver");
MODULE_AUTHOR("Matthieu Crapet <mcrapet@gmail.com>");
MODULE_AUTHOR("H Hartley Sweeten <hsweeten@visionengravers.com>");
MODULE_ALIAS("platform:ep93xx-pwm");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
a2308698 HS	2	/*
	3	* PWM framework driver for Cirrus Logic EP93xx
	4	*
	5	* Copyright (c) 2009 Matthieu Crapet <mcrapet@gmail.com>
	6	* Copyright (c) 2009, 2013 H Hartley Sweeten <hsweeten@visionengravers.com>
	7	*
	8	* EP9301/02 have only one channel:
	9	* platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
	10	*
	11	* EP9307 has only one channel:
	12	* platform device ep93xx-pwm.0 - PWMOUT
	13	*
	14	* EP9312/15 have two channels:
	15	* platform device ep93xx-pwm.0 - PWMOUT
	16	* platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
a2308698 HS	17	*/
	18
	19	#include <linux/module.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/slab.h>
	22	#include <linux/clk.h>
	23	#include <linux/err.h>
	24	#include <linux/io.h>
	25	#include <linux/pwm.h>
	26
	27	#include <asm/div64.h>
	28
67e38f57	29	#include <linux/soc/cirrus/ep93xx.h> /* for ep93xx_pwm_{acquire,release}_gpio() */
a2308698 HS	30
	31	#define EP93XX_PWMx_TERM_COUNT 0x00
	32	#define EP93XX_PWMx_DUTY_CYCLE 0x04
	33	#define EP93XX_PWMx_ENABLE 0x08
	34	#define EP93XX_PWMx_INVERT 0x0c
	35
	36	struct ep93xx_pwm {
	37	void __iomem *base;
	38	struct clk *clk;
	39	struct pwm_chip chip;
	40	};
	41
	42	static inline struct ep93xx_pwm to_ep93xx_pwm(struct pwm_chip chip)
	43	{
	44	return container_of(chip, struct ep93xx_pwm, chip);
	45	}
	46
	47	static int ep93xx_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	48	{
	49	struct platform_device *pdev = to_platform_device(chip->dev);
	50
	51	return ep93xx_pwm_acquire_gpio(pdev);
	52	}
	53
	54	static void ep93xx_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	55	{
	56	struct platform_device *pdev = to_platform_device(chip->dev);
	57
	58	ep93xx_pwm_release_gpio(pdev);
	59	}
	60
6d45374a UKK	61	static int ep93xx_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	62	const struct pwm_state *state)
	63	{
	64	int ret;
72cce47f	65	struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
6d45374a	66	bool enabled = state->enabled;
f4a8e31e UKK	67	void __iomem *base = ep93xx_pwm->base;
	68	unsigned long long c;
	69	unsigned long period_cycles;
	70	unsigned long duty_cycles;
	71	unsigned long term;
6d45374a UKK	72
	73	if (state->polarity != pwm->state.polarity) {
	74	if (enabled) {
72cce47f	75	writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
b235f8a3	76	clk_disable_unprepare(ep93xx_pwm->clk);
6d45374a UKK	77	enabled = false;
	78	}
	79
72cce47f UKK	80	/*
	81	* The clock needs to be enabled to access the PWM registers.
	82	* Polarity can only be changed when the PWM is disabled.
	83	*/
b235f8a3	84	ret = clk_prepare_enable(ep93xx_pwm->clk);
6d45374a UKK	85	if (ret)
6d45374a UKK	86	return ret;
72cce47f UKK	87
	88	if (state->polarity == PWM_POLARITY_INVERSED)
	89	writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
	90	else
	91	writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
	92
b235f8a3	93	clk_disable_unprepare(ep93xx_pwm->clk);
6d45374a UKK	94	}
	95
	96	if (!state->enabled) {
72cce47f UKK	97	if (enabled) {
72cce47f UKK	98	writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
b235f8a3	99	clk_disable_unprepare(ep93xx_pwm->clk);
72cce47f	100	}
6d45374a UKK	101
	102	return 0;
	103	}
	104
f4a8e31e UKK	105	/*
	106	* The clock needs to be enabled to access the PWM registers.
	107	* Configuration can be changed at any time.
	108	*/
	109	if (!pwm_is_enabled(pwm)) {
	110	ret = clk_prepare_enable(ep93xx_pwm->clk);
	111	if (ret)
	112	return ret;
	113	}
72cce47f	114
f4a8e31e UKK	115	c = clk_get_rate(ep93xx_pwm->clk);
	116	c *= state->period;
	117	do_div(c, 1000000000);
	118	period_cycles = c;
72cce47f	119
f4a8e31e UKK	120	c = period_cycles;
	121	c *= state->duty_cycle;
	122	do_div(c, state->period);
	123	duty_cycles = c;
	124
	125	if (period_cycles < 0x10000 && duty_cycles < 0x10000) {
	126	term = readw(base + EP93XX_PWMx_TERM_COUNT);
	127
	128	/* Order is important if PWM is running */
	129	if (period_cycles > term) {
	130	writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
	131	writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
72cce47f	132	} else {
f4a8e31e UKK	133	writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
f4a8e31e UKK	134	writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
72cce47f	135	}
f4a8e31e UKK	136	ret = 0;
	137	} else {
	138	ret = -EINVAL;
	139	}
72cce47f	140
f4a8e31e UKK	141	if (!pwm_is_enabled(pwm))
f4a8e31e UKK	142	clk_disable_unprepare(ep93xx_pwm->clk);
72cce47f	143
f4a8e31e UKK	144	if (ret)
f4a8e31e UKK	145	return ret;
6d45374a	146
72cce47f	147	if (!enabled) {
b235f8a3	148	ret = clk_prepare_enable(ep93xx_pwm->clk);
72cce47f UKK	149	if (ret)
	150	return ret;
	151
	152	writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
	153	}
6d45374a UKK	154
	155	return 0;
	156	}
	157
a2308698 HS	158	static const struct pwm_ops ep93xx_pwm_ops = {
	159	.request = ep93xx_pwm_request,
	160	.free = ep93xx_pwm_free,
6d45374a	161	.apply = ep93xx_pwm_apply,
a2308698 HS	162	.owner = THIS_MODULE,
	163	};
	164
	165	static int ep93xx_pwm_probe(struct platform_device *pdev)
	166	{
	167	struct ep93xx_pwm *ep93xx_pwm;
a2308698 HS	168	int ret;
	169
	170	ep93xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*ep93xx_pwm), GFP_KERNEL);
	171	if (!ep93xx_pwm)
	172	return -ENOMEM;
	173
fc0155f8	174	ep93xx_pwm->base = devm_platform_ioremap_resource(pdev, 0);
a2308698 HS	175	if (IS_ERR(ep93xx_pwm->base))
	176	return PTR_ERR(ep93xx_pwm->base);
	177
	178	ep93xx_pwm->clk = devm_clk_get(&pdev->dev, "pwm_clk");
	179	if (IS_ERR(ep93xx_pwm->clk))
	180	return PTR_ERR(ep93xx_pwm->clk);
	181
	182	ep93xx_pwm->chip.dev = &pdev->dev;
	183	ep93xx_pwm->chip.ops = &ep93xx_pwm_ops;
a2308698 HS	184	ep93xx_pwm->chip.npwm = 1;
a2308698 HS	185
a0b336a3	186	ret = devm_pwmchip_add(&pdev->dev, &ep93xx_pwm->chip);
a2308698 HS	187	if (ret < 0)
	188	return ret;
	189
a2308698 HS	190	return 0;
	191	}
	192
a2308698 HS	193	static struct platform_driver ep93xx_pwm_driver = {
	194	.driver = {
	195	.name = "ep93xx-pwm",
	196	},
	197	.probe = ep93xx_pwm_probe,
a2308698 HS	198	};
	199	module_platform_driver(ep93xx_pwm_driver);
	200
	201	MODULE_DESCRIPTION("Cirrus Logic EP93xx PWM driver");
5eabf82e JH	202	MODULE_AUTHOR("Matthieu Crapet <mcrapet@gmail.com>");
5eabf82e JH	203	MODULE_AUTHOR("H Hartley Sweeten <hsweeten@visionengravers.com>");
a2308698 HS	204	MODULE_ALIAS("platform:ep93xx-pwm");
a2308698 HS	205	MODULE_LICENSE("GPL");