projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 721ee188 BD |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * DesignWare PWM Controller driver | |
| 4 | * | |
| 5 | * Copyright (C) 2018-2020 Intel Corporation | |
| 6 | * | |
| 7 | * Author: Felipe Balbi (Intel) | |
| 8 | * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com> | |
| 9 | * Author: Raymond Tan <raymond.tan@intel.com> | |
| 10 | */ | |
| 11 | ||
| 12 | MODULE_IMPORT_NS(dwc_pwm); | |
| 13 | ||
| 14 | #define DWC_TIM_LD_CNT(n) ((n) * 0x14) | |
| 15 | #define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) | |
| 16 | #define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) | |
| 17 | #define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) | |
| 18 | #define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) | |
| 19 | #define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) | |
| 20 | ||
| 21 | #define DWC_TIMERS_INT_STS 0xa0 | |
| 22 | #define DWC_TIMERS_EOI 0xa4 | |
| 23 | #define DWC_TIMERS_RAW_INT_STS 0xa8 | |
| 24 | #define DWC_TIMERS_COMP_VERSION 0xac | |
| 25 | ||
| 26 | #define DWC_TIMERS_TOTAL 8 | |
| 721ee188 BD |
27 | |
| 28 | /* Timer Control Register */ | |
| 29 | #define DWC_TIM_CTRL_EN BIT(0) | |
| 30 | #define DWC_TIM_CTRL_MODE BIT(1) | |
| 31 | #define DWC_TIM_CTRL_MODE_FREE (0 << 1) | |
| 32 | #define DWC_TIM_CTRL_MODE_USER (1 << 1) | |
| 33 | #define DWC_TIM_CTRL_INT_MASK BIT(2) | |
| 34 | #define DWC_TIM_CTRL_PWM BIT(3) | |
| 35 | ||
| ebf2c89e RJ |
36 | struct dwc_pwm_info { |
| 37 | unsigned int nr; | |
| 38 | unsigned int size; | |
| 39 | }; | |
| 40 | ||
| 721ee188 BD |
41 | struct dwc_pwm_ctx { |
| 42 | u32 cnt; | |
| 43 | u32 cnt2; | |
| 44 | u32 ctrl; | |
| 45 | }; | |
| 46 | ||
| 47 | struct dwc_pwm { | |
| 721ee188 | 48 | void __iomem *base; |
| 81432e2e | 49 | unsigned int clk_ns; |
| 721ee188 BD |
50 | struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; |
| 51 | }; | |
| 1647e506 UKK |
52 | |
| 53 | static inline struct dwc_pwm *to_dwc_pwm(struct pwm_chip *chip) | |
| 54 | { | |
| 55 | return pwmchip_get_drvdata(chip); | |
| 56 | } | |
| 721ee188 BD |
57 | |
| 58 | static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) | |
| 59 | { | |
| 60 | return readl(dwc->base + offset); | |
| 61 | } | |
| 62 | ||
| 63 | static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset) | |
| 64 | { | |
| 65 | writel(value, dwc->base + offset); | |
| 66 | } | |
| 67 | ||
| aaa3cc29 | 68 | extern struct pwm_chip *dwc_pwm_alloc(struct device *dev); |