[linux-block.git] / drivers / pwm / pwm-dwc-core.c

// SPDX-License-Identifier: GPL-2.0
/*
 * DesignWare PWM Controller driver core
 *
 * Copyright (C) 2018-2020 Intel Corporation
 *
 * Author: Felipe Balbi (Intel)
 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
 * Author: Raymond Tan <raymond.tan@intel.com>
 */

#define DEFAULT_SYMBOL_NAMESPACE dwc_pwm

#include <linux/bitops.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include <linux/pwm.h>

#include "pwm-dwc.h"

static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled)
{
	u32 reg;

	reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm));

	if (enabled)
		reg |= DWC_TIM_CTRL_EN;
	else
		reg &= ~DWC_TIM_CTRL_EN;

	dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm));
}

static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
				     struct pwm_device *pwm,
				     const struct pwm_state *state)
{
	u64 tmp;
	u32 ctrl;
	u32 high;
	u32 low;

	/*
	 * Calculate width of low and high period in terms of input clock
	 * periods and check are the result within HW limits between 1 and
	 * 2^32 periods.
	 */
	tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns);
	if (tmp < 1 || tmp > (1ULL << 32))
		return -ERANGE;
	low = tmp - 1;

	tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
				    dwc->clk_ns);
	if (tmp < 1 || tmp > (1ULL << 32))
		return -ERANGE;
	high = tmp - 1;

	/*
	 * Specification says timer usage flow is to disable timer, then
	 * program it followed by enable. It also says Load Count is loaded
	 * into timer after it is enabled - either after a disable or
	 * a reset. Based on measurements it happens also without disable
	 * whenever Load Count is updated. But follow the specification.
	 */
	__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);

	/*
	 * Write Load Count and Load Count 2 registers. Former defines the
	 * width of low period and latter the width of high period in terms
	 * multiple of input clock periods:
	 * Width = ((Count + 1) * input clock period).
	 */
	dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm));
	dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm));

	/*
	 * Set user-defined mode, timer reloads from Load Count registers
	 * when it counts down to 0.
	 * Set PWM mode, it makes output to toggle and width of low and high
	 * periods are set by Load Count registers.
	 */
	ctrl = DWC_TIM_CTRL_MODE_USER | DWC_TIM_CTRL_PWM;
	dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm));

	/*
	 * Enable timer. Output starts from low period.
	 */
	__dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled);

	return 0;
}

static int dwc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *state)
{
	struct dwc_pwm *dwc = to_dwc_pwm(chip);

	if (state->polarity != PWM_POLARITY_INVERSED)
		return -EINVAL;

	if (state->enabled) {
		if (!pwm->state.enabled)
			pm_runtime_get_sync(pwmchip_parent(chip));
		return __dwc_pwm_configure_timer(dwc, pwm, state);
	} else {
		if (pwm->state.enabled) {
			__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
			pm_runtime_put_sync(pwmchip_parent(chip));
		}
	}

	return 0;
}

static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
			     struct pwm_state *state)
{
	struct dwc_pwm *dwc = to_dwc_pwm(chip);
	u64 duty, period;
	u32 ctrl, ld, ld2;

	pm_runtime_get_sync(pwmchip_parent(chip));

	ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm));
	ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
	ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));

	state->enabled = !!(ctrl & DWC_TIM_CTRL_EN);

	/*
	 * If we're not in PWM, technically the output is a 50-50
	 * based on the timer load-count only.
	 */
	if (ctrl & DWC_TIM_CTRL_PWM) {
		duty = (ld + 1) * dwc->clk_ns;
		period = (ld2 + 1)  * dwc->clk_ns;
		period += duty;
	} else {
		duty = (ld + 1) * dwc->clk_ns;
		period = duty * 2;
	}

	state->polarity = PWM_POLARITY_INVERSED;
	state->period = period;
	state->duty_cycle = duty;

	pm_runtime_put_sync(pwmchip_parent(chip));

	return 0;
}

static const struct pwm_ops dwc_pwm_ops = {
	.apply = dwc_pwm_apply,
	.get_state = dwc_pwm_get_state,
};

struct pwm_chip *dwc_pwm_alloc(struct device *dev)
{
	struct pwm_chip *chip;
	struct dwc_pwm *dwc;

	chip = devm_pwmchip_alloc(dev, DWC_TIMERS_TOTAL, sizeof(*dwc));
	if (IS_ERR(chip))
		return chip;
	dwc = to_dwc_pwm(chip);

	dwc->clk_ns = 10;
	chip->ops = &dwc_pwm_ops;

	return chip;
}
EXPORT_SYMBOL_GPL(dwc_pwm_alloc);

MODULE_AUTHOR("Felipe Balbi (Intel)");
MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
MODULE_DESCRIPTION("DesignWare PWM Controller");
MODULE_LICENSE("GPL");
Commit	Line	Data
721ee188 BD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* DesignWare PWM Controller driver core
	4	*
	5	* Copyright (C) 2018-2020 Intel Corporation
	6	*
	7	* Author: Felipe Balbi (Intel)
	8	* Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
	9	* Author: Raymond Tan <raymond.tan@intel.com>
	10	*/
	11
	12	#define DEFAULT_SYMBOL_NAMESPACE dwc_pwm
	13
	14	#include <linux/bitops.h>
	15	#include <linux/export.h>
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/pci.h>
	19	#include <linux/pm_runtime.h>
	20	#include <linux/pwm.h>
	21
	22	#include "pwm-dwc.h"
	23
	24	static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled)
	25	{
	26	u32 reg;
	27
	28	reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm));
	29
	30	if (enabled)
	31	reg \|= DWC_TIM_CTRL_EN;
	32	else
	33	reg &= ~DWC_TIM_CTRL_EN;
	34
	35	dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm));
	36	}
	37
	38	static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
	39	struct pwm_device *pwm,
	40	const struct pwm_state *state)
	41	{
	42	u64 tmp;
	43	u32 ctrl;
	44	u32 high;
	45	u32 low;
	46
	47	/*
	48	* Calculate width of low and high period in terms of input clock
	49	* periods and check are the result within HW limits between 1 and
	50	* 2^32 periods.
	51	*/
81432e2e	52	tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns);
721ee188 BD	53	if (tmp < 1 \|\| tmp > (1ULL << 32))
	54	return -ERANGE;
	55	low = tmp - 1;
	56
	57	tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
81432e2e	58	dwc->clk_ns);
721ee188 BD	59	if (tmp < 1 \|\| tmp > (1ULL << 32))
	60	return -ERANGE;
	61	high = tmp - 1;
	62
	63	/*
	64	* Specification says timer usage flow is to disable timer, then
	65	* program it followed by enable. It also says Load Count is loaded
	66	* into timer after it is enabled - either after a disable or
	67	* a reset. Based on measurements it happens also without disable
	68	* whenever Load Count is updated. But follow the specification.
	69	*/
	70	__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
	71
	72	/*
	73	* Write Load Count and Load Count 2 registers. Former defines the
	74	* width of low period and latter the width of high period in terms
	75	* multiple of input clock periods:
	76	* Width = ((Count + 1) * input clock period).
	77	*/
	78	dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm));
	79	dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm));
	80
	81	/*
	82	* Set user-defined mode, timer reloads from Load Count registers
	83	* when it counts down to 0.
	84	* Set PWM mode, it makes output to toggle and width of low and high
	85	* periods are set by Load Count registers.
	86	*/
	87	ctrl = DWC_TIM_CTRL_MODE_USER \| DWC_TIM_CTRL_PWM;
	88	dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm));
	89
	90	/*
	91	* Enable timer. Output starts from low period.
	92	*/
	93	__dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled);
	94
	95	return 0;
	96	}
	97
	98	static int dwc_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	99	const struct pwm_state *state)
	100	{
	101	struct dwc_pwm *dwc = to_dwc_pwm(chip);
	102
	103	if (state->polarity != PWM_POLARITY_INVERSED)
	104	return -EINVAL;
	105
	106	if (state->enabled) {
	107	if (!pwm->state.enabled)
4839f5a7	108	pm_runtime_get_sync(pwmchip_parent(chip));
721ee188 BD	109	return __dwc_pwm_configure_timer(dwc, pwm, state);
	110	} else {
	111	if (pwm->state.enabled) {
	112	__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
4839f5a7	113	pm_runtime_put_sync(pwmchip_parent(chip));
721ee188 BD	114	}
	115	}
	116
	117	return 0;
	118	}
	119
	120	static int dwc_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
	121	struct pwm_state *state)
	122	{
	123	struct dwc_pwm *dwc = to_dwc_pwm(chip);
	124	u64 duty, period;
4aff152d	125	u32 ctrl, ld, ld2;
721ee188	126
4839f5a7	127	pm_runtime_get_sync(pwmchip_parent(chip));
721ee188	128
4aff152d BD	129	ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm));
	130	ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
	131	ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
721ee188	132
4aff152d	133	state->enabled = !!(ctrl & DWC_TIM_CTRL_EN);
721ee188	134
4aff152d BD	135	/*
	136	* If we're not in PWM, technically the output is a 50-50
	137	* based on the timer load-count only.
	138	*/
	139	if (ctrl & DWC_TIM_CTRL_PWM) {
	140	duty = (ld + 1) * dwc->clk_ns;
	141	period = (ld2 + 1) * dwc->clk_ns;
	142	period += duty;
	143	} else {
	144	duty = (ld + 1) * dwc->clk_ns;
	145	period = duty * 2;
	146	}
721ee188 BD	147
721ee188 BD	148	state->polarity = PWM_POLARITY_INVERSED;
4aff152d BD	149	state->period = period;
4aff152d BD	150	state->duty_cycle = duty;
721ee188	151
4839f5a7	152	pm_runtime_put_sync(pwmchip_parent(chip));
721ee188 BD	153
	154	return 0;
	155	}
	156
	157	static const struct pwm_ops dwc_pwm_ops = {
	158	.apply = dwc_pwm_apply,
	159	.get_state = dwc_pwm_get_state,
	160	};
	161
aaa3cc29	162	struct pwm_chip dwc_pwm_alloc(struct device dev)
721ee188	163	{
aaa3cc29	164	struct pwm_chip *chip;
721ee188 BD	165	struct dwc_pwm *dwc;
721ee188 BD	166
1647e506 UKK	167	chip = devm_pwmchip_alloc(dev, DWC_TIMERS_TOTAL, sizeof(*dwc));
	168	if (IS_ERR(chip))
	169	return chip;
	170	dwc = to_dwc_pwm(chip);
721ee188	171
81432e2e	172	dwc->clk_ns = 10;
aaa3cc29	173	chip->ops = &dwc_pwm_ops;
721ee188	174
aaa3cc29	175	return chip;
721ee188 BD	176	}
	177	EXPORT_SYMBOL_GPL(dwc_pwm_alloc);
	178
	179	MODULE_AUTHOR("Felipe Balbi (Intel)");
	180	MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
	181	MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
	182	MODULE_DESCRIPTION("DesignWare PWM Controller");
	183	MODULE_LICENSE("GPL");