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4964cb52 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1f0d3bb0 | 2 | /* |
1f0d3bb0 | 3 | * Expose a PWM controlled by the ChromeOS EC to the host processor. |
4964cb52 EBS |
4 | * |
5 | * Copyright (C) 2016 Google, Inc. | |
1f0d3bb0 BN |
6 | */ |
7 | ||
8 | #include <linux/module.h> | |
840d9f13 EBS |
9 | #include <linux/platform_data/cros_ec_commands.h> |
10 | #include <linux/platform_data/cros_ec_proto.h> | |
1f0d3bb0 BN |
11 | #include <linux/platform_device.h> |
12 | #include <linux/pwm.h> | |
13 | #include <linux/slab.h> | |
14 | ||
15 | /** | |
16 | * struct cros_ec_pwm_device - Driver data for EC PWM | |
17 | * | |
18 | * @dev: Device node | |
19 | * @ec: Pointer to EC device | |
20 | * @chip: PWM controller chip | |
21 | */ | |
22 | struct cros_ec_pwm_device { | |
23 | struct device *dev; | |
24 | struct cros_ec_device *ec; | |
25 | struct pwm_chip chip; | |
26 | }; | |
27 | ||
1db37f95 TR |
28 | /** |
29 | * struct cros_ec_pwm - per-PWM driver data | |
30 | * @duty_cycle: cached duty cycle | |
31 | */ | |
32 | struct cros_ec_pwm { | |
33 | u16 duty_cycle; | |
34 | }; | |
35 | ||
1f0d3bb0 BN |
36 | static inline struct cros_ec_pwm_device *pwm_to_cros_ec_pwm(struct pwm_chip *c) |
37 | { | |
38 | return container_of(c, struct cros_ec_pwm_device, chip); | |
39 | } | |
40 | ||
1db37f95 TR |
41 | static int cros_ec_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) |
42 | { | |
43 | struct cros_ec_pwm *channel; | |
44 | ||
45 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); | |
46 | if (!channel) | |
47 | return -ENOMEM; | |
48 | ||
49 | pwm_set_chip_data(pwm, channel); | |
50 | ||
51 | return 0; | |
52 | } | |
53 | ||
54 | static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
55 | { | |
56 | struct cros_ec_pwm *channel = pwm_get_chip_data(pwm); | |
57 | ||
58 | kfree(channel); | |
59 | } | |
60 | ||
1f0d3bb0 BN |
61 | static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty) |
62 | { | |
63 | struct { | |
64 | struct cros_ec_command msg; | |
65 | struct ec_params_pwm_set_duty params; | |
065cfbbb | 66 | } __packed buf; |
1f0d3bb0 BN |
67 | struct ec_params_pwm_set_duty *params = &buf.params; |
68 | struct cros_ec_command *msg = &buf.msg; | |
69 | ||
70 | memset(&buf, 0, sizeof(buf)); | |
71 | ||
72 | msg->version = 0; | |
73 | msg->command = EC_CMD_PWM_SET_DUTY; | |
74 | msg->insize = 0; | |
75 | msg->outsize = sizeof(*params); | |
76 | ||
77 | params->duty = duty; | |
78 | params->pwm_type = EC_PWM_TYPE_GENERIC; | |
79 | params->index = index; | |
80 | ||
81 | return cros_ec_cmd_xfer_status(ec, msg); | |
82 | } | |
83 | ||
84 | static int __cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index, | |
85 | u32 *result) | |
86 | { | |
87 | struct { | |
88 | struct cros_ec_command msg; | |
89 | union { | |
90 | struct ec_params_pwm_get_duty params; | |
91 | struct ec_response_pwm_get_duty resp; | |
92 | }; | |
065cfbbb | 93 | } __packed buf; |
1f0d3bb0 BN |
94 | struct ec_params_pwm_get_duty *params = &buf.params; |
95 | struct ec_response_pwm_get_duty *resp = &buf.resp; | |
96 | struct cros_ec_command *msg = &buf.msg; | |
97 | int ret; | |
98 | ||
99 | memset(&buf, 0, sizeof(buf)); | |
100 | ||
101 | msg->version = 0; | |
102 | msg->command = EC_CMD_PWM_GET_DUTY; | |
e47866a1 NV |
103 | msg->insize = sizeof(*resp); |
104 | msg->outsize = sizeof(*params); | |
1f0d3bb0 BN |
105 | |
106 | params->pwm_type = EC_PWM_TYPE_GENERIC; | |
107 | params->index = index; | |
108 | ||
109 | ret = cros_ec_cmd_xfer_status(ec, msg); | |
110 | if (result) | |
111 | *result = msg->result; | |
112 | if (ret < 0) | |
113 | return ret; | |
114 | ||
115 | return resp->duty; | |
116 | } | |
117 | ||
118 | static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) | |
119 | { | |
120 | return __cros_ec_pwm_get_duty(ec, index, NULL); | |
121 | } | |
122 | ||
123 | static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, | |
71523d18 | 124 | const struct pwm_state *state) |
1f0d3bb0 BN |
125 | { |
126 | struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip); | |
1db37f95 TR |
127 | struct cros_ec_pwm *channel = pwm_get_chip_data(pwm); |
128 | u16 duty_cycle; | |
129 | int ret; | |
1f0d3bb0 BN |
130 | |
131 | /* The EC won't let us change the period */ | |
132 | if (state->period != EC_PWM_MAX_DUTY) | |
133 | return -EINVAL; | |
134 | ||
135 | /* | |
136 | * EC doesn't separate the concept of duty cycle and enabled, but | |
137 | * kernel does. Translate. | |
138 | */ | |
139 | duty_cycle = state->enabled ? state->duty_cycle : 0; | |
140 | ||
1db37f95 TR |
141 | ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle); |
142 | if (ret < 0) | |
143 | return ret; | |
144 | ||
145 | channel->duty_cycle = state->duty_cycle; | |
146 | ||
147 | return 0; | |
1f0d3bb0 BN |
148 | } |
149 | ||
150 | static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, | |
151 | struct pwm_state *state) | |
152 | { | |
153 | struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip); | |
1db37f95 | 154 | struct cros_ec_pwm *channel = pwm_get_chip_data(pwm); |
1f0d3bb0 BN |
155 | int ret; |
156 | ||
157 | ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm); | |
158 | if (ret < 0) { | |
159 | dev_err(chip->dev, "error getting initial duty: %d\n", ret); | |
160 | return; | |
161 | } | |
162 | ||
163 | state->enabled = (ret > 0); | |
164 | state->period = EC_PWM_MAX_DUTY; | |
165 | ||
1db37f95 TR |
166 | /* |
167 | * Note that "disabled" and "duty cycle == 0" are treated the same. If | |
168 | * the cached duty cycle is not zero, used the cached duty cycle. This | |
169 | * ensures that the configured duty cycle is kept across a disable and | |
170 | * enable operation and avoids potentially confusing consumers. | |
171 | * | |
172 | * For the case of the initial hardware readout, channel->duty_cycle | |
173 | * will be 0 and the actual duty cycle read from the EC is used. | |
174 | */ | |
175 | if (ret == 0 && channel->duty_cycle > 0) | |
176 | state->duty_cycle = channel->duty_cycle; | |
177 | else | |
178 | state->duty_cycle = ret; | |
1f0d3bb0 BN |
179 | } |
180 | ||
181 | static struct pwm_device * | |
182 | cros_ec_pwm_xlate(struct pwm_chip *pc, const struct of_phandle_args *args) | |
183 | { | |
184 | struct pwm_device *pwm; | |
185 | ||
186 | if (args->args[0] >= pc->npwm) | |
187 | return ERR_PTR(-EINVAL); | |
188 | ||
189 | pwm = pwm_request_from_chip(pc, args->args[0], NULL); | |
190 | if (IS_ERR(pwm)) | |
191 | return pwm; | |
192 | ||
193 | /* The EC won't let us change the period */ | |
194 | pwm->args.period = EC_PWM_MAX_DUTY; | |
195 | ||
196 | return pwm; | |
197 | } | |
198 | ||
199 | static const struct pwm_ops cros_ec_pwm_ops = { | |
1db37f95 TR |
200 | .request = cros_ec_pwm_request, |
201 | .free = cros_ec_pwm_free, | |
1f0d3bb0 BN |
202 | .get_state = cros_ec_pwm_get_state, |
203 | .apply = cros_ec_pwm_apply, | |
204 | .owner = THIS_MODULE, | |
205 | }; | |
206 | ||
207 | static int cros_ec_num_pwms(struct cros_ec_device *ec) | |
208 | { | |
209 | int i, ret; | |
210 | ||
211 | /* The index field is only 8 bits */ | |
212 | for (i = 0; i <= U8_MAX; i++) { | |
213 | u32 result = 0; | |
214 | ||
215 | ret = __cros_ec_pwm_get_duty(ec, i, &result); | |
216 | /* We want to parse EC protocol errors */ | |
217 | if (ret < 0 && !(ret == -EPROTO && result)) | |
218 | return ret; | |
219 | ||
220 | /* | |
221 | * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM | |
222 | * responses; everything else is treated as an error. | |
223 | */ | |
224 | if (result == EC_RES_INVALID_COMMAND) | |
225 | return -ENODEV; | |
226 | else if (result == EC_RES_INVALID_PARAM) | |
227 | return i; | |
228 | else if (result) | |
229 | return -EPROTO; | |
230 | } | |
231 | ||
232 | return U8_MAX; | |
233 | } | |
234 | ||
235 | static int cros_ec_pwm_probe(struct platform_device *pdev) | |
236 | { | |
237 | struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent); | |
238 | struct device *dev = &pdev->dev; | |
239 | struct cros_ec_pwm_device *ec_pwm; | |
240 | struct pwm_chip *chip; | |
241 | int ret; | |
242 | ||
243 | if (!ec) { | |
244 | dev_err(dev, "no parent EC device\n"); | |
245 | return -EINVAL; | |
246 | } | |
247 | ||
248 | ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL); | |
249 | if (!ec_pwm) | |
250 | return -ENOMEM; | |
251 | chip = &ec_pwm->chip; | |
252 | ec_pwm->ec = ec; | |
253 | ||
254 | /* PWM chip */ | |
255 | chip->dev = dev; | |
256 | chip->ops = &cros_ec_pwm_ops; | |
257 | chip->of_xlate = cros_ec_pwm_xlate; | |
258 | chip->of_pwm_n_cells = 1; | |
259 | chip->base = -1; | |
260 | ret = cros_ec_num_pwms(ec); | |
261 | if (ret < 0) { | |
262 | dev_err(dev, "Couldn't find PWMs: %d\n", ret); | |
263 | return ret; | |
264 | } | |
265 | chip->npwm = ret; | |
266 | dev_dbg(dev, "Probed %u PWMs\n", chip->npwm); | |
267 | ||
268 | ret = pwmchip_add(chip); | |
269 | if (ret < 0) { | |
270 | dev_err(dev, "cannot register PWM: %d\n", ret); | |
271 | return ret; | |
272 | } | |
273 | ||
274 | platform_set_drvdata(pdev, ec_pwm); | |
275 | ||
276 | return ret; | |
277 | } | |
278 | ||
279 | static int cros_ec_pwm_remove(struct platform_device *dev) | |
280 | { | |
281 | struct cros_ec_pwm_device *ec_pwm = platform_get_drvdata(dev); | |
282 | struct pwm_chip *chip = &ec_pwm->chip; | |
283 | ||
284 | return pwmchip_remove(chip); | |
285 | } | |
286 | ||
287 | #ifdef CONFIG_OF | |
288 | static const struct of_device_id cros_ec_pwm_of_match[] = { | |
289 | { .compatible = "google,cros-ec-pwm" }, | |
290 | {}, | |
291 | }; | |
292 | MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match); | |
293 | #endif | |
294 | ||
295 | static struct platform_driver cros_ec_pwm_driver = { | |
296 | .probe = cros_ec_pwm_probe, | |
297 | .remove = cros_ec_pwm_remove, | |
298 | .driver = { | |
299 | .name = "cros-ec-pwm", | |
300 | .of_match_table = of_match_ptr(cros_ec_pwm_of_match), | |
301 | }, | |
302 | }; | |
303 | module_platform_driver(cros_ec_pwm_driver); | |
304 | ||
305 | MODULE_ALIAS("platform:cros-ec-pwm"); | |
306 | MODULE_DESCRIPTION("ChromeOS EC PWM driver"); | |
307 | MODULE_LICENSE("GPL v2"); |