[linux-2.6-block.git] / drivers / pwm / pwm-bcm2835.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>

#define PWM_CONTROL		0x000
#define PWM_CONTROL_SHIFT(x)	((x) * 8)
#define PWM_CONTROL_MASK	0xff
#define PWM_MODE		0x80		/* set timer in PWM mode */
#define PWM_ENABLE		(1 << 0)
#define PWM_POLARITY		(1 << 4)

#define PERIOD(x)		(((x) * 0x10) + 0x10)
#define DUTY(x)			(((x) * 0x10) + 0x14)

#define PERIOD_MIN		0x2

struct bcm2835_pwm {
	void __iomem *base;
	struct clk *clk;
	unsigned long rate;
};

static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	u32 value;

	value = readl(pc->base + PWM_CONTROL);
	value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
	value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
	writel(value, pc->base + PWM_CONTROL);

	return 0;
}

static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	u32 value;

	value = readl(pc->base + PWM_CONTROL);
	value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
	writel(value, pc->base + PWM_CONTROL);
}

static int bcm2835_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			     const struct pwm_state *state)
{

	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	unsigned long long period_cycles;
	u64 max_period;

	u32 val;

	/*
	 * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
	 * must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
	 * multiplication period * rate doesn't overflow.
	 * To calculate the maximal possible period that guarantees the
	 * above inequality:
	 *
	 *     round(period * rate / NSEC_PER_SEC) <= U32_MAX
	 * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
	 * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
	 * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
	 * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
	 * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
	 */
	max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, pc->rate) - 1;

	if (state->period > max_period)
		return -EINVAL;

	/* set period */
	period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * pc->rate, NSEC_PER_SEC);

	/* don't accept a period that is too small */
	if (period_cycles < PERIOD_MIN)
		return -EINVAL;

	writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));

	/* set duty cycle */
	val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pc->rate, NSEC_PER_SEC);
	writel(val, pc->base + DUTY(pwm->hwpwm));

	/* set polarity */
	val = readl(pc->base + PWM_CONTROL);

	if (state->polarity == PWM_POLARITY_NORMAL)
		val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
	else
		val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);

	/* enable/disable */
	if (state->enabled)
		val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
	else
		val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));

	writel(val, pc->base + PWM_CONTROL);

	return 0;
}

static const struct pwm_ops bcm2835_pwm_ops = {
	.request = bcm2835_pwm_request,
	.free = bcm2835_pwm_free,
	.apply = bcm2835_pwm_apply,
};

static int bcm2835_pwm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct pwm_chip *chip;
	struct bcm2835_pwm *pc;
	int ret;

	chip = devm_pwmchip_alloc(dev, 2, sizeof(*pc));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	pc = to_bcm2835_pwm(chip);

	pc->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->base))
		return PTR_ERR(pc->base);

	pc->clk = devm_clk_get_enabled(dev, NULL);
	if (IS_ERR(pc->clk))
		return dev_err_probe(dev, PTR_ERR(pc->clk),
				     "clock not found\n");

	ret = devm_clk_rate_exclusive_get(dev, pc->clk);
	if (ret)
		return dev_err_probe(dev, ret,
				     "fail to get exclusive rate\n");

	pc->rate = clk_get_rate(pc->clk);
	if (!pc->rate)
		return dev_err_probe(dev, -EINVAL,
				     "failed to get clock rate\n");

	chip->ops = &bcm2835_pwm_ops;
	chip->atomic = true;

	platform_set_drvdata(pdev, pc);

	ret = devm_pwmchip_add(dev, chip);
	if (ret < 0)
		return dev_err_probe(dev, ret, "failed to add pwmchip\n");

	return 0;
}

static int bcm2835_pwm_suspend(struct device *dev)
{
	struct bcm2835_pwm *pc = dev_get_drvdata(dev);

	clk_disable_unprepare(pc->clk);

	return 0;
}

static int bcm2835_pwm_resume(struct device *dev)
{
	struct bcm2835_pwm *pc = dev_get_drvdata(dev);

	return clk_prepare_enable(pc->clk);
}

static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pwm_pm_ops, bcm2835_pwm_suspend,
				bcm2835_pwm_resume);

static const struct of_device_id bcm2835_pwm_of_match[] = {
	{ .compatible = "brcm,bcm2835-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);

static struct platform_driver bcm2835_pwm_driver = {
	.driver = {
		.name = "bcm2835-pwm",
		.of_match_table = bcm2835_pwm_of_match,
		.pm = pm_ptr(&bcm2835_pwm_pm_ops),
	},
	.probe = bcm2835_pwm_probe,
};
module_platform_driver(bcm2835_pwm_driver);

MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
e747cbe2	1	// SPDX-License-Identifier: GPL-2.0
e5a06dc5 BT	2	/*
e5a06dc5 BT	3	* Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
e5a06dc5 BT	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/err.h>
	8	#include <linux/io.h>
	9	#include <linux/module.h>
	10	#include <linux/of.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/pwm.h>
	13
	14	#define PWM_CONTROL 0x000
	15	#define PWM_CONTROL_SHIFT(x) ((x) * 8)
	16	#define PWM_CONTROL_MASK 0xff
	17	#define PWM_MODE 0x80 /* set timer in PWM mode */
	18	#define PWM_ENABLE (1 << 0)
	19	#define PWM_POLARITY (1 << 4)
	20
	21	#define PERIOD(x) (((x) * 0x10) + 0x10)
	22	#define DUTY(x) (((x) * 0x10) + 0x14)
	23
7e9713af	24	#define PERIOD_MIN 0x2
e5a06dc5 BT	25
e5a06dc5 BT	26	struct bcm2835_pwm {
e5a06dc5 BT	27	void __iomem *base;
e5a06dc5 BT	28	struct clk *clk;
fcc76072	29	unsigned long rate;
e5a06dc5 BT	30	};
	31
	32	static inline struct bcm2835_pwm to_bcm2835_pwm(struct pwm_chip chip)
	33	{
19c09ed0	34	return pwmchip_get_drvdata(chip);
e5a06dc5 BT	35	}
	36
	37	static int bcm2835_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	38	{
	39	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	40	u32 value;
	41
	42	value = readl(pc->base + PWM_CONTROL);
	43	value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
	44	value \|= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
	45	writel(value, pc->base + PWM_CONTROL);
	46
	47	return 0;
	48	}
	49
	50	static void bcm2835_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	51	{
	52	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	53	u32 value;
	54
	55	value = readl(pc->base + PWM_CONTROL);
	56	value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
	57	writel(value, pc->base + PWM_CONTROL);
	58	}
	59
2f81b51d LS	60	static int bcm2835_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
2f81b51d LS	61	const struct pwm_state *state)
e5a06dc5	62	{
2f81b51d	63
e5a06dc5	64	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
ca0d2fb7 UKK	65	unsigned long long period_cycles;
	66	u64 max_period;
	67
2f81b51d	68	u32 val;
fd13c144	69
ca0d2fb7 UKK	70	/*
	71	* period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
	72	* must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
	73	* multiplication period * rate doesn't overflow.
	74	* To calculate the maximal possible period that guarantees the
	75	* above inequality:
	76	*
	77	* round(period * rate / NSEC_PER_SEC) <= U32_MAX
	78	* <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
	79	* <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
	80	* <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
	81	* <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
	82	* <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
	83	*/
fcc76072	84	max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, pc->rate) - 1;
ca0d2fb7 UKK	85
	86	if (state->period > max_period)
	87	return -EINVAL;
	88
2f81b51d	89	/* set period */
fcc76072	90	period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * pc->rate, NSEC_PER_SEC);
e5a06dc5	91
ca0d2fb7 UKK	92	/* don't accept a period that is too small */
ca0d2fb7 UKK	93	if (period_cycles < PERIOD_MIN)
e5a06dc5	94	return -EINVAL;
e5a06dc5	95
ca0d2fb7	96	writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
e5a06dc5	97
2f81b51d	98	/* set duty cycle */
fcc76072	99	val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pc->rate, NSEC_PER_SEC);
2f81b51d	100	writel(val, pc->base + DUTY(pwm->hwpwm));
e5a06dc5	101
2f81b51d LS	102	/* set polarity */
2f81b51d LS	103	val = readl(pc->base + PWM_CONTROL);
e5a06dc5	104
2f81b51d LS	105	if (state->polarity == PWM_POLARITY_NORMAL)
	106	val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
	107	else
	108	val \|= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
e5a06dc5	109
2f81b51d LS	110	/* enable/disable */
	111	if (state->enabled)
	112	val \|= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
e5a06dc5	113	else
2f81b51d	114	val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
e5a06dc5	115
2f81b51d	116	writel(val, pc->base + PWM_CONTROL);
e5a06dc5 BT	117
	118	return 0;
	119	}
	120
	121	static const struct pwm_ops bcm2835_pwm_ops = {
	122	.request = bcm2835_pwm_request,
	123	.free = bcm2835_pwm_free,
2f81b51d	124	.apply = bcm2835_pwm_apply,
e5a06dc5 BT	125	};
	126
	127	static int bcm2835_pwm_probe(struct platform_device *pdev)
	128	{
664d8dbb	129	struct device *dev = &pdev->dev;
19c09ed0	130	struct pwm_chip *chip;
e5a06dc5	131	struct bcm2835_pwm *pc;
e5a06dc5 BT	132	int ret;
e5a06dc5 BT	133
664d8dbb	134	chip = devm_pwmchip_alloc(dev, 2, sizeof(*pc));
19c09ed0 UKK	135	if (IS_ERR(chip))
	136	return PTR_ERR(chip);
	137	pc = to_bcm2835_pwm(chip);
e5a06dc5	138
f57e7d25	139	pc->base = devm_platform_ioremap_resource(pdev, 0);
e5a06dc5 BT	140	if (IS_ERR(pc->base))
	141	return PTR_ERR(pc->base);
	142
664d8dbb	143	pc->clk = devm_clk_get_enabled(dev, NULL);
85a5745f	144	if (IS_ERR(pc->clk))
664d8dbb	145	return dev_err_probe(dev, PTR_ERR(pc->clk),
85a5745f	146	"clock not found\n");
e5a06dc5	147
141a8502	148	ret = devm_clk_rate_exclusive_get(dev, pc->clk);
fcc76072	149	if (ret)
664d8dbb	150	return dev_err_probe(dev, ret,
fcc76072 SY	151	"fail to get exclusive rate\n");
fcc76072 SY	152
fcc76072 SY	153	pc->rate = clk_get_rate(pc->clk);
fcc76072 SY	154	if (!pc->rate)
664d8dbb	155	return dev_err_probe(dev, -EINVAL,
fcc76072 SY	156	"failed to get clock rate\n");
fcc76072 SY	157
19c09ed0 UKK	158	chip->ops = &bcm2835_pwm_ops;
19c09ed0 UKK	159	chip->atomic = true;
e5a06dc5	160
4e7a8dbd FF	161	platform_set_drvdata(pdev, pc);
4e7a8dbd FF	162
664d8dbb	163	ret = devm_pwmchip_add(dev, chip);
e5a06dc5	164	if (ret < 0)
664d8dbb	165	return dev_err_probe(dev, ret, "failed to add pwmchip\n");
e5a06dc5 BT	166
e5a06dc5 BT	167	return 0;
e5a06dc5 BT	168	}
e5a06dc5 BT	169
119a508c FF	170	static int bcm2835_pwm_suspend(struct device *dev)
	171	{
	172	struct bcm2835_pwm *pc = dev_get_drvdata(dev);
	173
	174	clk_disable_unprepare(pc->clk);
	175
	176	return 0;
	177	}
	178
	179	static int bcm2835_pwm_resume(struct device *dev)
	180	{
	181	struct bcm2835_pwm *pc = dev_get_drvdata(dev);
	182
	183	return clk_prepare_enable(pc->clk);
	184	}
	185
	186	static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pwm_pm_ops, bcm2835_pwm_suspend,
	187	bcm2835_pwm_resume);
	188
e5a06dc5 BT	189	static const struct of_device_id bcm2835_pwm_of_match[] = {
	190	{ .compatible = "brcm,bcm2835-pwm", },
	191	{ /* sentinel */ }
	192	};
	193	MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
	194
	195	static struct platform_driver bcm2835_pwm_driver = {
	196	.driver = {
	197	.name = "bcm2835-pwm",
	198	.of_match_table = bcm2835_pwm_of_match,
119a508c	199	.pm = pm_ptr(&bcm2835_pwm_pm_ops),
e5a06dc5 BT	200	},
e5a06dc5 BT	201	.probe = bcm2835_pwm_probe,
e5a06dc5 BT	202	};
	203	module_platform_driver(bcm2835_pwm_driver);
	204
6ef7d1c4	205	MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
e5a06dc5 BT	206	MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
e5a06dc5 BT	207	MODULE_LICENSE("GPL v2");