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e747cbe2 | 1 | // SPDX-License-Identifier: GPL-2.0 |
e5a06dc5 BT |
2 | /* |
3 | * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be> | |
e5a06dc5 BT |
4 | */ |
5 | ||
6 | #include <linux/clk.h> | |
7 | #include <linux/err.h> | |
8 | #include <linux/io.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/of.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/pwm.h> | |
13 | ||
14 | #define PWM_CONTROL 0x000 | |
15 | #define PWM_CONTROL_SHIFT(x) ((x) * 8) | |
16 | #define PWM_CONTROL_MASK 0xff | |
17 | #define PWM_MODE 0x80 /* set timer in PWM mode */ | |
18 | #define PWM_ENABLE (1 << 0) | |
19 | #define PWM_POLARITY (1 << 4) | |
20 | ||
21 | #define PERIOD(x) (((x) * 0x10) + 0x10) | |
22 | #define DUTY(x) (((x) * 0x10) + 0x14) | |
23 | ||
7e9713af | 24 | #define PERIOD_MIN 0x2 |
e5a06dc5 BT |
25 | |
26 | struct bcm2835_pwm { | |
27 | struct pwm_chip chip; | |
28 | struct device *dev; | |
e5a06dc5 BT |
29 | void __iomem *base; |
30 | struct clk *clk; | |
31 | }; | |
32 | ||
33 | static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip) | |
34 | { | |
35 | return container_of(chip, struct bcm2835_pwm, chip); | |
36 | } | |
37 | ||
38 | static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) | |
39 | { | |
40 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
41 | u32 value; | |
42 | ||
43 | value = readl(pc->base + PWM_CONTROL); | |
44 | value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
45 | value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
46 | writel(value, pc->base + PWM_CONTROL); | |
47 | ||
48 | return 0; | |
49 | } | |
50 | ||
51 | static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
52 | { | |
53 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
54 | u32 value; | |
55 | ||
56 | value = readl(pc->base + PWM_CONTROL); | |
57 | value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
58 | writel(value, pc->base + PWM_CONTROL); | |
59 | } | |
60 | ||
61 | static int bcm2835_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
62 | int duty_ns, int period_ns) | |
63 | { | |
64 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
fd13c144 SW |
65 | unsigned long rate = clk_get_rate(pc->clk); |
66 | unsigned long scaler; | |
7e9713af | 67 | u32 period; |
fd13c144 SW |
68 | |
69 | if (!rate) { | |
70 | dev_err(pc->dev, "failed to get clock rate\n"); | |
71 | return -EINVAL; | |
72 | } | |
73 | ||
11fc4edc | 74 | scaler = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate); |
7e9713af | 75 | period = DIV_ROUND_CLOSEST(period_ns, scaler); |
e5a06dc5 | 76 | |
7e9713af | 77 | if (period < PERIOD_MIN) |
e5a06dc5 | 78 | return -EINVAL; |
e5a06dc5 | 79 | |
11fc4edc SY |
80 | writel(DIV_ROUND_CLOSEST(duty_ns, scaler), |
81 | pc->base + DUTY(pwm->hwpwm)); | |
7e9713af | 82 | writel(period, pc->base + PERIOD(pwm->hwpwm)); |
e5a06dc5 BT |
83 | |
84 | return 0; | |
85 | } | |
86 | ||
87 | static int bcm2835_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
88 | { | |
89 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
90 | u32 value; | |
91 | ||
92 | value = readl(pc->base + PWM_CONTROL); | |
93 | value |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm); | |
94 | writel(value, pc->base + PWM_CONTROL); | |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | static void bcm2835_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
100 | { | |
101 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
102 | u32 value; | |
103 | ||
104 | value = readl(pc->base + PWM_CONTROL); | |
105 | value &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
106 | writel(value, pc->base + PWM_CONTROL); | |
107 | } | |
108 | ||
109 | static int bcm2835_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, | |
110 | enum pwm_polarity polarity) | |
111 | { | |
112 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
113 | u32 value; | |
114 | ||
115 | value = readl(pc->base + PWM_CONTROL); | |
116 | ||
117 | if (polarity == PWM_POLARITY_NORMAL) | |
118 | value &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
119 | else | |
120 | value |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm); | |
121 | ||
122 | writel(value, pc->base + PWM_CONTROL); | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | static const struct pwm_ops bcm2835_pwm_ops = { | |
128 | .request = bcm2835_pwm_request, | |
129 | .free = bcm2835_pwm_free, | |
130 | .config = bcm2835_pwm_config, | |
131 | .enable = bcm2835_pwm_enable, | |
132 | .disable = bcm2835_pwm_disable, | |
133 | .set_polarity = bcm2835_set_polarity, | |
134 | .owner = THIS_MODULE, | |
135 | }; | |
136 | ||
137 | static int bcm2835_pwm_probe(struct platform_device *pdev) | |
138 | { | |
139 | struct bcm2835_pwm *pc; | |
140 | struct resource *res; | |
141 | int ret; | |
142 | ||
143 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); | |
144 | if (!pc) | |
145 | return -ENOMEM; | |
146 | ||
147 | pc->dev = &pdev->dev; | |
148 | ||
149 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
150 | pc->base = devm_ioremap_resource(&pdev->dev, res); | |
151 | if (IS_ERR(pc->base)) | |
152 | return PTR_ERR(pc->base); | |
153 | ||
154 | pc->clk = devm_clk_get(&pdev->dev, NULL); | |
155 | if (IS_ERR(pc->clk)) { | |
9e3ca01f SW |
156 | ret = PTR_ERR(pc->clk); |
157 | if (ret != -EPROBE_DEFER) | |
158 | dev_err(&pdev->dev, "clock not found: %d\n", ret); | |
159 | ||
160 | return ret; | |
e5a06dc5 BT |
161 | } |
162 | ||
163 | ret = clk_prepare_enable(pc->clk); | |
164 | if (ret) | |
165 | return ret; | |
166 | ||
e5a06dc5 BT |
167 | pc->chip.dev = &pdev->dev; |
168 | pc->chip.ops = &bcm2835_pwm_ops; | |
2c25b07e | 169 | pc->chip.base = -1; |
e5a06dc5 | 170 | pc->chip.npwm = 2; |
8a88b2a2 SW |
171 | pc->chip.of_xlate = of_pwm_xlate_with_flags; |
172 | pc->chip.of_pwm_n_cells = 3; | |
e5a06dc5 BT |
173 | |
174 | platform_set_drvdata(pdev, pc); | |
175 | ||
176 | ret = pwmchip_add(&pc->chip); | |
177 | if (ret < 0) | |
178 | goto add_fail; | |
179 | ||
180 | return 0; | |
181 | ||
182 | add_fail: | |
183 | clk_disable_unprepare(pc->clk); | |
184 | return ret; | |
185 | } | |
186 | ||
187 | static int bcm2835_pwm_remove(struct platform_device *pdev) | |
188 | { | |
189 | struct bcm2835_pwm *pc = platform_get_drvdata(pdev); | |
190 | ||
191 | clk_disable_unprepare(pc->clk); | |
192 | ||
193 | return pwmchip_remove(&pc->chip); | |
194 | } | |
195 | ||
196 | static const struct of_device_id bcm2835_pwm_of_match[] = { | |
197 | { .compatible = "brcm,bcm2835-pwm", }, | |
198 | { /* sentinel */ } | |
199 | }; | |
200 | MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match); | |
201 | ||
202 | static struct platform_driver bcm2835_pwm_driver = { | |
203 | .driver = { | |
204 | .name = "bcm2835-pwm", | |
205 | .of_match_table = bcm2835_pwm_of_match, | |
206 | }, | |
207 | .probe = bcm2835_pwm_probe, | |
208 | .remove = bcm2835_pwm_remove, | |
209 | }; | |
210 | module_platform_driver(bcm2835_pwm_driver); | |
211 | ||
6ef7d1c4 | 212 | MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>"); |
e5a06dc5 BT |
213 | MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver"); |
214 | MODULE_LICENSE("GPL v2"); |