[linux-2.6-block.git] / drivers / pwm / pwm-bcm2835.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>

#define PWM_CONTROL		0x000
#define PWM_CONTROL_SHIFT(x)	((x) * 8)
#define PWM_CONTROL_MASK	0xff
#define PWM_MODE		0x80		/* set timer in PWM mode */
#define PWM_ENABLE		(1 << 0)
#define PWM_POLARITY		(1 << 4)

#define PERIOD(x)		(((x) * 0x10) + 0x10)
#define DUTY(x)			(((x) * 0x10) + 0x14)

#define PERIOD_MIN		0x2

struct bcm2835_pwm {
	struct pwm_chip chip;
	struct device *dev;
	void __iomem *base;
	struct clk *clk;
};

static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct bcm2835_pwm, chip);
}

static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	u32 value;

	value = readl(pc->base + PWM_CONTROL);
	value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
	value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
	writel(value, pc->base + PWM_CONTROL);

	return 0;
}

static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	u32 value;

	value = readl(pc->base + PWM_CONTROL);
	value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
	writel(value, pc->base + PWM_CONTROL);
}

static int bcm2835_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			     const struct pwm_state *state)
{

	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	unsigned long rate = clk_get_rate(pc->clk);
	unsigned long long period;
	unsigned long scaler;
	u32 val;

	if (!rate) {
		dev_err(pc->dev, "failed to get clock rate\n");
		return -EINVAL;
	}

	scaler = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate);
	/* set period */
	period = DIV_ROUND_CLOSEST_ULL(state->period, scaler);

	/* dont accept a period that is too small or has been truncated */
	if ((period < PERIOD_MIN) || (period > U32_MAX))
		return -EINVAL;

	writel(period, pc->base + PERIOD(pwm->hwpwm));

	/* set duty cycle */
	val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, scaler);
	writel(val, pc->base + DUTY(pwm->hwpwm));

	/* set polarity */
	val = readl(pc->base + PWM_CONTROL);

	if (state->polarity == PWM_POLARITY_NORMAL)
		val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
	else
		val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);

	/* enable/disable */
	if (state->enabled)
		val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
	else
		val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));

	writel(val, pc->base + PWM_CONTROL);

	return 0;
}

static const struct pwm_ops bcm2835_pwm_ops = {
	.request = bcm2835_pwm_request,
	.free = bcm2835_pwm_free,
	.apply = bcm2835_pwm_apply,
	.owner = THIS_MODULE,
};

static int bcm2835_pwm_probe(struct platform_device *pdev)
{
	struct bcm2835_pwm *pc;
	int ret;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	pc->dev = &pdev->dev;

	pc->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->base))
		return PTR_ERR(pc->base);

	pc->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pc->clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
				     "clock not found\n");

	ret = clk_prepare_enable(pc->clk);
	if (ret)
		return ret;

	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &bcm2835_pwm_ops;
	pc->chip.base = -1;
	pc->chip.npwm = 2;
	pc->chip.of_xlate = of_pwm_xlate_with_flags;
	pc->chip.of_pwm_n_cells = 3;

	platform_set_drvdata(pdev, pc);

	ret = pwmchip_add(&pc->chip);
	if (ret < 0)
		goto add_fail;

	return 0;

add_fail:
	clk_disable_unprepare(pc->clk);
	return ret;
}

static int bcm2835_pwm_remove(struct platform_device *pdev)
{
	struct bcm2835_pwm *pc = platform_get_drvdata(pdev);

	clk_disable_unprepare(pc->clk);

	return pwmchip_remove(&pc->chip);
}

static const struct of_device_id bcm2835_pwm_of_match[] = {
	{ .compatible = "brcm,bcm2835-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);

static struct platform_driver bcm2835_pwm_driver = {
	.driver = {
		.name = "bcm2835-pwm",
		.of_match_table = bcm2835_pwm_of_match,
	},
	.probe = bcm2835_pwm_probe,
	.remove = bcm2835_pwm_remove,
};
module_platform_driver(bcm2835_pwm_driver);

MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
e747cbe2	1	// SPDX-License-Identifier: GPL-2.0
e5a06dc5 BT	2	/*
e5a06dc5 BT	3	* Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
e5a06dc5 BT	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/err.h>
	8	#include <linux/io.h>
	9	#include <linux/module.h>
	10	#include <linux/of.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/pwm.h>
	13
	14	#define PWM_CONTROL 0x000
	15	#define PWM_CONTROL_SHIFT(x) ((x) * 8)
	16	#define PWM_CONTROL_MASK 0xff
	17	#define PWM_MODE 0x80 /* set timer in PWM mode */
	18	#define PWM_ENABLE (1 << 0)
	19	#define PWM_POLARITY (1 << 4)
	20
	21	#define PERIOD(x) (((x) * 0x10) + 0x10)
	22	#define DUTY(x) (((x) * 0x10) + 0x14)
	23
7e9713af	24	#define PERIOD_MIN 0x2
e5a06dc5 BT	25
	26	struct bcm2835_pwm {
	27	struct pwm_chip chip;
	28	struct device *dev;
e5a06dc5 BT	29	void __iomem *base;
	30	struct clk *clk;
	31	};
	32
	33	static inline struct bcm2835_pwm to_bcm2835_pwm(struct pwm_chip chip)
	34	{
	35	return container_of(chip, struct bcm2835_pwm, chip);
	36	}
	37
	38	static int bcm2835_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	39	{
	40	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	41	u32 value;
	42
	43	value = readl(pc->base + PWM_CONTROL);
	44	value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
	45	value \|= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
	46	writel(value, pc->base + PWM_CONTROL);
	47
	48	return 0;
	49	}
	50
	51	static void bcm2835_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	52	{
	53	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
	54	u32 value;
	55
	56	value = readl(pc->base + PWM_CONTROL);
	57	value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
	58	writel(value, pc->base + PWM_CONTROL);
	59	}
	60
2f81b51d LS	61	static int bcm2835_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
2f81b51d LS	62	const struct pwm_state *state)
e5a06dc5	63	{
2f81b51d	64
e5a06dc5	65	struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
fd13c144	66	unsigned long rate = clk_get_rate(pc->clk);
2f81b51d	67	unsigned long long period;
fd13c144	68	unsigned long scaler;
2f81b51d	69	u32 val;
fd13c144 SW	70
	71	if (!rate) {
	72	dev_err(pc->dev, "failed to get clock rate\n");
	73	return -EINVAL;
	74	}
	75
11fc4edc	76	scaler = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate);
2f81b51d LS	77	/* set period */
2f81b51d LS	78	period = DIV_ROUND_CLOSEST_ULL(state->period, scaler);
e5a06dc5	79
2f81b51d LS	80	/* dont accept a period that is too small or has been truncated */
2f81b51d LS	81	if ((period < PERIOD_MIN) \|\| (period > U32_MAX))
e5a06dc5	82	return -EINVAL;
e5a06dc5	83
7e9713af	84	writel(period, pc->base + PERIOD(pwm->hwpwm));
e5a06dc5	85
2f81b51d LS	86	/* set duty cycle */
	87	val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, scaler);
	88	writel(val, pc->base + DUTY(pwm->hwpwm));
e5a06dc5	89
2f81b51d LS	90	/* set polarity */
2f81b51d LS	91	val = readl(pc->base + PWM_CONTROL);
e5a06dc5	92
2f81b51d LS	93	if (state->polarity == PWM_POLARITY_NORMAL)
	94	val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
	95	else
	96	val \|= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
e5a06dc5	97
2f81b51d LS	98	/* enable/disable */
	99	if (state->enabled)
	100	val \|= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
e5a06dc5	101	else
2f81b51d	102	val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
e5a06dc5	103
2f81b51d	104	writel(val, pc->base + PWM_CONTROL);
e5a06dc5 BT	105
	106	return 0;
	107	}
	108
	109	static const struct pwm_ops bcm2835_pwm_ops = {
	110	.request = bcm2835_pwm_request,
	111	.free = bcm2835_pwm_free,
2f81b51d	112	.apply = bcm2835_pwm_apply,
e5a06dc5 BT	113	.owner = THIS_MODULE,
	114	};
	115
	116	static int bcm2835_pwm_probe(struct platform_device *pdev)
	117	{
	118	struct bcm2835_pwm *pc;
e5a06dc5 BT	119	int ret;
	120
	121	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	122	if (!pc)
	123	return -ENOMEM;
	124
	125	pc->dev = &pdev->dev;
	126
f57e7d25	127	pc->base = devm_platform_ioremap_resource(pdev, 0);
e5a06dc5 BT	128	if (IS_ERR(pc->base))
	129	return PTR_ERR(pc->base);
	130
	131	pc->clk = devm_clk_get(&pdev->dev, NULL);
85a5745f KK	132	if (IS_ERR(pc->clk))
	133	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
	134	"clock not found\n");
e5a06dc5 BT	135
	136	ret = clk_prepare_enable(pc->clk);
	137	if (ret)
	138	return ret;
	139
e5a06dc5 BT	140	pc->chip.dev = &pdev->dev;
e5a06dc5 BT	141	pc->chip.ops = &bcm2835_pwm_ops;
2c25b07e	142	pc->chip.base = -1;
e5a06dc5	143	pc->chip.npwm = 2;
8a88b2a2 SW	144	pc->chip.of_xlate = of_pwm_xlate_with_flags;
8a88b2a2 SW	145	pc->chip.of_pwm_n_cells = 3;
e5a06dc5 BT	146
	147	platform_set_drvdata(pdev, pc);
	148
	149	ret = pwmchip_add(&pc->chip);
	150	if (ret < 0)
	151	goto add_fail;
	152
	153	return 0;
	154
	155	add_fail:
	156	clk_disable_unprepare(pc->clk);
	157	return ret;
	158	}
	159
	160	static int bcm2835_pwm_remove(struct platform_device *pdev)
	161	{
	162	struct bcm2835_pwm *pc = platform_get_drvdata(pdev);
	163
	164	clk_disable_unprepare(pc->clk);
	165
	166	return pwmchip_remove(&pc->chip);
	167	}
	168
	169	static const struct of_device_id bcm2835_pwm_of_match[] = {
	170	{ .compatible = "brcm,bcm2835-pwm", },
	171	{ /* sentinel */ }
	172	};
	173	MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
	174
	175	static struct platform_driver bcm2835_pwm_driver = {
	176	.driver = {
	177	.name = "bcm2835-pwm",
	178	.of_match_table = bcm2835_pwm_of_match,
	179	},
	180	.probe = bcm2835_pwm_probe,
	181	.remove = bcm2835_pwm_remove,
	182	};
	183	module_platform_driver(bcm2835_pwm_driver);
	184
6ef7d1c4	185	MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
e5a06dc5 BT	186	MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
e5a06dc5 BT	187	MODULE_LICENSE("GPL v2");