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e747cbe2 | 1 | // SPDX-License-Identifier: GPL-2.0 |
e5a06dc5 BT |
2 | /* |
3 | * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be> | |
e5a06dc5 BT |
4 | */ |
5 | ||
6 | #include <linux/clk.h> | |
7 | #include <linux/err.h> | |
8 | #include <linux/io.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/of.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/pwm.h> | |
13 | ||
14 | #define PWM_CONTROL 0x000 | |
15 | #define PWM_CONTROL_SHIFT(x) ((x) * 8) | |
16 | #define PWM_CONTROL_MASK 0xff | |
17 | #define PWM_MODE 0x80 /* set timer in PWM mode */ | |
18 | #define PWM_ENABLE (1 << 0) | |
19 | #define PWM_POLARITY (1 << 4) | |
20 | ||
21 | #define PERIOD(x) (((x) * 0x10) + 0x10) | |
22 | #define DUTY(x) (((x) * 0x10) + 0x14) | |
23 | ||
24 | #define MIN_PERIOD 108 /* 9.2 MHz max. PWM clock */ | |
25 | ||
26 | struct bcm2835_pwm { | |
27 | struct pwm_chip chip; | |
28 | struct device *dev; | |
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29 | void __iomem *base; |
30 | struct clk *clk; | |
31 | }; | |
32 | ||
33 | static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip) | |
34 | { | |
35 | return container_of(chip, struct bcm2835_pwm, chip); | |
36 | } | |
37 | ||
38 | static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) | |
39 | { | |
40 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
41 | u32 value; | |
42 | ||
43 | value = readl(pc->base + PWM_CONTROL); | |
44 | value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
45 | value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
46 | writel(value, pc->base + PWM_CONTROL); | |
47 | ||
48 | return 0; | |
49 | } | |
50 | ||
51 | static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
52 | { | |
53 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
54 | u32 value; | |
55 | ||
56 | value = readl(pc->base + PWM_CONTROL); | |
57 | value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
58 | writel(value, pc->base + PWM_CONTROL); | |
59 | } | |
60 | ||
61 | static int bcm2835_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
62 | int duty_ns, int period_ns) | |
63 | { | |
64 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
fd13c144 SW |
65 | unsigned long rate = clk_get_rate(pc->clk); |
66 | unsigned long scaler; | |
67 | ||
68 | if (!rate) { | |
69 | dev_err(pc->dev, "failed to get clock rate\n"); | |
70 | return -EINVAL; | |
71 | } | |
72 | ||
11fc4edc | 73 | scaler = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate); |
e5a06dc5 | 74 | |
4537e52a | 75 | if (period_ns <= MIN_PERIOD) |
e5a06dc5 | 76 | return -EINVAL; |
e5a06dc5 | 77 | |
11fc4edc SY |
78 | writel(DIV_ROUND_CLOSEST(duty_ns, scaler), |
79 | pc->base + DUTY(pwm->hwpwm)); | |
80 | writel(DIV_ROUND_CLOSEST(period_ns, scaler), | |
81 | pc->base + PERIOD(pwm->hwpwm)); | |
e5a06dc5 BT |
82 | |
83 | return 0; | |
84 | } | |
85 | ||
86 | static int bcm2835_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
87 | { | |
88 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
89 | u32 value; | |
90 | ||
91 | value = readl(pc->base + PWM_CONTROL); | |
92 | value |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm); | |
93 | writel(value, pc->base + PWM_CONTROL); | |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
98 | static void bcm2835_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
99 | { | |
100 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
101 | u32 value; | |
102 | ||
103 | value = readl(pc->base + PWM_CONTROL); | |
104 | value &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
105 | writel(value, pc->base + PWM_CONTROL); | |
106 | } | |
107 | ||
108 | static int bcm2835_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, | |
109 | enum pwm_polarity polarity) | |
110 | { | |
111 | struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); | |
112 | u32 value; | |
113 | ||
114 | value = readl(pc->base + PWM_CONTROL); | |
115 | ||
116 | if (polarity == PWM_POLARITY_NORMAL) | |
117 | value &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm)); | |
118 | else | |
119 | value |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm); | |
120 | ||
121 | writel(value, pc->base + PWM_CONTROL); | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | static const struct pwm_ops bcm2835_pwm_ops = { | |
127 | .request = bcm2835_pwm_request, | |
128 | .free = bcm2835_pwm_free, | |
129 | .config = bcm2835_pwm_config, | |
130 | .enable = bcm2835_pwm_enable, | |
131 | .disable = bcm2835_pwm_disable, | |
132 | .set_polarity = bcm2835_set_polarity, | |
133 | .owner = THIS_MODULE, | |
134 | }; | |
135 | ||
136 | static int bcm2835_pwm_probe(struct platform_device *pdev) | |
137 | { | |
138 | struct bcm2835_pwm *pc; | |
139 | struct resource *res; | |
140 | int ret; | |
141 | ||
142 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); | |
143 | if (!pc) | |
144 | return -ENOMEM; | |
145 | ||
146 | pc->dev = &pdev->dev; | |
147 | ||
148 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
149 | pc->base = devm_ioremap_resource(&pdev->dev, res); | |
150 | if (IS_ERR(pc->base)) | |
151 | return PTR_ERR(pc->base); | |
152 | ||
153 | pc->clk = devm_clk_get(&pdev->dev, NULL); | |
154 | if (IS_ERR(pc->clk)) { | |
155 | dev_err(&pdev->dev, "clock not found: %ld\n", PTR_ERR(pc->clk)); | |
156 | return PTR_ERR(pc->clk); | |
157 | } | |
158 | ||
159 | ret = clk_prepare_enable(pc->clk); | |
160 | if (ret) | |
161 | return ret; | |
162 | ||
e5a06dc5 BT |
163 | pc->chip.dev = &pdev->dev; |
164 | pc->chip.ops = &bcm2835_pwm_ops; | |
165 | pc->chip.npwm = 2; | |
8a88b2a2 SW |
166 | pc->chip.of_xlate = of_pwm_xlate_with_flags; |
167 | pc->chip.of_pwm_n_cells = 3; | |
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168 | |
169 | platform_set_drvdata(pdev, pc); | |
170 | ||
171 | ret = pwmchip_add(&pc->chip); | |
172 | if (ret < 0) | |
173 | goto add_fail; | |
174 | ||
175 | return 0; | |
176 | ||
177 | add_fail: | |
178 | clk_disable_unprepare(pc->clk); | |
179 | return ret; | |
180 | } | |
181 | ||
182 | static int bcm2835_pwm_remove(struct platform_device *pdev) | |
183 | { | |
184 | struct bcm2835_pwm *pc = platform_get_drvdata(pdev); | |
185 | ||
186 | clk_disable_unprepare(pc->clk); | |
187 | ||
188 | return pwmchip_remove(&pc->chip); | |
189 | } | |
190 | ||
191 | static const struct of_device_id bcm2835_pwm_of_match[] = { | |
192 | { .compatible = "brcm,bcm2835-pwm", }, | |
193 | { /* sentinel */ } | |
194 | }; | |
195 | MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match); | |
196 | ||
197 | static struct platform_driver bcm2835_pwm_driver = { | |
198 | .driver = { | |
199 | .name = "bcm2835-pwm", | |
200 | .of_match_table = bcm2835_pwm_of_match, | |
201 | }, | |
202 | .probe = bcm2835_pwm_probe, | |
203 | .remove = bcm2835_pwm_remove, | |
204 | }; | |
205 | module_platform_driver(bcm2835_pwm_driver); | |
206 | ||
6ef7d1c4 | 207 | MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>"); |
e5a06dc5 BT |
208 | MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver"); |
209 | MODULE_LICENSE("GPL v2"); |