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2aec85b2 TG |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // Copyright (C) 2016 Broadcom | |
daa5abc4 YRDR |
3 | |
4 | #include <linux/clk.h> | |
5 | #include <linux/delay.h> | |
6 | #include <linux/err.h> | |
7 | #include <linux/io.h> | |
8 | #include <linux/math64.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/of.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/pwm.h> | |
13 | ||
14 | #define IPROC_PWM_CTRL_OFFSET 0x00 | |
15 | #define IPROC_PWM_CTRL_TYPE_SHIFT(ch) (15 + (ch)) | |
16 | #define IPROC_PWM_CTRL_POLARITY_SHIFT(ch) (8 + (ch)) | |
17 | #define IPROC_PWM_CTRL_EN_SHIFT(ch) (ch) | |
18 | ||
19 | #define IPROC_PWM_PERIOD_OFFSET(ch) (0x04 + ((ch) << 3)) | |
20 | #define IPROC_PWM_PERIOD_MIN 0x02 | |
21 | #define IPROC_PWM_PERIOD_MAX 0xffff | |
22 | ||
23 | #define IPROC_PWM_DUTY_CYCLE_OFFSET(ch) (0x08 + ((ch) << 3)) | |
24 | #define IPROC_PWM_DUTY_CYCLE_MIN 0x00 | |
25 | #define IPROC_PWM_DUTY_CYCLE_MAX 0xffff | |
26 | ||
27 | #define IPROC_PWM_PRESCALE_OFFSET 0x24 | |
28 | #define IPROC_PWM_PRESCALE_BITS 0x06 | |
29 | #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \ | |
30 | IPROC_PWM_PRESCALE_BITS) | |
31 | #define IPROC_PWM_PRESCALE_MASK(ch) (IPROC_PWM_PRESCALE_MAX << \ | |
32 | IPROC_PWM_PRESCALE_SHIFT(ch)) | |
33 | #define IPROC_PWM_PRESCALE_MIN 0x00 | |
34 | #define IPROC_PWM_PRESCALE_MAX 0x3f | |
35 | ||
36 | struct iproc_pwmc { | |
37 | struct pwm_chip chip; | |
38 | void __iomem *base; | |
39 | struct clk *clk; | |
40 | }; | |
41 | ||
42 | static inline struct iproc_pwmc *to_iproc_pwmc(struct pwm_chip *chip) | |
43 | { | |
44 | return container_of(chip, struct iproc_pwmc, chip); | |
45 | } | |
46 | ||
47 | static void iproc_pwmc_enable(struct iproc_pwmc *ip, unsigned int channel) | |
48 | { | |
49 | u32 value; | |
50 | ||
51 | value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); | |
52 | value |= 1 << IPROC_PWM_CTRL_EN_SHIFT(channel); | |
53 | writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); | |
54 | ||
55 | /* must be a 400 ns delay between clearing and setting enable bit */ | |
56 | ndelay(400); | |
57 | } | |
58 | ||
59 | static void iproc_pwmc_disable(struct iproc_pwmc *ip, unsigned int channel) | |
60 | { | |
61 | u32 value; | |
62 | ||
63 | value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); | |
64 | value &= ~(1 << IPROC_PWM_CTRL_EN_SHIFT(channel)); | |
65 | writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); | |
66 | ||
67 | /* must be a 400 ns delay between clearing and setting enable bit */ | |
68 | ndelay(400); | |
69 | } | |
70 | ||
6c452cff UKK |
71 | static int iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm, |
72 | struct pwm_state *state) | |
daa5abc4 YRDR |
73 | { |
74 | struct iproc_pwmc *ip = to_iproc_pwmc(chip); | |
75 | u64 tmp, multi, rate; | |
76 | u32 value, prescale; | |
77 | ||
daa5abc4 YRDR |
78 | value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); |
79 | ||
80 | if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) | |
81 | state->enabled = true; | |
82 | else | |
83 | state->enabled = false; | |
84 | ||
85 | if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) | |
86 | state->polarity = PWM_POLARITY_NORMAL; | |
87 | else | |
88 | state->polarity = PWM_POLARITY_INVERSED; | |
89 | ||
6ced5ff0 RK |
90 | rate = clk_get_rate(ip->clk); |
91 | if (rate == 0) { | |
92 | state->period = 0; | |
93 | state->duty_cycle = 0; | |
6c452cff | 94 | return 0; |
6ced5ff0 RK |
95 | } |
96 | ||
daa5abc4 YRDR |
97 | value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); |
98 | prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); | |
99 | prescale &= IPROC_PWM_PRESCALE_MAX; | |
100 | ||
101 | multi = NSEC_PER_SEC * (prescale + 1); | |
102 | ||
103 | value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); | |
104 | tmp = (value & IPROC_PWM_PERIOD_MAX) * multi; | |
105 | state->period = div64_u64(tmp, rate); | |
106 | ||
107 | value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); | |
108 | tmp = (value & IPROC_PWM_PERIOD_MAX) * multi; | |
109 | state->duty_cycle = div64_u64(tmp, rate); | |
6c452cff UKK |
110 | |
111 | return 0; | |
daa5abc4 YRDR |
112 | } |
113 | ||
114 | static int iproc_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm, | |
71523d18 | 115 | const struct pwm_state *state) |
daa5abc4 YRDR |
116 | { |
117 | unsigned long prescale = IPROC_PWM_PRESCALE_MIN; | |
118 | struct iproc_pwmc *ip = to_iproc_pwmc(chip); | |
119 | u32 value, period, duty; | |
120 | u64 rate; | |
121 | ||
122 | rate = clk_get_rate(ip->clk); | |
123 | ||
124 | /* | |
125 | * Find period count, duty count and prescale to suit duty_cycle and | |
126 | * period. This is done according to formulas described below: | |
127 | * | |
128 | * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE | |
129 | * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE | |
130 | * | |
131 | * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1)) | |
132 | * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1)) | |
133 | */ | |
134 | while (1) { | |
135 | u64 value, div; | |
136 | ||
137 | div = NSEC_PER_SEC * (prescale + 1); | |
138 | value = rate * state->period; | |
139 | period = div64_u64(value, div); | |
140 | value = rate * state->duty_cycle; | |
141 | duty = div64_u64(value, div); | |
142 | ||
9443f2c8 | 143 | if (period < IPROC_PWM_PERIOD_MIN) |
daa5abc4 YRDR |
144 | return -EINVAL; |
145 | ||
146 | if (period <= IPROC_PWM_PERIOD_MAX && | |
147 | duty <= IPROC_PWM_DUTY_CYCLE_MAX) | |
148 | break; | |
149 | ||
150 | /* Otherwise, increase prescale and recalculate counts */ | |
151 | if (++prescale > IPROC_PWM_PRESCALE_MAX) | |
152 | return -EINVAL; | |
153 | } | |
154 | ||
155 | iproc_pwmc_disable(ip, pwm->hwpwm); | |
156 | ||
157 | /* Set prescale */ | |
158 | value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); | |
159 | value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm); | |
160 | value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); | |
161 | writel(value, ip->base + IPROC_PWM_PRESCALE_OFFSET); | |
162 | ||
163 | /* set period and duty cycle */ | |
164 | writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); | |
165 | writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); | |
166 | ||
167 | /* set polarity */ | |
168 | value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); | |
169 | ||
170 | if (state->polarity == PWM_POLARITY_NORMAL) | |
171 | value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm); | |
172 | else | |
173 | value &= ~(1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm)); | |
174 | ||
175 | writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); | |
176 | ||
177 | if (state->enabled) | |
178 | iproc_pwmc_enable(ip, pwm->hwpwm); | |
179 | ||
180 | return 0; | |
181 | } | |
182 | ||
183 | static const struct pwm_ops iproc_pwm_ops = { | |
184 | .apply = iproc_pwmc_apply, | |
185 | .get_state = iproc_pwmc_get_state, | |
24906a41 | 186 | .owner = THIS_MODULE, |
daa5abc4 YRDR |
187 | }; |
188 | ||
189 | static int iproc_pwmc_probe(struct platform_device *pdev) | |
190 | { | |
191 | struct iproc_pwmc *ip; | |
daa5abc4 YRDR |
192 | unsigned int i; |
193 | u32 value; | |
194 | int ret; | |
195 | ||
196 | ip = devm_kzalloc(&pdev->dev, sizeof(*ip), GFP_KERNEL); | |
197 | if (!ip) | |
198 | return -ENOMEM; | |
199 | ||
200 | platform_set_drvdata(pdev, ip); | |
201 | ||
202 | ip->chip.dev = &pdev->dev; | |
203 | ip->chip.ops = &iproc_pwm_ops; | |
daa5abc4 | 204 | ip->chip.npwm = 4; |
daa5abc4 | 205 | |
ed98401f | 206 | ip->base = devm_platform_ioremap_resource(pdev, 0); |
daa5abc4 YRDR |
207 | if (IS_ERR(ip->base)) |
208 | return PTR_ERR(ip->base); | |
209 | ||
210 | ip->clk = devm_clk_get(&pdev->dev, NULL); | |
211 | if (IS_ERR(ip->clk)) { | |
212 | dev_err(&pdev->dev, "failed to get clock: %ld\n", | |
213 | PTR_ERR(ip->clk)); | |
214 | return PTR_ERR(ip->clk); | |
215 | } | |
216 | ||
217 | ret = clk_prepare_enable(ip->clk); | |
218 | if (ret < 0) { | |
219 | dev_err(&pdev->dev, "failed to enable clock: %d\n", ret); | |
220 | return ret; | |
221 | } | |
222 | ||
223 | /* Set full drive and normal polarity for all channels */ | |
224 | value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); | |
225 | ||
226 | for (i = 0; i < ip->chip.npwm; i++) { | |
227 | value &= ~(1 << IPROC_PWM_CTRL_TYPE_SHIFT(i)); | |
228 | value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(i); | |
229 | } | |
230 | ||
231 | writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); | |
232 | ||
233 | ret = pwmchip_add(&ip->chip); | |
234 | if (ret < 0) { | |
235 | dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); | |
236 | clk_disable_unprepare(ip->clk); | |
237 | } | |
238 | ||
239 | return ret; | |
240 | } | |
241 | ||
242 | static int iproc_pwmc_remove(struct platform_device *pdev) | |
243 | { | |
244 | struct iproc_pwmc *ip = platform_get_drvdata(pdev); | |
245 | ||
d4ac3917 UKK |
246 | pwmchip_remove(&ip->chip); |
247 | ||
daa5abc4 YRDR |
248 | clk_disable_unprepare(ip->clk); |
249 | ||
d4ac3917 | 250 | return 0; |
daa5abc4 YRDR |
251 | } |
252 | ||
253 | static const struct of_device_id bcm_iproc_pwmc_dt[] = { | |
254 | { .compatible = "brcm,iproc-pwm" }, | |
255 | { }, | |
256 | }; | |
257 | MODULE_DEVICE_TABLE(of, bcm_iproc_pwmc_dt); | |
258 | ||
259 | static struct platform_driver iproc_pwmc_driver = { | |
260 | .driver = { | |
261 | .name = "bcm-iproc-pwm", | |
262 | .of_match_table = bcm_iproc_pwmc_dt, | |
263 | }, | |
264 | .probe = iproc_pwmc_probe, | |
265 | .remove = iproc_pwmc_remove, | |
266 | }; | |
267 | module_platform_driver(iproc_pwmc_driver); | |
268 | ||
269 | MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>"); | |
270 | MODULE_DESCRIPTION("Broadcom iProc PWM driver"); | |
271 | MODULE_LICENSE("GPL v2"); |