[linux-2.6-block.git] / drivers / pwm / pwm-atmel.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Atmel Pulse Width Modulation Controller
 *
 * Copyright (C) 2013 Atmel Corporation
 *		 Bo Shen <voice.shen@atmel.com>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

/* The following is global registers for PWM controller */
#define PWM_ENA			0x04
#define PWM_DIS			0x08
#define PWM_SR			0x0C
#define PWM_ISR			0x1C
/* Bit field in SR */
#define PWM_SR_ALL_CH_ON	0x0F

/* The following register is PWM channel related registers */
#define PWM_CH_REG_OFFSET	0x200
#define PWM_CH_REG_SIZE		0x20

#define PWM_CMR			0x0
/* Bit field in CMR */
#define PWM_CMR_CPOL		(1 << 9)
#define PWM_CMR_UPD_CDTY	(1 << 10)
#define PWM_CMR_CPRE_MSK	0xF

/* The following registers for PWM v1 */
#define PWMV1_CDTY		0x04
#define PWMV1_CPRD		0x08
#define PWMV1_CUPD		0x10

/* The following registers for PWM v2 */
#define PWMV2_CDTY		0x04
#define PWMV2_CDTYUPD		0x08
#define PWMV2_CPRD		0x0C
#define PWMV2_CPRDUPD		0x10

struct atmel_pwm_registers {
	u8 period;
	u8 period_upd;
	u8 duty;
	u8 duty_upd;
};

struct atmel_pwm_config {
	u32 max_period;
	u32 max_pres;
};

struct atmel_pwm_data {
	struct atmel_pwm_registers regs;
	struct atmel_pwm_config cfg;
};

struct atmel_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
	const struct atmel_pwm_data *data;

	unsigned int updated_pwms;
	/* ISR is cleared when read, ensure only one thread does that */
	struct mutex isr_lock;
};

static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct atmel_pwm_chip, chip);
}

static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
				  unsigned long offset)
{
	return readl_relaxed(chip->base + offset);
}

static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
				    unsigned long offset, unsigned long val)
{
	writel_relaxed(val, chip->base + offset);
}

static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
				     unsigned int ch, unsigned long offset)
{
	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;

	return readl_relaxed(chip->base + base + offset);
}

static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
				       unsigned int ch, unsigned long offset,
				       unsigned long val)
{
	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;

	writel_relaxed(val, chip->base + base + offset);
}

static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
					     const struct pwm_state *state,
					     unsigned long *cprd, u32 *pres)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	unsigned long long cycles = state->period;

	/* Calculate the period cycles and prescale value */
	cycles *= clk_get_rate(atmel_pwm->clk);
	do_div(cycles, NSEC_PER_SEC);

	for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1)
		(*pres)++;

	if (*pres > atmel_pwm->data->cfg.max_pres) {
		dev_err(chip->dev, "pres exceeds the maximum value\n");
		return -EINVAL;
	}

	*cprd = cycles;

	return 0;
}

static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
				     unsigned long cprd, unsigned long *cdty)
{
	unsigned long long cycles = state->duty_cycle;

	cycles *= cprd;
	do_div(cycles, state->period);
	*cdty = cprd - cycles;
}

static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
				  unsigned long cdty)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	u32 val;

	if (atmel_pwm->data->regs.duty_upd ==
	    atmel_pwm->data->regs.period_upd) {
		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
		val &= ~PWM_CMR_UPD_CDTY;
		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
	}

	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
			    atmel_pwm->data->regs.duty_upd, cdty);
}

static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
				    struct pwm_device *pwm,
				    unsigned long cprd, unsigned long cdty)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);

	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
			    atmel_pwm->data->regs.duty, cdty);
	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
			    atmel_pwm->data->regs.period, cprd);
}

static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
			      bool disable_clk)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	unsigned long timeout = jiffies + 2 * HZ;

	/*
	 * Wait for at least a complete period to have passed before disabling a
	 * channel to be sure that CDTY has been updated
	 */
	mutex_lock(&atmel_pwm->isr_lock);
	atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);

	while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
	       time_before(jiffies, timeout)) {
		usleep_range(10, 100);
		atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
	}

	mutex_unlock(&atmel_pwm->isr_lock);
	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);

	/*
	 * Wait for the PWM channel disable operation to be effective before
	 * stopping the clock.
	 */
	timeout = jiffies + 2 * HZ;

	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
	       time_before(jiffies, timeout))
		usleep_range(10, 100);

	if (disable_clk)
		clk_disable(atmel_pwm->clk);
}

static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   struct pwm_state *state)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	struct pwm_state cstate;
	unsigned long cprd, cdty;
	u32 pres, val;
	int ret;

	pwm_get_state(pwm, &cstate);

	if (state->enabled) {
		if (cstate.enabled &&
		    cstate.polarity == state->polarity &&
		    cstate.period == state->period) {
			cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
						  atmel_pwm->data->regs.period);
			atmel_pwm_calculate_cdty(state, cprd, &cdty);
			atmel_pwm_update_cdty(chip, pwm, cdty);
			return 0;
		}

		ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
							&pres);
		if (ret) {
			dev_err(chip->dev,
				"failed to calculate cprd and prescaler\n");
			return ret;
		}

		atmel_pwm_calculate_cdty(state, cprd, &cdty);

		if (cstate.enabled) {
			atmel_pwm_disable(chip, pwm, false);
		} else {
			ret = clk_enable(atmel_pwm->clk);
			if (ret) {
				dev_err(chip->dev, "failed to enable clock\n");
				return ret;
			}
		}

		/* It is necessary to preserve CPOL, inside CMR */
		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
		val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
		if (state->polarity == PWM_POLARITY_NORMAL)
			val &= ~PWM_CMR_CPOL;
		else
			val |= PWM_CMR_CPOL;
		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
		atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
		mutex_lock(&atmel_pwm->isr_lock);
		atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
		atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
		mutex_unlock(&atmel_pwm->isr_lock);
		atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
	} else if (cstate.enabled) {
		atmel_pwm_disable(chip, pwm, true);
	}

	return 0;
}

static const struct pwm_ops atmel_pwm_ops = {
	.apply = atmel_pwm_apply,
	.owner = THIS_MODULE,
};

static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
	.regs = {
		.period		= PWMV1_CPRD,
		.period_upd	= PWMV1_CUPD,
		.duty		= PWMV1_CDTY,
		.duty_upd	= PWMV1_CUPD,
	},
	.cfg = {
		/* 16 bits to keep period and duty. */
		.max_period	= 0xffff,
		.max_pres	= 10,
	},
};

static const struct atmel_pwm_data atmel_sama5_pwm_data = {
	.regs = {
		.period		= PWMV2_CPRD,
		.period_upd	= PWMV2_CPRDUPD,
		.duty		= PWMV2_CDTY,
		.duty_upd	= PWMV2_CDTYUPD,
	},
	.cfg = {
		/* 16 bits to keep period and duty. */
		.max_period	= 0xffff,
		.max_pres	= 10,
	},
};

static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
	.regs = {
		.period		= PWMV1_CPRD,
		.period_upd	= PWMV1_CUPD,
		.duty		= PWMV1_CDTY,
		.duty_upd	= PWMV1_CUPD,
	},
	.cfg = {
		/* 32 bits to keep period and duty. */
		.max_period	= 0xffffffff,
		.max_pres	= 10,
	},
};

static const struct platform_device_id atmel_pwm_devtypes[] = {
	{
		.name = "at91sam9rl-pwm",
		.driver_data = (kernel_ulong_t)&atmel_sam9rl_pwm_data,
	}, {
		.name = "sama5d3-pwm",
		.driver_data = (kernel_ulong_t)&atmel_sama5_pwm_data,
	}, {
		/* sentinel */
	},
};
MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);

static const struct of_device_id atmel_pwm_dt_ids[] = {
	{
		.compatible = "atmel,at91sam9rl-pwm",
		.data = &atmel_sam9rl_pwm_data,
	}, {
		.compatible = "atmel,sama5d3-pwm",
		.data = &atmel_sama5_pwm_data,
	}, {
		.compatible = "atmel,sama5d2-pwm",
		.data = &atmel_sama5_pwm_data,
	}, {
		.compatible = "microchip,sam9x60-pwm",
		.data = &mchp_sam9x60_pwm_data,
	}, {
		/* sentinel */
	},
};
MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);

static inline const struct atmel_pwm_data *
atmel_pwm_get_driver_data(struct platform_device *pdev)
{
	const struct platform_device_id *id;

	if (pdev->dev.of_node)
		return of_device_get_match_data(&pdev->dev);

	id = platform_get_device_id(pdev);

	return (struct atmel_pwm_data *)id->driver_data;
}

static int atmel_pwm_probe(struct platform_device *pdev)
{
	const struct atmel_pwm_data *data;
	struct atmel_pwm_chip *atmel_pwm;
	struct resource *res;
	int ret;

	data = atmel_pwm_get_driver_data(pdev);
	if (!data)
		return -ENODEV;

	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
	if (!atmel_pwm)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(atmel_pwm->base))
		return PTR_ERR(atmel_pwm->base);

	atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(atmel_pwm->clk))
		return PTR_ERR(atmel_pwm->clk);

	ret = clk_prepare(atmel_pwm->clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to prepare PWM clock\n");
		return ret;
	}

	atmel_pwm->chip.dev = &pdev->dev;
	atmel_pwm->chip.ops = &atmel_pwm_ops;

	if (pdev->dev.of_node) {
		atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
		atmel_pwm->chip.of_pwm_n_cells = 3;
	}

	atmel_pwm->chip.base = -1;
	atmel_pwm->chip.npwm = 4;
	atmel_pwm->data = data;
	atmel_pwm->updated_pwms = 0;
	mutex_init(&atmel_pwm->isr_lock);

	ret = pwmchip_add(&atmel_pwm->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
		goto unprepare_clk;
	}

	platform_set_drvdata(pdev, atmel_pwm);

	return ret;

unprepare_clk:
	clk_unprepare(atmel_pwm->clk);
	return ret;
}

static int atmel_pwm_remove(struct platform_device *pdev)
{
	struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);

	clk_unprepare(atmel_pwm->clk);
	mutex_destroy(&atmel_pwm->isr_lock);

	return pwmchip_remove(&atmel_pwm->chip);
}

static struct platform_driver atmel_pwm_driver = {
	.driver = {
		.name = "atmel-pwm",
		.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
	},
	.id_table = atmel_pwm_devtypes,
	.probe = atmel_pwm_probe,
	.remove = atmel_pwm_remove,
};
module_platform_driver(atmel_pwm_driver);

MODULE_ALIAS("platform:atmel-pwm");
MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
MODULE_DESCRIPTION("Atmel PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f50a7f3d	1	// SPDX-License-Identifier: GPL-2.0-only
32b16d46 BS	2	/*
	3	* Driver for Atmel Pulse Width Modulation Controller
	4	*
	5	* Copyright (C) 2013 Atmel Corporation
	6	* Bo Shen <voice.shen@atmel.com>
32b16d46 BS	7	*/
	8
	9	#include <linux/clk.h>
472ac3dc	10	#include <linux/delay.h>
32b16d46 BS	11	#include <linux/err.h>
	12	#include <linux/io.h>
	13	#include <linux/module.h>
472ac3dc	14	#include <linux/mutex.h>
32b16d46 BS	15	#include <linux/of.h>
	16	#include <linux/of_device.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pwm.h>
	19	#include <linux/slab.h>
	20
	21	/* The following is global registers for PWM controller */
	22	#define PWM_ENA 0x04
	23	#define PWM_DIS 0x08
	24	#define PWM_SR 0x0C
472ac3dc	25	#define PWM_ISR 0x1C
32b16d46 BS	26	/* Bit field in SR */
	27	#define PWM_SR_ALL_CH_ON 0x0F
	28
	29	/* The following register is PWM channel related registers */
	30	#define PWM_CH_REG_OFFSET 0x200
	31	#define PWM_CH_REG_SIZE 0x20
	32
	33	#define PWM_CMR 0x0
	34	/* Bit field in CMR */
	35	#define PWM_CMR_CPOL (1 << 9)
	36	#define PWM_CMR_UPD_CDTY (1 << 10)
8db9e29f	37	#define PWM_CMR_CPRE_MSK 0xF
32b16d46 BS	38
	39	/* The following registers for PWM v1 */
	40	#define PWMV1_CDTY 0x04
	41	#define PWMV1_CPRD 0x08
	42	#define PWMV1_CUPD 0x10
	43
	44	/* The following registers for PWM v2 */
	45	#define PWMV2_CDTY 0x04
	46	#define PWMV2_CDTYUPD 0x08
	47	#define PWMV2_CPRD 0x0C
	48	#define PWMV2_CPRDUPD 0x10
	49
1a722aad CB	50	struct atmel_pwm_registers {
	51	u8 period;
	52	u8 period_upd;
	53	u8 duty;
	54	u8 duty_upd;
	55	};
	56
0285827d CB	57	struct atmel_pwm_config {
	58	u32 max_period;
	59	u32 max_pres;
	60	};
	61
53784159 CB	62	struct atmel_pwm_data {
53784159 CB	63	struct atmel_pwm_registers regs;
0285827d	64	struct atmel_pwm_config cfg;
53784159 CB	65	};
53784159 CB	66
32b16d46 BS	67	struct atmel_pwm_chip {
	68	struct pwm_chip chip;
	69	struct clk *clk;
	70	void __iomem *base;
53784159	71	const struct atmel_pwm_data *data;
32b16d46	72
472ac3dc	73	unsigned int updated_pwms;
313b78ef TR	74	/* ISR is cleared when read, ensure only one thread does that */
313b78ef TR	75	struct mutex isr_lock;
32b16d46 BS	76	};
	77
	78	static inline struct atmel_pwm_chip to_atmel_pwm_chip(struct pwm_chip chip)
	79	{
	80	return container_of(chip, struct atmel_pwm_chip, chip);
	81	}
	82
	83	static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
	84	unsigned long offset)
	85	{
	86	return readl_relaxed(chip->base + offset);
	87	}
	88
	89	static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
	90	unsigned long offset, unsigned long val)
	91	{
	92	writel_relaxed(val, chip->base + offset);
	93	}
	94
	95	static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
	96	unsigned int ch, unsigned long offset)
	97	{
	98	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
	99
	100	return readl_relaxed(chip->base + base + offset);
	101	}
	102
	103	static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
	104	unsigned int ch, unsigned long offset,
	105	unsigned long val)
	106	{
	107	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
	108
	109	writel_relaxed(val, chip->base + base + offset);
	110	}
	111
1a722aad CB	112	static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
	113	const struct pwm_state *state,
	114	unsigned long cprd, u32 pres)
32b16d46 BS	115	{
32b16d46 BS	116	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
1a722aad	117	unsigned long long cycles = state->period;
32b16d46	118
e2e08970	119	/* Calculate the period cycles and prescale value */
1a722aad CB	120	cycles *= clk_get_rate(atmel_pwm->clk);
1a722aad CB	121	do_div(cycles, NSEC_PER_SEC);
32b16d46	122
0285827d	123	for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1)
1a722aad	124	(*pres)++;
e2e08970	125
0285827d	126	if (*pres > atmel_pwm->data->cfg.max_pres) {
e2e08970 NV	127	dev_err(chip->dev, "pres exceeds the maximum value\n");
e2e08970 NV	128	return -EINVAL;
32b16d46 BS	129	}
32b16d46 BS	130
1a722aad	131	*cprd = cycles;
32b16d46	132
1a722aad	133	return 0;
32b16d46 BS	134	}
32b16d46 BS	135
1a722aad CB	136	static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
1a722aad CB	137	unsigned long cprd, unsigned long *cdty)
32b16d46	138	{
1a722aad	139	unsigned long long cycles = state->duty_cycle;
32b16d46	140
1a722aad CB	141	cycles *= cprd;
	142	do_div(cycles, state->period);
	143	*cdty = cprd - cycles;
32b16d46 BS	144	}
32b16d46 BS	145
1a722aad CB	146	static void atmel_pwm_update_cdty(struct pwm_chip chip, struct pwm_device pwm,
1a722aad CB	147	unsigned long cdty)
32b16d46 BS	148	{
	149	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	150	u32 val;
32b16d46	151
53784159 CB	152	if (atmel_pwm->data->regs.duty_upd ==
53784159 CB	153	atmel_pwm->data->regs.period_upd) {
1a722aad CB	154	val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
	155	val &= ~PWM_CMR_UPD_CDTY;
	156	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
32b16d46 BS	157	}
32b16d46 BS	158
1a722aad	159	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
53784159	160	atmel_pwm->data->regs.duty_upd, cdty);
32b16d46 BS	161	}
32b16d46 BS	162
1a722aad CB	163	static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
	164	struct pwm_device *pwm,
	165	unsigned long cprd, unsigned long cdty)
32b16d46 BS	166	{
32b16d46 BS	167	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
32b16d46	168
1a722aad	169	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
53784159	170	atmel_pwm->data->regs.duty, cdty);
1a722aad	171	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
53784159	172	atmel_pwm->data->regs.period, cprd);
32b16d46 BS	173	}
32b16d46 BS	174
1a722aad CB	175	static void atmel_pwm_disable(struct pwm_chip chip, struct pwm_device pwm,
1a722aad CB	176	bool disable_clk)
32b16d46 BS	177	{
32b16d46 BS	178	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
472ac3dc AB	179	unsigned long timeout = jiffies + 2 * HZ;
	180
	181	/*
	182	* Wait for at least a complete period to have passed before disabling a
	183	* channel to be sure that CDTY has been updated
	184	*/
	185	mutex_lock(&atmel_pwm->isr_lock);
	186	atmel_pwm->updated_pwms \|= atmel_pwm_readl(atmel_pwm, PWM_ISR);
	187
	188	while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
	189	time_before(jiffies, timeout)) {
	190	usleep_range(10, 100);
	191	atmel_pwm->updated_pwms \|= atmel_pwm_readl(atmel_pwm, PWM_ISR);
	192	}
32b16d46	193
472ac3dc	194	mutex_unlock(&atmel_pwm->isr_lock);
32b16d46 BS	195	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
32b16d46 BS	196
f718c54c GR	197	/*
	198	* Wait for the PWM channel disable operation to be effective before
	199	* stopping the clock.
	200	*/
	201	timeout = jiffies + 2 * HZ;
	202
	203	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
	204	time_before(jiffies, timeout))
	205	usleep_range(10, 100);
	206
1a722aad CB	207	if (disable_clk)
	208	clk_disable(atmel_pwm->clk);
	209	}
	210
	211	static int atmel_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	212	struct pwm_state *state)
	213	{
	214	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	215	struct pwm_state cstate;
	216	unsigned long cprd, cdty;
	217	u32 pres, val;
	218	int ret;
	219
	220	pwm_get_state(pwm, &cstate);
	221
	222	if (state->enabled) {
	223	if (cstate.enabled &&
	224	cstate.polarity == state->polarity &&
	225	cstate.period == state->period) {
	226	cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
53784159	227	atmel_pwm->data->regs.period);
1a722aad CB	228	atmel_pwm_calculate_cdty(state, cprd, &cdty);
	229	atmel_pwm_update_cdty(chip, pwm, cdty);
	230	return 0;
	231	}
	232
	233	ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
	234	&pres);
	235	if (ret) {
	236	dev_err(chip->dev,
	237	"failed to calculate cprd and prescaler\n");
	238	return ret;
	239	}
	240
	241	atmel_pwm_calculate_cdty(state, cprd, &cdty);
	242
	243	if (cstate.enabled) {
	244	atmel_pwm_disable(chip, pwm, false);
	245	} else {
	246	ret = clk_enable(atmel_pwm->clk);
	247	if (ret) {
	248	dev_err(chip->dev, "failed to enable clock\n");
	249	return ret;
	250	}
	251	}
	252
	253	/* It is necessary to preserve CPOL, inside CMR */
	254	val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
	255	val = (val & ~PWM_CMR_CPRE_MSK) \| (pres & PWM_CMR_CPRE_MSK);
	256	if (state->polarity == PWM_POLARITY_NORMAL)
	257	val &= ~PWM_CMR_CPOL;
	258	else
	259	val \|= PWM_CMR_CPOL;
	260	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
	261	atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
	262	mutex_lock(&atmel_pwm->isr_lock);
	263	atmel_pwm->updated_pwms \|= atmel_pwm_readl(atmel_pwm, PWM_ISR);
	264	atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
	265	mutex_unlock(&atmel_pwm->isr_lock);
	266	atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
	267	} else if (cstate.enabled) {
	268	atmel_pwm_disable(chip, pwm, true);
	269	}
	270
	271	return 0;
32b16d46 BS	272	}
	273
	274	static const struct pwm_ops atmel_pwm_ops = {
1a722aad	275	.apply = atmel_pwm_apply,
32b16d46 BS	276	.owner = THIS_MODULE,
	277	};
	278
abcbe373	279	static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
53784159 CB	280	.regs = {
	281	.period = PWMV1_CPRD,
	282	.period_upd = PWMV1_CUPD,
	283	.duty = PWMV1_CDTY,
	284	.duty_upd = PWMV1_CUPD,
	285	},
0285827d CB	286	.cfg = {
0285827d CB	287	/* 16 bits to keep period and duty. */
d7d96312 TR	288	.max_period = 0xffff,
d7d96312 TR	289	.max_pres = 10,
0285827d	290	},
32b16d46 BS	291	};
32b16d46 BS	292
abcbe373	293	static const struct atmel_pwm_data atmel_sama5_pwm_data = {
53784159 CB	294	.regs = {
	295	.period = PWMV2_CPRD,
	296	.period_upd = PWMV2_CPRDUPD,
	297	.duty = PWMV2_CDTY,
	298	.duty_upd = PWMV2_CDTYUPD,
	299	},
0285827d CB	300	.cfg = {
0285827d CB	301	/* 16 bits to keep period and duty. */
d7d96312 TR	302	.max_period = 0xffff,
d7d96312 TR	303	.max_pres = 10,
0285827d	304	},
32b16d46 BS	305	};
32b16d46 BS	306
74d0c3b2 CB	307	static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
	308	.regs = {
	309	.period = PWMV1_CPRD,
	310	.period_upd = PWMV1_CUPD,
	311	.duty = PWMV1_CDTY,
	312	.duty_upd = PWMV1_CUPD,
	313	},
	314	.cfg = {
	315	/* 32 bits to keep period and duty. */
d7d96312 TR	316	.max_period = 0xffffffff,
d7d96312 TR	317	.max_pres = 10,
74d0c3b2 CB	318	},
	319	};
	320
32b16d46 BS	321	static const struct platform_device_id atmel_pwm_devtypes[] = {
	322	{
	323	.name = "at91sam9rl-pwm",
abcbe373	324	.driver_data = (kernel_ulong_t)&atmel_sam9rl_pwm_data,
32b16d46 BS	325	}, {
32b16d46 BS	326	.name = "sama5d3-pwm",
abcbe373	327	.driver_data = (kernel_ulong_t)&atmel_sama5_pwm_data,
32b16d46 BS	328	}, {
	329	/* sentinel */
	330	},
	331	};
	332	MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
	333
	334	static const struct of_device_id atmel_pwm_dt_ids[] = {
	335	{
	336	.compatible = "atmel,at91sam9rl-pwm",
abcbe373	337	.data = &atmel_sam9rl_pwm_data,
32b16d46 BS	338	}, {
32b16d46 BS	339	.compatible = "atmel,sama5d3-pwm",
abcbe373	340	.data = &atmel_sama5_pwm_data,
44521afa CB	341	}, {
44521afa CB	342	.compatible = "atmel,sama5d2-pwm",
abcbe373	343	.data = &atmel_sama5_pwm_data,
74d0c3b2 CB	344	}, {
	345	.compatible = "microchip,sam9x60-pwm",
	346	.data = &mchp_sam9x60_pwm_data,
32b16d46 BS	347	}, {
	348	/* sentinel */
	349	},
	350	};
	351	MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
	352
53784159	353	static inline const struct atmel_pwm_data *
32b16d46 BS	354	atmel_pwm_get_driver_data(struct platform_device *pdev)
32b16d46 BS	355	{
313b78ef TR	356	const struct platform_device_id *id;
313b78ef TR	357
017bb04e TR	358	if (pdev->dev.of_node)
017bb04e TR	359	return of_device_get_match_data(&pdev->dev);
32b16d46	360
313b78ef	361	id = platform_get_device_id(pdev);
32b16d46	362
53784159	363	return (struct atmel_pwm_data *)id->driver_data;
32b16d46 BS	364	}
	365
	366	static int atmel_pwm_probe(struct platform_device *pdev)
	367	{
53784159	368	const struct atmel_pwm_data *data;
32b16d46 BS	369	struct atmel_pwm_chip *atmel_pwm;
	370	struct resource *res;
	371	int ret;
	372
53784159 CB	373	data = atmel_pwm_get_driver_data(pdev);
53784159 CB	374	if (!data)
32b16d46 BS	375	return -ENODEV;
	376
	377	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
	378	if (!atmel_pwm)
	379	return -ENOMEM;
	380
	381	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	382	atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
	383	if (IS_ERR(atmel_pwm->base))
	384	return PTR_ERR(atmel_pwm->base);
	385
	386	atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
	387	if (IS_ERR(atmel_pwm->clk))
	388	return PTR_ERR(atmel_pwm->clk);
	389
	390	ret = clk_prepare(atmel_pwm->clk);
	391	if (ret) {
	392	dev_err(&pdev->dev, "failed to prepare PWM clock\n");
	393	return ret;
	394	}
	395
	396	atmel_pwm->chip.dev = &pdev->dev;
	397	atmel_pwm->chip.ops = &atmel_pwm_ops;
	398
	399	if (pdev->dev.of_node) {
	400	atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
	401	atmel_pwm->chip.of_pwm_n_cells = 3;
	402	}
	403
	404	atmel_pwm->chip.base = -1;
	405	atmel_pwm->chip.npwm = 4;
53784159	406	atmel_pwm->data = data;
472ac3dc AB	407	atmel_pwm->updated_pwms = 0;
472ac3dc AB	408	mutex_init(&atmel_pwm->isr_lock);
32b16d46 BS	409
	410	ret = pwmchip_add(&atmel_pwm->chip);
	411	if (ret < 0) {
	412	dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
	413	goto unprepare_clk;
	414	}
	415
	416	platform_set_drvdata(pdev, atmel_pwm);
	417
6a683356 BS	418	return ret;
6a683356 BS	419
32b16d46 BS	420	unprepare_clk:
	421	clk_unprepare(atmel_pwm->clk);
	422	return ret;
	423	}
	424
	425	static int atmel_pwm_remove(struct platform_device *pdev)
	426	{
	427	struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
	428
	429	clk_unprepare(atmel_pwm->clk);
472ac3dc	430	mutex_destroy(&atmel_pwm->isr_lock);
32b16d46 BS	431
	432	return pwmchip_remove(&atmel_pwm->chip);
	433	}
	434
	435	static struct platform_driver atmel_pwm_driver = {
	436	.driver = {
	437	.name = "atmel-pwm",
	438	.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
	439	},
	440	.id_table = atmel_pwm_devtypes,
	441	.probe = atmel_pwm_probe,
	442	.remove = atmel_pwm_remove,
	443	};
	444	module_platform_driver(atmel_pwm_driver);
	445
	446	MODULE_ALIAS("platform:atmel-pwm");
	447	MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
	448	MODULE_DESCRIPTION("Atmel PWM driver");
	449	MODULE_LICENSE("GPL v2");