[linux-2.6-block.git] / drivers / pwm / pwm-atmel.c

/*
 * Driver for Atmel Pulse Width Modulation Controller
 *
 * Copyright (C) 2013 Atmel Corporation
 *		 Bo Shen <voice.shen@atmel.com>
 *
 * Licensed under GPLv2.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

/* The following is global registers for PWM controller */
#define PWM_ENA			0x04
#define PWM_DIS			0x08
#define PWM_SR			0x0C
#define PWM_ISR			0x1C
/* Bit field in SR */
#define PWM_SR_ALL_CH_ON	0x0F

/* The following register is PWM channel related registers */
#define PWM_CH_REG_OFFSET	0x200
#define PWM_CH_REG_SIZE		0x20

#define PWM_CMR			0x0
/* Bit field in CMR */
#define PWM_CMR_CPOL		(1 << 9)
#define PWM_CMR_UPD_CDTY	(1 << 10)
#define PWM_CMR_CPRE_MSK	0xF

/* The following registers for PWM v1 */
#define PWMV1_CDTY		0x04
#define PWMV1_CPRD		0x08
#define PWMV1_CUPD		0x10

/* The following registers for PWM v2 */
#define PWMV2_CDTY		0x04
#define PWMV2_CDTYUPD		0x08
#define PWMV2_CPRD		0x0C
#define PWMV2_CPRDUPD		0x10

struct atmel_pwm_registers {
	u8 period;
	u8 period_upd;
	u8 duty;
	u8 duty_upd;
};

struct atmel_pwm_config {
	u32 max_period;
	u32 max_pres;
};

struct atmel_pwm_data {
	struct atmel_pwm_registers regs;
	struct atmel_pwm_config cfg;
};

struct atmel_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
	const struct atmel_pwm_data *data;

	unsigned int updated_pwms;
	/* ISR is cleared when read, ensure only one thread does that */
	struct mutex isr_lock;
};

static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct atmel_pwm_chip, chip);
}

static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
				  unsigned long offset)
{
	return readl_relaxed(chip->base + offset);
}

static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
				    unsigned long offset, unsigned long val)
{
	writel_relaxed(val, chip->base + offset);
}

static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
				     unsigned int ch, unsigned long offset)
{
	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;

	return readl_relaxed(chip->base + base + offset);
}

static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
				       unsigned int ch, unsigned long offset,
				       unsigned long val)
{
	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;

	writel_relaxed(val, chip->base + base + offset);
}

static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
					     const struct pwm_state *state,
					     unsigned long *cprd, u32 *pres)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	unsigned long long cycles = state->period;

	/* Calculate the period cycles and prescale value */
	cycles *= clk_get_rate(atmel_pwm->clk);
	do_div(cycles, NSEC_PER_SEC);

	for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1)
		(*pres)++;

	if (*pres > atmel_pwm->data->cfg.max_pres) {
		dev_err(chip->dev, "pres exceeds the maximum value\n");
		return -EINVAL;
	}

	*cprd = cycles;

	return 0;
}

static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
				     unsigned long cprd, unsigned long *cdty)
{
	unsigned long long cycles = state->duty_cycle;

	cycles *= cprd;
	do_div(cycles, state->period);
	*cdty = cprd - cycles;
}

static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
				  unsigned long cdty)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	u32 val;

	if (atmel_pwm->data->regs.duty_upd ==
	    atmel_pwm->data->regs.period_upd) {
		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
		val &= ~PWM_CMR_UPD_CDTY;
		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
	}

	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
			    atmel_pwm->data->regs.duty_upd, cdty);
}

static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
				    struct pwm_device *pwm,
				    unsigned long cprd, unsigned long cdty)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);

	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
			    atmel_pwm->data->regs.duty, cdty);
	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
			    atmel_pwm->data->regs.period, cprd);
}

static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
			      bool disable_clk)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	unsigned long timeout = jiffies + 2 * HZ;

	/*
	 * Wait for at least a complete period to have passed before disabling a
	 * channel to be sure that CDTY has been updated
	 */
	mutex_lock(&atmel_pwm->isr_lock);
	atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);

	while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
	       time_before(jiffies, timeout)) {
		usleep_range(10, 100);
		atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
	}

	mutex_unlock(&atmel_pwm->isr_lock);
	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);

	/*
	 * Wait for the PWM channel disable operation to be effective before
	 * stopping the clock.
	 */
	timeout = jiffies + 2 * HZ;

	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
	       time_before(jiffies, timeout))
		usleep_range(10, 100);

	if (disable_clk)
		clk_disable(atmel_pwm->clk);
}

static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   struct pwm_state *state)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	struct pwm_state cstate;
	unsigned long cprd, cdty;
	u32 pres, val;
	int ret;

	pwm_get_state(pwm, &cstate);

	if (state->enabled) {
		if (cstate.enabled &&
		    cstate.polarity == state->polarity &&
		    cstate.period == state->period) {
			cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
						  atmel_pwm->data->regs.period);
			atmel_pwm_calculate_cdty(state, cprd, &cdty);
			atmel_pwm_update_cdty(chip, pwm, cdty);
			return 0;
		}

		ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
							&pres);
		if (ret) {
			dev_err(chip->dev,
				"failed to calculate cprd and prescaler\n");
			return ret;
		}

		atmel_pwm_calculate_cdty(state, cprd, &cdty);

		if (cstate.enabled) {
			atmel_pwm_disable(chip, pwm, false);
		} else {
			ret = clk_enable(atmel_pwm->clk);
			if (ret) {
				dev_err(chip->dev, "failed to enable clock\n");
				return ret;
			}
		}

		/* It is necessary to preserve CPOL, inside CMR */
		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
		val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
		if (state->polarity == PWM_POLARITY_NORMAL)
			val &= ~PWM_CMR_CPOL;
		else
			val |= PWM_CMR_CPOL;
		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
		atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
		mutex_lock(&atmel_pwm->isr_lock);
		atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
		atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
		mutex_unlock(&atmel_pwm->isr_lock);
		atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
	} else if (cstate.enabled) {
		atmel_pwm_disable(chip, pwm, true);
	}

	return 0;
}

static const struct pwm_ops atmel_pwm_ops = {
	.apply = atmel_pwm_apply,
	.owner = THIS_MODULE,
};

static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
	.regs = {
		.period		= PWMV1_CPRD,
		.period_upd	= PWMV1_CUPD,
		.duty		= PWMV1_CDTY,
		.duty_upd	= PWMV1_CUPD,
	},
	.cfg = {
		/* 16 bits to keep period and duty. */
		.max_period	= 0xffff,
		.max_pres	= 10,
	},
};

static const struct atmel_pwm_data atmel_sama5_pwm_data = {
	.regs = {
		.period		= PWMV2_CPRD,
		.period_upd	= PWMV2_CPRDUPD,
		.duty		= PWMV2_CDTY,
		.duty_upd	= PWMV2_CDTYUPD,
	},
	.cfg = {
		/* 16 bits to keep period and duty. */
		.max_period	= 0xffff,
		.max_pres	= 10,
	},
};

static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
	.regs = {
		.period		= PWMV1_CPRD,
		.period_upd	= PWMV1_CUPD,
		.duty		= PWMV1_CDTY,
		.duty_upd	= PWMV1_CUPD,
	},
	.cfg = {
		/* 32 bits to keep period and duty. */
		.max_period	= 0xffffffff,
		.max_pres	= 10,
	},
};

static const struct platform_device_id atmel_pwm_devtypes[] = {
	{
		.name = "at91sam9rl-pwm",
		.driver_data = (kernel_ulong_t)&atmel_sam9rl_pwm_data,
	}, {
		.name = "sama5d3-pwm",
		.driver_data = (kernel_ulong_t)&atmel_sama5_pwm_data,
	}, {
		/* sentinel */
	},
};
MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);

static const struct of_device_id atmel_pwm_dt_ids[] = {
	{
		.compatible = "atmel,at91sam9rl-pwm",
		.data = &atmel_sam9rl_pwm_data,
	}, {
		.compatible = "atmel,sama5d3-pwm",
		.data = &atmel_sama5_pwm_data,
	}, {
		.compatible = "atmel,sama5d2-pwm",
		.data = &atmel_sama5_pwm_data,
	}, {
		.compatible = "microchip,sam9x60-pwm",
		.data = &mchp_sam9x60_pwm_data,
	}, {
		/* sentinel */
	},
};
MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);

static inline const struct atmel_pwm_data *
atmel_pwm_get_driver_data(struct platform_device *pdev)
{
	const struct platform_device_id *id;

	if (pdev->dev.of_node)
		return of_device_get_match_data(&pdev->dev);

	id = platform_get_device_id(pdev);

	return (struct atmel_pwm_data *)id->driver_data;
}

static int atmel_pwm_probe(struct platform_device *pdev)
{
	const struct atmel_pwm_data *data;
	struct atmel_pwm_chip *atmel_pwm;
	struct resource *res;
	int ret;

	data = atmel_pwm_get_driver_data(pdev);
	if (!data)
		return -ENODEV;

	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
	if (!atmel_pwm)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(atmel_pwm->base))
		return PTR_ERR(atmel_pwm->base);

	atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(atmel_pwm->clk))
		return PTR_ERR(atmel_pwm->clk);

	ret = clk_prepare(atmel_pwm->clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to prepare PWM clock\n");
		return ret;
	}

	atmel_pwm->chip.dev = &pdev->dev;
	atmel_pwm->chip.ops = &atmel_pwm_ops;

	if (pdev->dev.of_node) {
		atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
		atmel_pwm->chip.of_pwm_n_cells = 3;
	}

	atmel_pwm->chip.base = -1;
	atmel_pwm->chip.npwm = 4;
	atmel_pwm->data = data;
	atmel_pwm->updated_pwms = 0;
	mutex_init(&atmel_pwm->isr_lock);

	ret = pwmchip_add(&atmel_pwm->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
		goto unprepare_clk;
	}

	platform_set_drvdata(pdev, atmel_pwm);

	return ret;

unprepare_clk:
	clk_unprepare(atmel_pwm->clk);
	return ret;
}

static int atmel_pwm_remove(struct platform_device *pdev)
{
	struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);

	clk_unprepare(atmel_pwm->clk);
	mutex_destroy(&atmel_pwm->isr_lock);

	return pwmchip_remove(&atmel_pwm->chip);
}

static struct platform_driver atmel_pwm_driver = {
	.driver = {
		.name = "atmel-pwm",
		.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
	},
	.id_table = atmel_pwm_devtypes,
	.probe = atmel_pwm_probe,
	.remove = atmel_pwm_remove,
};
module_platform_driver(atmel_pwm_driver);

MODULE_ALIAS("platform:atmel-pwm");
MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
MODULE_DESCRIPTION("Atmel PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
32b16d46 BS	1	/*
	2	* Driver for Atmel Pulse Width Modulation Controller
	3	*
	4	* Copyright (C) 2013 Atmel Corporation
	5	* Bo Shen <voice.shen@atmel.com>
	6	*
	7	* Licensed under GPLv2.
	8	*/
	9
	10	#include <linux/clk.h>
472ac3dc	11	#include <linux/delay.h>
32b16d46 BS	12	#include <linux/err.h>
	13	#include <linux/io.h>
	14	#include <linux/module.h>
472ac3dc	15	#include <linux/mutex.h>
32b16d46 BS	16	#include <linux/of.h>
	17	#include <linux/of_device.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/pwm.h>
	20	#include <linux/slab.h>
	21
	22	/* The following is global registers for PWM controller */
	23	#define PWM_ENA 0x04
	24	#define PWM_DIS 0x08
	25	#define PWM_SR 0x0C
472ac3dc	26	#define PWM_ISR 0x1C
32b16d46 BS	27	/* Bit field in SR */
	28	#define PWM_SR_ALL_CH_ON 0x0F
	29
	30	/* The following register is PWM channel related registers */
	31	#define PWM_CH_REG_OFFSET 0x200
	32	#define PWM_CH_REG_SIZE 0x20
	33
	34	#define PWM_CMR 0x0
	35	/* Bit field in CMR */
	36	#define PWM_CMR_CPOL (1 << 9)
	37	#define PWM_CMR_UPD_CDTY (1 << 10)
8db9e29f	38	#define PWM_CMR_CPRE_MSK 0xF
32b16d46 BS	39
	40	/* The following registers for PWM v1 */
	41	#define PWMV1_CDTY 0x04
	42	#define PWMV1_CPRD 0x08
	43	#define PWMV1_CUPD 0x10
	44
	45	/* The following registers for PWM v2 */
	46	#define PWMV2_CDTY 0x04
	47	#define PWMV2_CDTYUPD 0x08
	48	#define PWMV2_CPRD 0x0C
	49	#define PWMV2_CPRDUPD 0x10
	50
1a722aad CB	51	struct atmel_pwm_registers {
	52	u8 period;
	53	u8 period_upd;
	54	u8 duty;
	55	u8 duty_upd;
	56	};
	57
0285827d CB	58	struct atmel_pwm_config {
	59	u32 max_period;
	60	u32 max_pres;
	61	};
	62
53784159 CB	63	struct atmel_pwm_data {
53784159 CB	64	struct atmel_pwm_registers regs;
0285827d	65	struct atmel_pwm_config cfg;
53784159 CB	66	};
53784159 CB	67
32b16d46 BS	68	struct atmel_pwm_chip {
	69	struct pwm_chip chip;
	70	struct clk *clk;
	71	void __iomem *base;
53784159	72	const struct atmel_pwm_data *data;
32b16d46	73
472ac3dc	74	unsigned int updated_pwms;
313b78ef TR	75	/* ISR is cleared when read, ensure only one thread does that */
313b78ef TR	76	struct mutex isr_lock;
32b16d46 BS	77	};
	78
	79	static inline struct atmel_pwm_chip to_atmel_pwm_chip(struct pwm_chip chip)
	80	{
	81	return container_of(chip, struct atmel_pwm_chip, chip);
	82	}
	83
	84	static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
	85	unsigned long offset)
	86	{
	87	return readl_relaxed(chip->base + offset);
	88	}
	89
	90	static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
	91	unsigned long offset, unsigned long val)
	92	{
	93	writel_relaxed(val, chip->base + offset);
	94	}
	95
	96	static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
	97	unsigned int ch, unsigned long offset)
	98	{
	99	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
	100
	101	return readl_relaxed(chip->base + base + offset);
	102	}
	103
	104	static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
	105	unsigned int ch, unsigned long offset,
	106	unsigned long val)
	107	{
	108	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
	109
	110	writel_relaxed(val, chip->base + base + offset);
	111	}
	112
1a722aad CB	113	static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
	114	const struct pwm_state *state,
	115	unsigned long cprd, u32 pres)
32b16d46 BS	116	{
32b16d46 BS	117	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
1a722aad	118	unsigned long long cycles = state->period;
32b16d46	119
e2e08970	120	/* Calculate the period cycles and prescale value */
1a722aad CB	121	cycles *= clk_get_rate(atmel_pwm->clk);
1a722aad CB	122	do_div(cycles, NSEC_PER_SEC);
32b16d46	123
0285827d	124	for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1)
1a722aad	125	(*pres)++;
e2e08970	126
0285827d	127	if (*pres > atmel_pwm->data->cfg.max_pres) {
e2e08970 NV	128	dev_err(chip->dev, "pres exceeds the maximum value\n");
e2e08970 NV	129	return -EINVAL;
32b16d46 BS	130	}
32b16d46 BS	131
1a722aad	132	*cprd = cycles;
32b16d46	133
1a722aad	134	return 0;
32b16d46 BS	135	}
32b16d46 BS	136
1a722aad CB	137	static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
1a722aad CB	138	unsigned long cprd, unsigned long *cdty)
32b16d46	139	{
1a722aad	140	unsigned long long cycles = state->duty_cycle;
32b16d46	141
1a722aad CB	142	cycles *= cprd;
	143	do_div(cycles, state->period);
	144	*cdty = cprd - cycles;
32b16d46 BS	145	}
32b16d46 BS	146
1a722aad CB	147	static void atmel_pwm_update_cdty(struct pwm_chip chip, struct pwm_device pwm,
1a722aad CB	148	unsigned long cdty)
32b16d46 BS	149	{
	150	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	151	u32 val;
32b16d46	152
53784159 CB	153	if (atmel_pwm->data->regs.duty_upd ==
53784159 CB	154	atmel_pwm->data->regs.period_upd) {
1a722aad CB	155	val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
	156	val &= ~PWM_CMR_UPD_CDTY;
	157	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
32b16d46 BS	158	}
32b16d46 BS	159
1a722aad	160	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
53784159	161	atmel_pwm->data->regs.duty_upd, cdty);
32b16d46 BS	162	}
32b16d46 BS	163
1a722aad CB	164	static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
	165	struct pwm_device *pwm,
	166	unsigned long cprd, unsigned long cdty)
32b16d46 BS	167	{
32b16d46 BS	168	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
32b16d46	169
1a722aad	170	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
53784159	171	atmel_pwm->data->regs.duty, cdty);
1a722aad	172	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
53784159	173	atmel_pwm->data->regs.period, cprd);
32b16d46 BS	174	}
32b16d46 BS	175
1a722aad CB	176	static void atmel_pwm_disable(struct pwm_chip chip, struct pwm_device pwm,
1a722aad CB	177	bool disable_clk)
32b16d46 BS	178	{
32b16d46 BS	179	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
472ac3dc AB	180	unsigned long timeout = jiffies + 2 * HZ;
	181
	182	/*
	183	* Wait for at least a complete period to have passed before disabling a
	184	* channel to be sure that CDTY has been updated
	185	*/
	186	mutex_lock(&atmel_pwm->isr_lock);
	187	atmel_pwm->updated_pwms \|= atmel_pwm_readl(atmel_pwm, PWM_ISR);
	188
	189	while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
	190	time_before(jiffies, timeout)) {
	191	usleep_range(10, 100);
	192	atmel_pwm->updated_pwms \|= atmel_pwm_readl(atmel_pwm, PWM_ISR);
	193	}
32b16d46	194
472ac3dc	195	mutex_unlock(&atmel_pwm->isr_lock);
32b16d46 BS	196	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
32b16d46 BS	197
f718c54c GR	198	/*
	199	* Wait for the PWM channel disable operation to be effective before
	200	* stopping the clock.
	201	*/
	202	timeout = jiffies + 2 * HZ;
	203
	204	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
	205	time_before(jiffies, timeout))
	206	usleep_range(10, 100);
	207
1a722aad CB	208	if (disable_clk)
	209	clk_disable(atmel_pwm->clk);
	210	}
	211
	212	static int atmel_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	213	struct pwm_state *state)
	214	{
	215	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	216	struct pwm_state cstate;
	217	unsigned long cprd, cdty;
	218	u32 pres, val;
	219	int ret;
	220
	221	pwm_get_state(pwm, &cstate);
	222
	223	if (state->enabled) {
	224	if (cstate.enabled &&
	225	cstate.polarity == state->polarity &&
	226	cstate.period == state->period) {
	227	cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
53784159	228	atmel_pwm->data->regs.period);
1a722aad CB	229	atmel_pwm_calculate_cdty(state, cprd, &cdty);
	230	atmel_pwm_update_cdty(chip, pwm, cdty);
	231	return 0;
	232	}
	233
	234	ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
	235	&pres);
	236	if (ret) {
	237	dev_err(chip->dev,
	238	"failed to calculate cprd and prescaler\n");
	239	return ret;
	240	}
	241
	242	atmel_pwm_calculate_cdty(state, cprd, &cdty);
	243
	244	if (cstate.enabled) {
	245	atmel_pwm_disable(chip, pwm, false);
	246	} else {
	247	ret = clk_enable(atmel_pwm->clk);
	248	if (ret) {
	249	dev_err(chip->dev, "failed to enable clock\n");
	250	return ret;
	251	}
	252	}
	253
	254	/* It is necessary to preserve CPOL, inside CMR */
	255	val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
	256	val = (val & ~PWM_CMR_CPRE_MSK) \| (pres & PWM_CMR_CPRE_MSK);
	257	if (state->polarity == PWM_POLARITY_NORMAL)
	258	val &= ~PWM_CMR_CPOL;
	259	else
	260	val \|= PWM_CMR_CPOL;
	261	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
	262	atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
	263	mutex_lock(&atmel_pwm->isr_lock);
	264	atmel_pwm->updated_pwms \|= atmel_pwm_readl(atmel_pwm, PWM_ISR);
	265	atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
	266	mutex_unlock(&atmel_pwm->isr_lock);
	267	atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
	268	} else if (cstate.enabled) {
	269	atmel_pwm_disable(chip, pwm, true);
	270	}
	271
	272	return 0;
32b16d46 BS	273	}
	274
	275	static const struct pwm_ops atmel_pwm_ops = {
1a722aad	276	.apply = atmel_pwm_apply,
32b16d46 BS	277	.owner = THIS_MODULE,
	278	};
	279
abcbe373	280	static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
53784159 CB	281	.regs = {
	282	.period = PWMV1_CPRD,
	283	.period_upd = PWMV1_CUPD,
	284	.duty = PWMV1_CDTY,
	285	.duty_upd = PWMV1_CUPD,
	286	},
0285827d CB	287	.cfg = {
0285827d CB	288	/* 16 bits to keep period and duty. */
d7d96312 TR	289	.max_period = 0xffff,
d7d96312 TR	290	.max_pres = 10,
0285827d	291	},
32b16d46 BS	292	};
32b16d46 BS	293
abcbe373	294	static const struct atmel_pwm_data atmel_sama5_pwm_data = {
53784159 CB	295	.regs = {
	296	.period = PWMV2_CPRD,
	297	.period_upd = PWMV2_CPRDUPD,
	298	.duty = PWMV2_CDTY,
	299	.duty_upd = PWMV2_CDTYUPD,
	300	},
0285827d CB	301	.cfg = {
0285827d CB	302	/* 16 bits to keep period and duty. */
d7d96312 TR	303	.max_period = 0xffff,
d7d96312 TR	304	.max_pres = 10,
0285827d	305	},
32b16d46 BS	306	};
32b16d46 BS	307
74d0c3b2 CB	308	static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
	309	.regs = {
	310	.period = PWMV1_CPRD,
	311	.period_upd = PWMV1_CUPD,
	312	.duty = PWMV1_CDTY,
	313	.duty_upd = PWMV1_CUPD,
	314	},
	315	.cfg = {
	316	/* 32 bits to keep period and duty. */
d7d96312 TR	317	.max_period = 0xffffffff,
d7d96312 TR	318	.max_pres = 10,
74d0c3b2 CB	319	},
	320	};
	321
32b16d46 BS	322	static const struct platform_device_id atmel_pwm_devtypes[] = {
	323	{
	324	.name = "at91sam9rl-pwm",
abcbe373	325	.driver_data = (kernel_ulong_t)&atmel_sam9rl_pwm_data,
32b16d46 BS	326	}, {
32b16d46 BS	327	.name = "sama5d3-pwm",
abcbe373	328	.driver_data = (kernel_ulong_t)&atmel_sama5_pwm_data,
32b16d46 BS	329	}, {
	330	/* sentinel */
	331	},
	332	};
	333	MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
	334
	335	static const struct of_device_id atmel_pwm_dt_ids[] = {
	336	{
	337	.compatible = "atmel,at91sam9rl-pwm",
abcbe373	338	.data = &atmel_sam9rl_pwm_data,
32b16d46 BS	339	}, {
32b16d46 BS	340	.compatible = "atmel,sama5d3-pwm",
abcbe373	341	.data = &atmel_sama5_pwm_data,
44521afa CB	342	}, {
44521afa CB	343	.compatible = "atmel,sama5d2-pwm",
abcbe373	344	.data = &atmel_sama5_pwm_data,
74d0c3b2 CB	345	}, {
	346	.compatible = "microchip,sam9x60-pwm",
	347	.data = &mchp_sam9x60_pwm_data,
32b16d46 BS	348	}, {
	349	/* sentinel */
	350	},
	351	};
	352	MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
	353
53784159	354	static inline const struct atmel_pwm_data *
32b16d46 BS	355	atmel_pwm_get_driver_data(struct platform_device *pdev)
32b16d46 BS	356	{
313b78ef TR	357	const struct platform_device_id *id;
313b78ef TR	358
017bb04e TR	359	if (pdev->dev.of_node)
017bb04e TR	360	return of_device_get_match_data(&pdev->dev);
32b16d46	361
313b78ef	362	id = platform_get_device_id(pdev);
32b16d46	363
53784159	364	return (struct atmel_pwm_data *)id->driver_data;
32b16d46 BS	365	}
	366
	367	static int atmel_pwm_probe(struct platform_device *pdev)
	368	{
53784159	369	const struct atmel_pwm_data *data;
32b16d46 BS	370	struct atmel_pwm_chip *atmel_pwm;
	371	struct resource *res;
	372	int ret;
	373
53784159 CB	374	data = atmel_pwm_get_driver_data(pdev);
53784159 CB	375	if (!data)
32b16d46 BS	376	return -ENODEV;
	377
	378	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
	379	if (!atmel_pwm)
	380	return -ENOMEM;
	381
	382	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	383	atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
	384	if (IS_ERR(atmel_pwm->base))
	385	return PTR_ERR(atmel_pwm->base);
	386
	387	atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
	388	if (IS_ERR(atmel_pwm->clk))
	389	return PTR_ERR(atmel_pwm->clk);
	390
	391	ret = clk_prepare(atmel_pwm->clk);
	392	if (ret) {
	393	dev_err(&pdev->dev, "failed to prepare PWM clock\n");
	394	return ret;
	395	}
	396
	397	atmel_pwm->chip.dev = &pdev->dev;
	398	atmel_pwm->chip.ops = &atmel_pwm_ops;
	399
	400	if (pdev->dev.of_node) {
	401	atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
	402	atmel_pwm->chip.of_pwm_n_cells = 3;
	403	}
	404
	405	atmel_pwm->chip.base = -1;
	406	atmel_pwm->chip.npwm = 4;
53784159	407	atmel_pwm->data = data;
472ac3dc AB	408	atmel_pwm->updated_pwms = 0;
472ac3dc AB	409	mutex_init(&atmel_pwm->isr_lock);
32b16d46 BS	410
	411	ret = pwmchip_add(&atmel_pwm->chip);
	412	if (ret < 0) {
	413	dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
	414	goto unprepare_clk;
	415	}
	416
	417	platform_set_drvdata(pdev, atmel_pwm);
	418
6a683356 BS	419	return ret;
6a683356 BS	420
32b16d46 BS	421	unprepare_clk:
	422	clk_unprepare(atmel_pwm->clk);
	423	return ret;
	424	}
	425
	426	static int atmel_pwm_remove(struct platform_device *pdev)
	427	{
	428	struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
	429
	430	clk_unprepare(atmel_pwm->clk);
472ac3dc	431	mutex_destroy(&atmel_pwm->isr_lock);
32b16d46 BS	432
	433	return pwmchip_remove(&atmel_pwm->chip);
	434	}
	435
	436	static struct platform_driver atmel_pwm_driver = {
	437	.driver = {
	438	.name = "atmel-pwm",
	439	.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
	440	},
	441	.id_table = atmel_pwm_devtypes,
	442	.probe = atmel_pwm_probe,
	443	.remove = atmel_pwm_remove,
	444	};
	445	module_platform_driver(atmel_pwm_driver);
	446
	447	MODULE_ALIAS("platform:atmel-pwm");
	448	MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
	449	MODULE_DESCRIPTION("Atmel PWM driver");
	450	MODULE_LICENSE("GPL v2");