[linux-block.git] / drivers / pwm / pwm-atmel-tcb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) Overkiz SAS 2012
 *
 * Author: Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <soc/at91/atmel_tcb.h>

#define NPWM	2

#define ATMEL_TC_ACMR_MASK	(ATMEL_TC_ACPA | ATMEL_TC_ACPC |	\
				 ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)

#define ATMEL_TC_BCMR_MASK	(ATMEL_TC_BCPB | ATMEL_TC_BCPC |	\
				 ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)

struct atmel_tcb_pwm_device {
	unsigned div;			/* PWM clock divider */
	unsigned duty;			/* PWM duty expressed in clk cycles */
	unsigned period;		/* PWM period expressed in clk cycles */
};

struct atmel_tcb_channel {
	u32 enabled;
	u32 cmr;
	u32 ra;
	u32 rb;
	u32 rc;
};

struct atmel_tcb_pwm_chip {
	spinlock_t lock;
	u8 channel;
	u8 width;
	struct regmap *regmap;
	struct clk *clk;
	struct clk *gclk;
	struct clk *slow_clk;
	struct atmel_tcb_pwm_device pwms[NPWM];
	struct atmel_tcb_channel bkup;
};

static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };

static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static int atmel_tcb_pwm_request(struct pwm_chip *chip,
				 struct pwm_device *pwm)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
	unsigned cmr;
	int ret;

	ret = clk_prepare_enable(tcbpwmc->clk);
	if (ret)
		return ret;

	tcbpwm->duty = 0;
	tcbpwm->period = 0;
	tcbpwm->div = 0;

	guard(spinlock)(&tcbpwmc->lock);

	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
	/*
	 * Get init config from Timer Counter registers if
	 * Timer Counter is already configured as a PWM generator.
	 */
	if (cmr & ATMEL_TC_WAVE) {
		if (pwm->hwpwm == 0)
			regmap_read(tcbpwmc->regmap,
				    ATMEL_TC_REG(tcbpwmc->channel, RA),
				    &tcbpwm->duty);
		else
			regmap_read(tcbpwmc->regmap,
				    ATMEL_TC_REG(tcbpwmc->channel, RB),
				    &tcbpwm->duty);

		tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
		regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
			    &tcbpwm->period);
		cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
			ATMEL_TC_BCMR_MASK);
	} else
		cmr = 0;

	cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);

	return 0;
}

static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);

	clk_disable_unprepare(tcbpwmc->clk);
}

static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
				  enum pwm_polarity polarity)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
	unsigned cmr;

	/*
	 * If duty is 0 the timer will be stopped and we have to
	 * configure the output correctly on software trigger:
	 *  - set output to high if PWM_POLARITY_INVERSED
	 *  - set output to low if PWM_POLARITY_NORMAL
	 *
	 * This is why we're reverting polarity in this case.
	 */
	if (tcbpwm->duty == 0)
		polarity = !polarity;

	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);

	/* flush old setting and set the new one */
	if (pwm->hwpwm == 0) {
		cmr &= ~ATMEL_TC_ACMR_MASK;
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_ASWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_ASWTRG_SET;
	} else {
		cmr &= ~ATMEL_TC_BCMR_MASK;
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_BSWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_BSWTRG_SET;
	}

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);

	/*
	 * Use software trigger to apply the new setting.
	 * If both PWM devices in this group are disabled we stop the clock.
	 */
	if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, CCR),
			     ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
		tcbpwmc->bkup.enabled = 1;
	} else {
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, CCR),
			     ATMEL_TC_SWTRG);
		tcbpwmc->bkup.enabled = 0;
	}
}

static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
				enum pwm_polarity polarity)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
	u32 cmr;

	/*
	 * If duty is 0 the timer will be stopped and we have to
	 * configure the output correctly on software trigger:
	 *  - set output to high if PWM_POLARITY_INVERSED
	 *  - set output to low if PWM_POLARITY_NORMAL
	 *
	 * This is why we're reverting polarity in this case.
	 */
	if (tcbpwm->duty == 0)
		polarity = !polarity;

	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);

	/* flush old setting and set the new one */
	cmr &= ~ATMEL_TC_TCCLKS;

	if (pwm->hwpwm == 0) {
		cmr &= ~ATMEL_TC_ACMR_MASK;

		/* Set CMR flags according to given polarity */
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_ASWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_ASWTRG_SET;
	} else {
		cmr &= ~ATMEL_TC_BCMR_MASK;
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_BSWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_BSWTRG_SET;
	}

	/*
	 * If duty is 0 or equal to period there's no need to register
	 * a specific action on RA/RB and RC compare.
	 * The output will be configured on software trigger and keep
	 * this config till next config call.
	 */
	if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
		if (pwm->hwpwm == 0) {
			if (polarity == PWM_POLARITY_INVERSED)
				cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
			else
				cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
		} else {
			if (polarity == PWM_POLARITY_INVERSED)
				cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
			else
				cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
		}
	}

	cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);

	if (pwm->hwpwm == 0)
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, RA),
			     tcbpwm->duty);
	else
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, RB),
			     tcbpwm->duty);

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
		     tcbpwm->period);

	/* Use software trigger to apply the new setting */
	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
		     ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
	tcbpwmc->bkup.enabled = 1;
	return 0;
}

static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
				int duty_ns, int period_ns)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
	/* companion PWM sharing register values period and div */
	struct atmel_tcb_pwm_device *atcbpwm = &tcbpwmc->pwms[pwm->hwpwm ^ 1];
	int i = 0;
	int slowclk = 0;
	unsigned period;
	unsigned duty;
	unsigned rate = clk_get_rate(tcbpwmc->clk);
	unsigned long long min;
	unsigned long long max;

	/*
	 * Find best clk divisor:
	 * the smallest divisor which can fulfill the period_ns requirements.
	 * If there is a gclk, the first divisor is actually the gclk selector
	 */
	if (tcbpwmc->gclk)
		i = 1;
	for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
		if (atmel_tcb_divisors[i] == 0) {
			slowclk = i;
			continue;
		}
		min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
		max = min << tcbpwmc->width;
		if (max >= period_ns)
			break;
	}

	/*
	 * If none of the divisor are small enough to represent period_ns
	 * take slow clock (32KHz).
	 */
	if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
		i = slowclk;
		rate = clk_get_rate(tcbpwmc->slow_clk);
		min = div_u64(NSEC_PER_SEC, rate);
		max = min << tcbpwmc->width;

		/* If period is too big return ERANGE error */
		if (max < period_ns)
			return -ERANGE;
	}

	duty = div_u64(duty_ns, min);
	period = div_u64(period_ns, min);

	/*
	 * PWM devices provided by the TCB driver are grouped by 2.
	 * PWM devices in a given group must be configured with the
	 * same period_ns.
	 *
	 * We're checking the period value of the second PWM device
	 * in this group before applying the new config.
	 */
	if ((atcbpwm->duty > 0 && atcbpwm->duty != atcbpwm->period) &&
		(atcbpwm->div != i || atcbpwm->period != period)) {
		dev_err(pwmchip_parent(chip),
			"failed to configure period_ns: PWM group already configured with a different value\n");
		return -EINVAL;
	}

	tcbpwm->period = period;
	tcbpwm->div = i;
	tcbpwm->duty = duty;

	return 0;
}

static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			       const struct pwm_state *state)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	int duty_cycle, period;
	int ret;

	guard(spinlock)(&tcbpwmc->lock);

	if (!state->enabled) {
		atmel_tcb_pwm_disable(chip, pwm, state->polarity);
		return 0;
	}

	period = min(state->period, INT_MAX);
	duty_cycle = min(state->duty_cycle, INT_MAX);

	ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
	if (ret)
		return ret;

	return atmel_tcb_pwm_enable(chip, pwm, state->polarity);
}

static const struct pwm_ops atmel_tcb_pwm_ops = {
	.request = atmel_tcb_pwm_request,
	.free = atmel_tcb_pwm_free,
	.apply = atmel_tcb_pwm_apply,
};

static struct atmel_tcb_config tcb_rm9200_config = {
	.counter_width = 16,
};

static struct atmel_tcb_config tcb_sam9x5_config = {
	.counter_width = 32,
};

static struct atmel_tcb_config tcb_sama5d2_config = {
	.counter_width = 32,
	.has_gclk = 1,
};

static const struct of_device_id atmel_tcb_of_match[] = {
	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
	{ /* sentinel */ }
};

static int atmel_tcb_pwm_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	const struct of_device_id *match;
	struct atmel_tcb_pwm_chip *tcbpwmc;
	const struct atmel_tcb_config *config;
	struct device_node *np = pdev->dev.of_node;
	char clk_name[] = "t0_clk";
	int err;
	int channel;

	chip = devm_pwmchip_alloc(&pdev->dev, NPWM, sizeof(*tcbpwmc));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	tcbpwmc = to_tcb_chip(chip);

	err = of_property_read_u32(np, "reg", &channel);
	if (err < 0) {
		dev_err(&pdev->dev,
			"failed to get Timer Counter Block channel from device tree (error: %d)\n",
			err);
		return err;
	}

	tcbpwmc->regmap = syscon_node_to_regmap(np->parent);
	if (IS_ERR(tcbpwmc->regmap))
		return PTR_ERR(tcbpwmc->regmap);

	tcbpwmc->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
	if (IS_ERR(tcbpwmc->slow_clk))
		return PTR_ERR(tcbpwmc->slow_clk);

	clk_name[1] += channel;
	tcbpwmc->clk = of_clk_get_by_name(np->parent, clk_name);
	if (IS_ERR(tcbpwmc->clk))
		tcbpwmc->clk = of_clk_get_by_name(np->parent, "t0_clk");
	if (IS_ERR(tcbpwmc->clk)) {
		err = PTR_ERR(tcbpwmc->clk);
		goto err_slow_clk;
	}

	match = of_match_node(atmel_tcb_of_match, np->parent);
	config = match->data;

	if (config->has_gclk) {
		tcbpwmc->gclk = of_clk_get_by_name(np->parent, "gclk");
		if (IS_ERR(tcbpwmc->gclk)) {
			err = PTR_ERR(tcbpwmc->gclk);
			goto err_clk;
		}
	}

	chip->ops = &atmel_tcb_pwm_ops;
	tcbpwmc->channel = channel;
	tcbpwmc->width = config->counter_width;

	err = clk_prepare_enable(tcbpwmc->slow_clk);
	if (err)
		goto err_gclk;

	spin_lock_init(&tcbpwmc->lock);

	err = pwmchip_add(chip);
	if (err < 0)
		goto err_disable_clk;

	platform_set_drvdata(pdev, chip);

	return 0;

err_disable_clk:
	clk_disable_unprepare(tcbpwmc->slow_clk);

err_gclk:
	clk_put(tcbpwmc->gclk);

err_clk:
	clk_put(tcbpwmc->clk);

err_slow_clk:
	clk_put(tcbpwmc->slow_clk);

	return err;
}

static void atmel_tcb_pwm_remove(struct platform_device *pdev)
{
	struct pwm_chip *chip = platform_get_drvdata(pdev);
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);

	pwmchip_remove(chip);

	clk_disable_unprepare(tcbpwmc->slow_clk);
	clk_put(tcbpwmc->gclk);
	clk_put(tcbpwmc->clk);
	clk_put(tcbpwmc->slow_clk);
}

static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
	{ .compatible = "atmel,tcb-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);

static int atmel_tcb_pwm_suspend(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_channel *chan = &tcbpwmc->bkup;
	unsigned int channel = tcbpwmc->channel;

	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);

	return 0;
}

static int atmel_tcb_pwm_resume(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_channel *chan = &tcbpwmc->bkup;
	unsigned int channel = tcbpwmc->channel;

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RC), chan->rc);

	if (chan->enabled)
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
			     ATMEL_TC_REG(channel, CCR));

	return 0;
}

static DEFINE_SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
				atmel_tcb_pwm_resume);

static struct platform_driver atmel_tcb_pwm_driver = {
	.driver = {
		.name = "atmel-tcb-pwm",
		.of_match_table = atmel_tcb_pwm_dt_ids,
		.pm = pm_ptr(&atmel_tcb_pwm_pm_ops),
	},
	.probe = atmel_tcb_pwm_probe,
	.remove = atmel_tcb_pwm_remove,
};
module_platform_driver(atmel_tcb_pwm_driver);

MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
af873fce	1	// SPDX-License-Identifier: GPL-2.0-only
9421bade BB	2	/*
	3	* Copyright (C) Overkiz SAS 2012
	4	*
	5	* Author: Boris BREZILLON <b.brezillon@overkiz.com>
9421bade BB	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/init.h>
	10	#include <linux/clocksource.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/ioport.h>
	18	#include <linux/io.h>
061f8572	19	#include <linux/mfd/syscon.h>
9421bade	20	#include <linux/platform_device.h>
9421bade	21	#include <linux/pwm.h>
0a41b0c5	22	#include <linux/of.h>
061f8572	23	#include <linux/regmap.h>
9421bade	24	#include <linux/slab.h>
c2c9136b	25	#include <soc/at91/atmel_tcb.h>
9421bade	26
061f8572	27	#define NPWM 2
9421bade BB	28
	29	#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA \| ATMEL_TC_ACPC \| \
	30	ATMEL_TC_AEEVT \| ATMEL_TC_ASWTRG)
	31
	32	#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB \| ATMEL_TC_BCPC \| \
	33	ATMEL_TC_BEEVT \| ATMEL_TC_BSWTRG)
	34
	35	struct atmel_tcb_pwm_device {
9421bade BB	36	unsigned div; /* PWM clock divider */
	37	unsigned duty; /* PWM duty expressed in clk cycles */
	38	unsigned period; /* PWM period expressed in clk cycles */
	39	};
	40
1b3d9a93 RI	41	struct atmel_tcb_channel {
	42	u32 enabled;
	43	u32 cmr;
	44	u32 ra;
	45	u32 rb;
	46	u32 rc;
	47	};
	48
9421bade	49	struct atmel_tcb_pwm_chip {
9421bade	50	spinlock_t lock;
061f8572 AB	51	u8 channel;
	52	u8 width;
	53	struct regmap *regmap;
	54	struct clk *clk;
34cbcd72	55	struct clk *gclk;
061f8572	56	struct clk *slow_clk;
78dca23b	57	struct atmel_tcb_pwm_device pwms[NPWM];
061f8572	58	struct atmel_tcb_channel bkup;
9421bade BB	59	};
9421bade BB	60
d7b44083	61	static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
061f8572	62
9421bade BB	63	static inline struct atmel_tcb_pwm_chip to_tcb_chip(struct pwm_chip chip)
9421bade BB	64	{
af184748	65	return pwmchip_get_drvdata(chip);
9421bade BB	66	}
9421bade BB	67
9421bade BB	68	static int atmel_tcb_pwm_request(struct pwm_chip *chip,
	69	struct pwm_device *pwm)
	70	{
	71	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
78dca23b	72	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
9421bade BB	73	unsigned cmr;
	74	int ret;
	75
061f8572	76	ret = clk_prepare_enable(tcbpwmc->clk);
78dca23b	77	if (ret)
9421bade	78	return ret;
9421bade	79
9421bade BB	80	tcbpwm->duty = 0;
	81	tcbpwm->period = 0;
	82	tcbpwm->div = 0;
	83
37f77070 UKK	84	guard(spinlock)(&tcbpwmc->lock);
37f77070 UKK	85
061f8572	86	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
9421bade BB	87	/*
	88	* Get init config from Timer Counter registers if
	89	* Timer Counter is already configured as a PWM generator.
	90	*/
	91	if (cmr & ATMEL_TC_WAVE) {
061f8572 AB	92	if (pwm->hwpwm == 0)
	93	regmap_read(tcbpwmc->regmap,
	94	ATMEL_TC_REG(tcbpwmc->channel, RA),
	95	&tcbpwm->duty);
9421bade	96	else
061f8572 AB	97	regmap_read(tcbpwmc->regmap,
	98	ATMEL_TC_REG(tcbpwmc->channel, RB),
	99	&tcbpwm->duty);
9421bade BB	100
9421bade BB	101	tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
061f8572 AB	102	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
061f8572 AB	103	&tcbpwm->period);
9421bade BB	104	cmr &= (ATMEL_TC_TCCLKS \| ATMEL_TC_ACMR_MASK \|
	105	ATMEL_TC_BCMR_MASK);
	106	} else
	107	cmr = 0;
	108
	109	cmr \|= ATMEL_TC_WAVE \| ATMEL_TC_WAVESEL_UP_AUTO \| ATMEL_TC_EEVT_XC0;
061f8572	110	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
9421bade	111
9421bade BB	112	return 0;
	113	}
	114
	115	static void atmel_tcb_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	116	{
	117	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
9421bade	118
061f8572	119	clk_disable_unprepare(tcbpwmc->clk);
9421bade BB	120	}
9421bade BB	121
28a1dadc UKK	122	static void atmel_tcb_pwm_disable(struct pwm_chip chip, struct pwm_device pwm,
28a1dadc UKK	123	enum pwm_polarity polarity)
9421bade BB	124	{
9421bade BB	125	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
78dca23b	126	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
9421bade	127	unsigned cmr;
9421bade BB	128
	129	/*
	130	* If duty is 0 the timer will be stopped and we have to
	131	* configure the output correctly on software trigger:
	132	* - set output to high if PWM_POLARITY_INVERSED
	133	* - set output to low if PWM_POLARITY_NORMAL
	134	*
	135	* This is why we're reverting polarity in this case.
	136	*/
	137	if (tcbpwm->duty == 0)
	138	polarity = !polarity;
	139
061f8572	140	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
9421bade BB	141
9421bade BB	142	/* flush old setting and set the new one */
061f8572	143	if (pwm->hwpwm == 0) {
9421bade BB	144	cmr &= ~ATMEL_TC_ACMR_MASK;
	145	if (polarity == PWM_POLARITY_INVERSED)
	146	cmr \|= ATMEL_TC_ASWTRG_CLEAR;
	147	else
	148	cmr \|= ATMEL_TC_ASWTRG_SET;
	149	} else {
	150	cmr &= ~ATMEL_TC_BCMR_MASK;
	151	if (polarity == PWM_POLARITY_INVERSED)
	152	cmr \|= ATMEL_TC_BSWTRG_CLEAR;
	153	else
	154	cmr \|= ATMEL_TC_BSWTRG_SET;
	155	}
	156
061f8572	157	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
9421bade BB	158
	159	/*
	160	* Use software trigger to apply the new setting.
	161	* If both PWM devices in this group are disabled we stop the clock.
	162	*/
1b3d9a93	163	if (!(cmr & (ATMEL_TC_ACPC \| ATMEL_TC_BCPC))) {
061f8572 AB	164	regmap_write(tcbpwmc->regmap,
	165	ATMEL_TC_REG(tcbpwmc->channel, CCR),
	166	ATMEL_TC_SWTRG \| ATMEL_TC_CLKDIS);
	167	tcbpwmc->bkup.enabled = 1;
1b3d9a93	168	} else {
061f8572 AB	169	regmap_write(tcbpwmc->regmap,
	170	ATMEL_TC_REG(tcbpwmc->channel, CCR),
	171	ATMEL_TC_SWTRG);
	172	tcbpwmc->bkup.enabled = 0;
1b3d9a93	173	}
9421bade BB	174	}
9421bade BB	175
28a1dadc UKK	176	static int atmel_tcb_pwm_enable(struct pwm_chip chip, struct pwm_device pwm,
28a1dadc UKK	177	enum pwm_polarity polarity)
9421bade BB	178	{
9421bade BB	179	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
78dca23b	180	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
9421bade	181	u32 cmr;
9421bade BB	182
	183	/*
	184	* If duty is 0 the timer will be stopped and we have to
	185	* configure the output correctly on software trigger:
	186	* - set output to high if PWM_POLARITY_INVERSED
	187	* - set output to low if PWM_POLARITY_NORMAL
	188	*
	189	* This is why we're reverting polarity in this case.
	190	*/
	191	if (tcbpwm->duty == 0)
	192	polarity = !polarity;
	193
061f8572	194	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
9421bade BB	195
	196	/* flush old setting and set the new one */
	197	cmr &= ~ATMEL_TC_TCCLKS;
	198
061f8572	199	if (pwm->hwpwm == 0) {
9421bade BB	200	cmr &= ~ATMEL_TC_ACMR_MASK;
	201
	202	/* Set CMR flags according to given polarity */
	203	if (polarity == PWM_POLARITY_INVERSED)
	204	cmr \|= ATMEL_TC_ASWTRG_CLEAR;
	205	else
	206	cmr \|= ATMEL_TC_ASWTRG_SET;
	207	} else {
	208	cmr &= ~ATMEL_TC_BCMR_MASK;
	209	if (polarity == PWM_POLARITY_INVERSED)
	210	cmr \|= ATMEL_TC_BSWTRG_CLEAR;
	211	else
	212	cmr \|= ATMEL_TC_BSWTRG_SET;
	213	}
	214
	215	/*
	216	* If duty is 0 or equal to period there's no need to register
	217	* a specific action on RA/RB and RC compare.
	218	* The output will be configured on software trigger and keep
	219	* this config till next config call.
	220	*/
	221	if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
061f8572	222	if (pwm->hwpwm == 0) {
9421bade BB	223	if (polarity == PWM_POLARITY_INVERSED)
	224	cmr \|= ATMEL_TC_ACPA_SET \| ATMEL_TC_ACPC_CLEAR;
	225	else
	226	cmr \|= ATMEL_TC_ACPA_CLEAR \| ATMEL_TC_ACPC_SET;
	227	} else {
	228	if (polarity == PWM_POLARITY_INVERSED)
	229	cmr \|= ATMEL_TC_BCPB_SET \| ATMEL_TC_BCPC_CLEAR;
	230	else
	231	cmr \|= ATMEL_TC_BCPB_CLEAR \| ATMEL_TC_BCPC_SET;
	232	}
	233	}
	234
f3a82170 BB	235	cmr \|= (tcbpwm->div & ATMEL_TC_TCCLKS);
f3a82170 BB	236
061f8572	237	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
9421bade	238
061f8572 AB	239	if (pwm->hwpwm == 0)
	240	regmap_write(tcbpwmc->regmap,
	241	ATMEL_TC_REG(tcbpwmc->channel, RA),
	242	tcbpwm->duty);
9421bade	243	else
061f8572 AB	244	regmap_write(tcbpwmc->regmap,
	245	ATMEL_TC_REG(tcbpwmc->channel, RB),
	246	tcbpwm->duty);
9421bade	247
061f8572 AB	248	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
061f8572 AB	249	tcbpwm->period);
9421bade BB	250
9421bade BB	251	/* Use software trigger to apply the new setting */
061f8572 AB	252	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
	253	ATMEL_TC_SWTRG \| ATMEL_TC_CLKEN);
	254	tcbpwmc->bkup.enabled = 1;
9421bade BB	255	return 0;
	256	}
	257
	258	static int atmel_tcb_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	259	int duty_ns, int period_ns)
	260	{
	261	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
78dca23b	262	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
c1330cb9 UKK	263	/* companion PWM sharing register values period and div */
c1330cb9 UKK	264	struct atmel_tcb_pwm_device *atcbpwm = &tcbpwmc->pwms[pwm->hwpwm ^ 1];
34cbcd72	265	int i = 0;
9421bade BB	266	int slowclk = 0;
	267	unsigned period;
	268	unsigned duty;
061f8572	269	unsigned rate = clk_get_rate(tcbpwmc->clk);
9421bade BB	270	unsigned long long min;
	271	unsigned long long max;
	272
	273	/*
	274	* Find best clk divisor:
	275	* the smallest divisor which can fulfill the period_ns requirements.
f6bc65d3	276	* If there is a gclk, the first divisor is actually the gclk selector
9421bade	277	*/
34cbcd72 AB	278	if (tcbpwmc->gclk)
	279	i = 1;
	280	for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
061f8572	281	if (atmel_tcb_divisors[i] == 0) {
9421bade BB	282	slowclk = i;
	283	continue;
	284	}
061f8572 AB	285	min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
061f8572 AB	286	max = min << tcbpwmc->width;
9421bade BB	287	if (max >= period_ns)
	288	break;
	289	}
	290
	291	/*
	292	* If none of the divisor are small enough to represent period_ns
	293	* take slow clock (32KHz).
	294	*/
061f8572	295	if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
9421bade	296	i = slowclk;
061f8572	297	rate = clk_get_rate(tcbpwmc->slow_clk);
9421bade	298	min = div_u64(NSEC_PER_SEC, rate);
061f8572	299	max = min << tcbpwmc->width;
9421bade BB	300
	301	/* If period is too big return ERANGE error */
	302	if (max < period_ns)
	303	return -ERANGE;
	304	}
	305
	306	duty = div_u64(duty_ns, min);
	307	period = div_u64(period_ns, min);
	308
9421bade	309	/*
061f8572	310	* PWM devices provided by the TCB driver are grouped by 2.
9421bade BB	311	* PWM devices in a given group must be configured with the
	312	* same period_ns.
	313	*
	314	* We're checking the period value of the second PWM device
	315	* in this group before applying the new config.
	316	*/
c1330cb9	317	if ((atcbpwm->duty > 0 && atcbpwm->duty != atcbpwm->period) &&
9421bade	318	(atcbpwm->div != i \|\| atcbpwm->period != period)) {
44fe6578	319	dev_err(pwmchip_parent(chip),
9421bade BB	320	"failed to configure period_ns: PWM group already configured with a different value\n");
	321	return -EINVAL;
	322	}
	323
	324	tcbpwm->period = period;
	325	tcbpwm->div = i;
	326	tcbpwm->duty = duty;
	327
9421bade BB	328	return 0;
	329	}
	330
30882cf1 UKK	331	static int atmel_tcb_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	332	const struct pwm_state *state)
	333	{
37f77070	334	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
30882cf1 UKK	335	int duty_cycle, period;
	336	int ret;
	337
37f77070 UKK	338	guard(spinlock)(&tcbpwmc->lock);
37f77070 UKK	339
30882cf1	340	if (!state->enabled) {
28a1dadc	341	atmel_tcb_pwm_disable(chip, pwm, state->polarity);
30882cf1 UKK	342	return 0;
	343	}
	344
51f81370 SL	345	period = min(state->period, INT_MAX);
51f81370 SL	346	duty_cycle = min(state->duty_cycle, INT_MAX);
30882cf1 UKK	347
	348	ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
	349	if (ret)
	350	return ret;
	351
28a1dadc	352	return atmel_tcb_pwm_enable(chip, pwm, state->polarity);
30882cf1 UKK	353	}
30882cf1 UKK	354
9421bade BB	355	static const struct pwm_ops atmel_tcb_pwm_ops = {
	356	.request = atmel_tcb_pwm_request,
	357	.free = atmel_tcb_pwm_free,
30882cf1	358	.apply = atmel_tcb_pwm_apply,
9421bade BB	359	};
9421bade BB	360
061f8572 AB	361	static struct atmel_tcb_config tcb_rm9200_config = {
	362	.counter_width = 16,
	363	};
	364
	365	static struct atmel_tcb_config tcb_sam9x5_config = {
	366	.counter_width = 32,
	367	};
	368
34cbcd72 AB	369	static struct atmel_tcb_config tcb_sama5d2_config = {
	370	.counter_width = 32,
	371	.has_gclk = 1,
	372	};
	373
061f8572 AB	374	static const struct of_device_id atmel_tcb_of_match[] = {
	375	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
	376	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
34cbcd72	377	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
061f8572 AB	378	{ /* sentinel */ }
	379	};
	380
9421bade BB	381	static int atmel_tcb_pwm_probe(struct platform_device *pdev)
9421bade BB	382	{
dfab73eb	383	struct pwm_chip *chip;
061f8572	384	const struct of_device_id *match;
c9a787b9	385	struct atmel_tcb_pwm_chip *tcbpwmc;
061f8572	386	const struct atmel_tcb_config *config;
9421bade	387	struct device_node *np = pdev->dev.of_node;
061f8572	388	char clk_name[] = "t0_clk";
9421bade	389	int err;
061f8572	390	int channel;
9421bade	391
c9a787b9	392	chip = devm_pwmchip_alloc(&pdev->dev, NPWM, sizeof(*tcbpwmc));
af184748 UKK	393	if (IS_ERR(chip))
af184748 UKK	394	return PTR_ERR(chip);
c9a787b9	395	tcbpwmc = to_tcb_chip(chip);
0323e8fe	396
061f8572	397	err = of_property_read_u32(np, "reg", &channel);
9421bade BB	398	if (err < 0) {
9421bade BB	399	dev_err(&pdev->dev,
061f8572	400	"failed to get Timer Counter Block channel from device tree (error: %d)\n",
9421bade BB	401	err);
	402	return err;
	403	}
	404
c9a787b9 UKK	405	tcbpwmc->regmap = syscon_node_to_regmap(np->parent);
	406	if (IS_ERR(tcbpwmc->regmap))
	407	return PTR_ERR(tcbpwmc->regmap);
061f8572	408
c9a787b9 UKK	409	tcbpwmc->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
	410	if (IS_ERR(tcbpwmc->slow_clk))
	411	return PTR_ERR(tcbpwmc->slow_clk);
061f8572 AB	412
061f8572 AB	413	clk_name[1] += channel;
c9a787b9 UKK	414	tcbpwmc->clk = of_clk_get_by_name(np->parent, clk_name);
	415	if (IS_ERR(tcbpwmc->clk))
	416	tcbpwmc->clk = of_clk_get_by_name(np->parent, "t0_clk");
	417	if (IS_ERR(tcbpwmc->clk)) {
	418	err = PTR_ERR(tcbpwmc->clk);
c1162232 UKK	419	goto err_slow_clk;
c1162232 UKK	420	}
061f8572 AB	421
	422	match = of_match_node(atmel_tcb_of_match, np->parent);
	423	config = match->data;
9421bade	424
34cbcd72	425	if (config->has_gclk) {
c9a787b9 UKK	426	tcbpwmc->gclk = of_clk_get_by_name(np->parent, "gclk");
	427	if (IS_ERR(tcbpwmc->gclk)) {
	428	err = PTR_ERR(tcbpwmc->gclk);
c1162232 UKK	429	goto err_clk;
c1162232 UKK	430	}
9421bade BB	431	}
9421bade BB	432
dfab73eb	433	chip->ops = &atmel_tcb_pwm_ops;
c9a787b9 UKK	434	tcbpwmc->channel = channel;
c9a787b9 UKK	435	tcbpwmc->width = config->counter_width;
9421bade	436
c9a787b9	437	err = clk_prepare_enable(tcbpwmc->slow_clk);
7d8d05d1	438	if (err)
c1162232	439	goto err_gclk;
7d8d05d1	440
c9a787b9	441	spin_lock_init(&tcbpwmc->lock);
9421bade	442
dfab73eb	443	err = pwmchip_add(chip);
7d8d05d1 BB	444	if (err < 0)
7d8d05d1 BB	445	goto err_disable_clk;
9421bade	446
dfab73eb	447	platform_set_drvdata(pdev, chip);
9421bade BB	448
9421bade BB	449	return 0;
7d8d05d1 BB	450
7d8d05d1 BB	451	err_disable_clk:
c9a787b9	452	clk_disable_unprepare(tcbpwmc->slow_clk);
7d8d05d1	453
c1162232	454	err_gclk:
c9a787b9	455	clk_put(tcbpwmc->gclk);
c1162232 UKK	456
c1162232 UKK	457	err_clk:
c9a787b9	458	clk_put(tcbpwmc->clk);
c1162232	459
061f8572	460	err_slow_clk:
c9a787b9	461	clk_put(tcbpwmc->slow_clk);
7d8d05d1 BB	462
7d8d05d1 BB	463	return err;
9421bade BB	464	}
9421bade BB	465
9609284a	466	static void atmel_tcb_pwm_remove(struct platform_device *pdev)
9421bade	467	{
dfab73eb	468	struct pwm_chip *chip = platform_get_drvdata(pdev);
c9a787b9	469	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
9421bade	470
dfab73eb	471	pwmchip_remove(chip);
9421bade	472
c9a787b9 UKK	473	clk_disable_unprepare(tcbpwmc->slow_clk);
	474	clk_put(tcbpwmc->gclk);
	475	clk_put(tcbpwmc->clk);
	476	clk_put(tcbpwmc->slow_clk);
9421bade BB	477	}
	478
	479	static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
	480	{ .compatible = "atmel,tcb-pwm", },
	481	{ /* sentinel */ }
	482	};
	483	MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
	484
1b3d9a93 RI	485	static int atmel_tcb_pwm_suspend(struct device *dev)
1b3d9a93 RI	486	{
dfab73eb	487	struct pwm_chip *chip = dev_get_drvdata(dev);
c9a787b9 UKK	488	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	489	struct atmel_tcb_channel *chan = &tcbpwmc->bkup;
	490	unsigned int channel = tcbpwmc->channel;
1b3d9a93	491
c9a787b9 UKK	492	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
	493	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
	494	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
	495	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
1b3d9a93	496
1b3d9a93 RI	497	return 0;
	498	}
	499
	500	static int atmel_tcb_pwm_resume(struct device *dev)
	501	{
dfab73eb	502	struct pwm_chip *chip = dev_get_drvdata(dev);
c9a787b9 UKK	503	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	504	struct atmel_tcb_channel *chan = &tcbpwmc->bkup;
	505	unsigned int channel = tcbpwmc->channel;
1b3d9a93	506
c9a787b9 UKK	507	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
	508	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
	509	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
	510	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
061f8572 AB	511
061f8572 AB	512	if (chan->enabled)
c9a787b9	513	regmap_write(tcbpwmc->regmap,
061f8572 AB	514	ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG,
061f8572 AB	515	ATMEL_TC_REG(channel, CCR));
1b3d9a93	516
1b3d9a93 RI	517	return 0;
1b3d9a93 RI	518	}
1b3d9a93	519
a7bab37f UKK	520	static DEFINE_SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
a7bab37f UKK	521	atmel_tcb_pwm_resume);
1b3d9a93	522
9421bade BB	523	static struct platform_driver atmel_tcb_pwm_driver = {
	524	.driver = {
	525	.name = "atmel-tcb-pwm",
	526	.of_match_table = atmel_tcb_pwm_dt_ids,
a7bab37f	527	.pm = pm_ptr(&atmel_tcb_pwm_pm_ops),
9421bade BB	528	},
9421bade BB	529	.probe = atmel_tcb_pwm_probe,
8db7fdff	530	.remove = atmel_tcb_pwm_remove,
9421bade BB	531	};
	532	module_platform_driver(atmel_tcb_pwm_driver);
	533
	534	MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
	535	MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
	536	MODULE_LICENSE("GPL v2");