[linux-block.git] / drivers / pwm / pwm-atmel-tcb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) Overkiz SAS 2012
 *
 * Author: Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <soc/at91/atmel_tcb.h>

#define NPWM	2

#define ATMEL_TC_ACMR_MASK	(ATMEL_TC_ACPA | ATMEL_TC_ACPC |	\
				 ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)

#define ATMEL_TC_BCMR_MASK	(ATMEL_TC_BCPB | ATMEL_TC_BCPC |	\
				 ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)

struct atmel_tcb_pwm_device {
	enum pwm_polarity polarity;	/* PWM polarity */
	unsigned div;			/* PWM clock divider */
	unsigned duty;			/* PWM duty expressed in clk cycles */
	unsigned period;		/* PWM period expressed in clk cycles */
};

struct atmel_tcb_channel {
	u32 enabled;
	u32 cmr;
	u32 ra;
	u32 rb;
	u32 rc;
};

struct atmel_tcb_pwm_chip {
	struct pwm_chip chip;
	spinlock_t lock;
	u8 channel;
	u8 width;
	struct regmap *regmap;
	struct clk *clk;
	struct clk *gclk;
	struct clk *slow_clk;
	struct atmel_tcb_pwm_device *pwms[NPWM];
	struct atmel_tcb_channel bkup;
};

static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };

static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct atmel_tcb_pwm_chip, chip);
}

static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
				      struct pwm_device *pwm,
				      enum pwm_polarity polarity)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];

	tcbpwm->polarity = polarity;

	return 0;
}

static int atmel_tcb_pwm_request(struct pwm_chip *chip,
				 struct pwm_device *pwm)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm;
	unsigned cmr;
	int ret;

	tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
	if (!tcbpwm)
		return -ENOMEM;

	ret = clk_prepare_enable(tcbpwmc->clk);
	if (ret) {
		devm_kfree(chip->dev, tcbpwm);
		return ret;
	}

	tcbpwm->polarity = PWM_POLARITY_NORMAL;
	tcbpwm->duty = 0;
	tcbpwm->period = 0;
	tcbpwm->div = 0;

	spin_lock(&tcbpwmc->lock);
	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
	/*
	 * Get init config from Timer Counter registers if
	 * Timer Counter is already configured as a PWM generator.
	 */
	if (cmr & ATMEL_TC_WAVE) {
		if (pwm->hwpwm == 0)
			regmap_read(tcbpwmc->regmap,
				    ATMEL_TC_REG(tcbpwmc->channel, RA),
				    &tcbpwm->duty);
		else
			regmap_read(tcbpwmc->regmap,
				    ATMEL_TC_REG(tcbpwmc->channel, RB),
				    &tcbpwm->duty);

		tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
		regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
			    &tcbpwm->period);
		cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
			ATMEL_TC_BCMR_MASK);
	} else
		cmr = 0;

	cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
	spin_unlock(&tcbpwmc->lock);

	tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;

	return 0;
}

static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];

	clk_disable_unprepare(tcbpwmc->clk);
	tcbpwmc->pwms[pwm->hwpwm] = NULL;
	devm_kfree(chip->dev, tcbpwm);
}

static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
	unsigned cmr;
	enum pwm_polarity polarity = tcbpwm->polarity;

	/*
	 * If duty is 0 the timer will be stopped and we have to
	 * configure the output correctly on software trigger:
	 *  - set output to high if PWM_POLARITY_INVERSED
	 *  - set output to low if PWM_POLARITY_NORMAL
	 *
	 * This is why we're reverting polarity in this case.
	 */
	if (tcbpwm->duty == 0)
		polarity = !polarity;

	spin_lock(&tcbpwmc->lock);
	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);

	/* flush old setting and set the new one */
	if (pwm->hwpwm == 0) {
		cmr &= ~ATMEL_TC_ACMR_MASK;
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_ASWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_ASWTRG_SET;
	} else {
		cmr &= ~ATMEL_TC_BCMR_MASK;
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_BSWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_BSWTRG_SET;
	}

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);

	/*
	 * Use software trigger to apply the new setting.
	 * If both PWM devices in this group are disabled we stop the clock.
	 */
	if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, CCR),
			     ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
		tcbpwmc->bkup.enabled = 1;
	} else {
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, CCR),
			     ATMEL_TC_SWTRG);
		tcbpwmc->bkup.enabled = 0;
	}

	spin_unlock(&tcbpwmc->lock);
}

static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
	u32 cmr;
	enum pwm_polarity polarity = tcbpwm->polarity;

	/*
	 * If duty is 0 the timer will be stopped and we have to
	 * configure the output correctly on software trigger:
	 *  - set output to high if PWM_POLARITY_INVERSED
	 *  - set output to low if PWM_POLARITY_NORMAL
	 *
	 * This is why we're reverting polarity in this case.
	 */
	if (tcbpwm->duty == 0)
		polarity = !polarity;

	spin_lock(&tcbpwmc->lock);
	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);

	/* flush old setting and set the new one */
	cmr &= ~ATMEL_TC_TCCLKS;

	if (pwm->hwpwm == 0) {
		cmr &= ~ATMEL_TC_ACMR_MASK;

		/* Set CMR flags according to given polarity */
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_ASWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_ASWTRG_SET;
	} else {
		cmr &= ~ATMEL_TC_BCMR_MASK;
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_BSWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_BSWTRG_SET;
	}

	/*
	 * If duty is 0 or equal to period there's no need to register
	 * a specific action on RA/RB and RC compare.
	 * The output will be configured on software trigger and keep
	 * this config till next config call.
	 */
	if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
		if (pwm->hwpwm == 0) {
			if (polarity == PWM_POLARITY_INVERSED)
				cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
			else
				cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
		} else {
			if (polarity == PWM_POLARITY_INVERSED)
				cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
			else
				cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
		}
	}

	cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);

	if (pwm->hwpwm == 0)
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, RA),
			     tcbpwm->duty);
	else
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, RB),
			     tcbpwm->duty);

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
		     tcbpwm->period);

	/* Use software trigger to apply the new setting */
	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
		     ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
	tcbpwmc->bkup.enabled = 1;
	spin_unlock(&tcbpwmc->lock);
	return 0;
}

static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
				int duty_ns, int period_ns)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
	struct atmel_tcb_pwm_device *atcbpwm = NULL;
	int i = 0;
	int slowclk = 0;
	unsigned period;
	unsigned duty;
	unsigned rate = clk_get_rate(tcbpwmc->clk);
	unsigned long long min;
	unsigned long long max;

	/*
	 * Find best clk divisor:
	 * the smallest divisor which can fulfill the period_ns requirements.
	 * If there is a gclk, the first divisor is actually the gclk selector
	 */
	if (tcbpwmc->gclk)
		i = 1;
	for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
		if (atmel_tcb_divisors[i] == 0) {
			slowclk = i;
			continue;
		}
		min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
		max = min << tcbpwmc->width;
		if (max >= period_ns)
			break;
	}

	/*
	 * If none of the divisor are small enough to represent period_ns
	 * take slow clock (32KHz).
	 */
	if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
		i = slowclk;
		rate = clk_get_rate(tcbpwmc->slow_clk);
		min = div_u64(NSEC_PER_SEC, rate);
		max = min << tcbpwmc->width;

		/* If period is too big return ERANGE error */
		if (max < period_ns)
			return -ERANGE;
	}

	duty = div_u64(duty_ns, min);
	period = div_u64(period_ns, min);

	if (pwm->hwpwm == 0)
		atcbpwm = tcbpwmc->pwms[1];
	else
		atcbpwm = tcbpwmc->pwms[0];

	/*
	 * PWM devices provided by the TCB driver are grouped by 2.
	 * PWM devices in a given group must be configured with the
	 * same period_ns.
	 *
	 * We're checking the period value of the second PWM device
	 * in this group before applying the new config.
	 */
	if ((atcbpwm && atcbpwm->duty > 0 &&
			atcbpwm->duty != atcbpwm->period) &&
		(atcbpwm->div != i || atcbpwm->period != period)) {
		dev_err(chip->dev,
			"failed to configure period_ns: PWM group already configured with a different value\n");
		return -EINVAL;
	}

	tcbpwm->period = period;
	tcbpwm->div = i;
	tcbpwm->duty = duty;

	return 0;
}

static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			       const struct pwm_state *state)
{
	int duty_cycle, period;
	int ret;

	/* This function only sets a flag in driver data */
	atmel_tcb_pwm_set_polarity(chip, pwm, state->polarity);

	if (!state->enabled) {
		atmel_tcb_pwm_disable(chip, pwm);
		return 0;
	}

	period = state->period < INT_MAX ? state->period : INT_MAX;
	duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;

	ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
	if (ret)
		return ret;

	return atmel_tcb_pwm_enable(chip, pwm);
}

static const struct pwm_ops atmel_tcb_pwm_ops = {
	.request = atmel_tcb_pwm_request,
	.free = atmel_tcb_pwm_free,
	.apply = atmel_tcb_pwm_apply,
	.owner = THIS_MODULE,
};

static struct atmel_tcb_config tcb_rm9200_config = {
	.counter_width = 16,
};

static struct atmel_tcb_config tcb_sam9x5_config = {
	.counter_width = 32,
};

static struct atmel_tcb_config tcb_sama5d2_config = {
	.counter_width = 32,
	.has_gclk = 1,
};

static const struct of_device_id atmel_tcb_of_match[] = {
	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
	{ /* sentinel */ }
};

static int atmel_tcb_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct atmel_tcb_pwm_chip *tcbpwm;
	const struct atmel_tcb_config *config;
	struct device_node *np = pdev->dev.of_node;
	char clk_name[] = "t0_clk";
	int err;
	int channel;

	tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
	if (tcbpwm == NULL)
		return -ENOMEM;

	err = of_property_read_u32(np, "reg", &channel);
	if (err < 0) {
		dev_err(&pdev->dev,
			"failed to get Timer Counter Block channel from device tree (error: %d)\n",
			err);
		return err;
	}

	tcbpwm->regmap = syscon_node_to_regmap(np->parent);
	if (IS_ERR(tcbpwm->regmap))
		return PTR_ERR(tcbpwm->regmap);

	tcbpwm->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
	if (IS_ERR(tcbpwm->slow_clk))
		return PTR_ERR(tcbpwm->slow_clk);

	clk_name[1] += channel;
	tcbpwm->clk = of_clk_get_by_name(np->parent, clk_name);
	if (IS_ERR(tcbpwm->clk))
		tcbpwm->clk = of_clk_get_by_name(np->parent, "t0_clk");
	if (IS_ERR(tcbpwm->clk))
		return PTR_ERR(tcbpwm->clk);

	match = of_match_node(atmel_tcb_of_match, np->parent);
	config = match->data;

	if (config->has_gclk) {
		tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk");
		if (IS_ERR(tcbpwm->gclk))
			return PTR_ERR(tcbpwm->gclk);
	}

	tcbpwm->chip.dev = &pdev->dev;
	tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
	tcbpwm->chip.npwm = NPWM;
	tcbpwm->channel = channel;
	tcbpwm->width = config->counter_width;

	err = clk_prepare_enable(tcbpwm->slow_clk);
	if (err)
		goto err_slow_clk;

	spin_lock_init(&tcbpwm->lock);

	err = pwmchip_add(&tcbpwm->chip);
	if (err < 0)
		goto err_disable_clk;

	platform_set_drvdata(pdev, tcbpwm);

	return 0;

err_disable_clk:
	clk_disable_unprepare(tcbpwm->slow_clk);

err_slow_clk:
	clk_put(tcbpwm->slow_clk);

	return err;
}

static void atmel_tcb_pwm_remove(struct platform_device *pdev)
{
	struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);

	pwmchip_remove(&tcbpwm->chip);

	clk_disable_unprepare(tcbpwm->slow_clk);
	clk_put(tcbpwm->slow_clk);
	clk_put(tcbpwm->clk);
}

static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
	{ .compatible = "atmel,tcb-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);

#ifdef CONFIG_PM_SLEEP
static int atmel_tcb_pwm_suspend(struct device *dev)
{
	struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
	unsigned int channel = tcbpwm->channel;

	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);

	return 0;
}

static int atmel_tcb_pwm_resume(struct device *dev)
{
	struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
	unsigned int channel = tcbpwm->channel;

	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);

	if (chan->enabled)
		regmap_write(tcbpwm->regmap,
			     ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
			     ATMEL_TC_REG(channel, CCR));

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
			 atmel_tcb_pwm_resume);

static struct platform_driver atmel_tcb_pwm_driver = {
	.driver = {
		.name = "atmel-tcb-pwm",
		.of_match_table = atmel_tcb_pwm_dt_ids,
		.pm = &atmel_tcb_pwm_pm_ops,
	},
	.probe = atmel_tcb_pwm_probe,
	.remove_new = atmel_tcb_pwm_remove,
};
module_platform_driver(atmel_tcb_pwm_driver);

MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
af873fce	1	// SPDX-License-Identifier: GPL-2.0-only
9421bade BB	2	/*
	3	* Copyright (C) Overkiz SAS 2012
	4	*
	5	* Author: Boris BREZILLON <b.brezillon@overkiz.com>
9421bade BB	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/init.h>
	10	#include <linux/clocksource.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/ioport.h>
	18	#include <linux/io.h>
061f8572	19	#include <linux/mfd/syscon.h>
9421bade	20	#include <linux/platform_device.h>
9421bade	21	#include <linux/pwm.h>
0a41b0c5	22	#include <linux/of.h>
061f8572	23	#include <linux/regmap.h>
9421bade	24	#include <linux/slab.h>
c2c9136b	25	#include <soc/at91/atmel_tcb.h>
9421bade	26
061f8572	27	#define NPWM 2
9421bade BB	28
	29	#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA \| ATMEL_TC_ACPC \| \
	30	ATMEL_TC_AEEVT \| ATMEL_TC_ASWTRG)
	31
	32	#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB \| ATMEL_TC_BCPC \| \
	33	ATMEL_TC_BEEVT \| ATMEL_TC_BSWTRG)
	34
	35	struct atmel_tcb_pwm_device {
	36	enum pwm_polarity polarity; /* PWM polarity */
	37	unsigned div; /* PWM clock divider */
	38	unsigned duty; /* PWM duty expressed in clk cycles */
	39	unsigned period; /* PWM period expressed in clk cycles */
	40	};
	41
1b3d9a93 RI	42	struct atmel_tcb_channel {
	43	u32 enabled;
	44	u32 cmr;
	45	u32 ra;
	46	u32 rb;
	47	u32 rc;
	48	};
	49
9421bade BB	50	struct atmel_tcb_pwm_chip {
	51	struct pwm_chip chip;
	52	spinlock_t lock;
061f8572 AB	53	u8 channel;
	54	u8 width;
	55	struct regmap *regmap;
	56	struct clk *clk;
34cbcd72	57	struct clk *gclk;
061f8572	58	struct clk *slow_clk;
9421bade	59	struct atmel_tcb_pwm_device *pwms[NPWM];
061f8572	60	struct atmel_tcb_channel bkup;
9421bade BB	61	};
9421bade BB	62
d7b44083	63	static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
061f8572	64
9421bade BB	65	static inline struct atmel_tcb_pwm_chip to_tcb_chip(struct pwm_chip chip)
	66	{
	67	return container_of(chip, struct atmel_tcb_pwm_chip, chip);
	68	}
	69
	70	static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
	71	struct pwm_device *pwm,
	72	enum pwm_polarity polarity)
	73	{
fdaa6efc UKK	74	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
fdaa6efc UKK	75	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
9421bade BB	76
	77	tcbpwm->polarity = polarity;
	78
	79	return 0;
	80	}
	81
	82	static int atmel_tcb_pwm_request(struct pwm_chip *chip,
	83	struct pwm_device *pwm)
	84	{
	85	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	86	struct atmel_tcb_pwm_device *tcbpwm;
9421bade BB	87	unsigned cmr;
	88	int ret;
	89
	90	tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
	91	if (!tcbpwm)
	92	return -ENOMEM;
	93
061f8572	94	ret = clk_prepare_enable(tcbpwmc->clk);
9421bade BB	95	if (ret) {
	96	devm_kfree(chip->dev, tcbpwm);
	97	return ret;
	98	}
	99
9421bade BB	100	tcbpwm->polarity = PWM_POLARITY_NORMAL;
	101	tcbpwm->duty = 0;
	102	tcbpwm->period = 0;
	103	tcbpwm->div = 0;
	104
	105	spin_lock(&tcbpwmc->lock);
061f8572	106	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
9421bade BB	107	/*
	108	* Get init config from Timer Counter registers if
	109	* Timer Counter is already configured as a PWM generator.
	110	*/
	111	if (cmr & ATMEL_TC_WAVE) {
061f8572 AB	112	if (pwm->hwpwm == 0)
	113	regmap_read(tcbpwmc->regmap,
	114	ATMEL_TC_REG(tcbpwmc->channel, RA),
	115	&tcbpwm->duty);
9421bade	116	else
061f8572 AB	117	regmap_read(tcbpwmc->regmap,
	118	ATMEL_TC_REG(tcbpwmc->channel, RB),
	119	&tcbpwm->duty);
9421bade BB	120
9421bade BB	121	tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
061f8572 AB	122	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
061f8572 AB	123	&tcbpwm->period);
9421bade BB	124	cmr &= (ATMEL_TC_TCCLKS \| ATMEL_TC_ACMR_MASK \|
	125	ATMEL_TC_BCMR_MASK);
	126	} else
	127	cmr = 0;
	128
	129	cmr \|= ATMEL_TC_WAVE \| ATMEL_TC_WAVESEL_UP_AUTO \| ATMEL_TC_EEVT_XC0;
061f8572	130	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
9421bade BB	131	spin_unlock(&tcbpwmc->lock);
	132
	133	tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;
	134
	135	return 0;
	136	}
	137
	138	static void atmel_tcb_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	139	{
	140	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
fdaa6efc	141	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
9421bade	142
061f8572	143	clk_disable_unprepare(tcbpwmc->clk);
9421bade BB	144	tcbpwmc->pwms[pwm->hwpwm] = NULL;
	145	devm_kfree(chip->dev, tcbpwm);
	146	}
	147
	148	static void atmel_tcb_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	149	{
	150	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
fdaa6efc	151	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
9421bade BB	152	unsigned cmr;
	153	enum pwm_polarity polarity = tcbpwm->polarity;
	154
	155	/*
	156	* If duty is 0 the timer will be stopped and we have to
	157	* configure the output correctly on software trigger:
	158	* - set output to high if PWM_POLARITY_INVERSED
	159	* - set output to low if PWM_POLARITY_NORMAL
	160	*
	161	* This is why we're reverting polarity in this case.
	162	*/
	163	if (tcbpwm->duty == 0)
	164	polarity = !polarity;
	165
	166	spin_lock(&tcbpwmc->lock);
061f8572	167	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
9421bade BB	168
9421bade BB	169	/* flush old setting and set the new one */
061f8572	170	if (pwm->hwpwm == 0) {
9421bade BB	171	cmr &= ~ATMEL_TC_ACMR_MASK;
	172	if (polarity == PWM_POLARITY_INVERSED)
	173	cmr \|= ATMEL_TC_ASWTRG_CLEAR;
	174	else
	175	cmr \|= ATMEL_TC_ASWTRG_SET;
	176	} else {
	177	cmr &= ~ATMEL_TC_BCMR_MASK;
	178	if (polarity == PWM_POLARITY_INVERSED)
	179	cmr \|= ATMEL_TC_BSWTRG_CLEAR;
	180	else
	181	cmr \|= ATMEL_TC_BSWTRG_SET;
	182	}
	183
061f8572	184	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
9421bade BB	185
	186	/*
	187	* Use software trigger to apply the new setting.
	188	* If both PWM devices in this group are disabled we stop the clock.
	189	*/
1b3d9a93	190	if (!(cmr & (ATMEL_TC_ACPC \| ATMEL_TC_BCPC))) {
061f8572 AB	191	regmap_write(tcbpwmc->regmap,
	192	ATMEL_TC_REG(tcbpwmc->channel, CCR),
	193	ATMEL_TC_SWTRG \| ATMEL_TC_CLKDIS);
	194	tcbpwmc->bkup.enabled = 1;
1b3d9a93	195	} else {
061f8572 AB	196	regmap_write(tcbpwmc->regmap,
	197	ATMEL_TC_REG(tcbpwmc->channel, CCR),
	198	ATMEL_TC_SWTRG);
	199	tcbpwmc->bkup.enabled = 0;
1b3d9a93	200	}
9421bade BB	201
	202	spin_unlock(&tcbpwmc->lock);
	203	}
	204
	205	static int atmel_tcb_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	206	{
	207	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
fdaa6efc	208	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
9421bade BB	209	u32 cmr;
	210	enum pwm_polarity polarity = tcbpwm->polarity;
	211
	212	/*
	213	* If duty is 0 the timer will be stopped and we have to
	214	* configure the output correctly on software trigger:
	215	* - set output to high if PWM_POLARITY_INVERSED
	216	* - set output to low if PWM_POLARITY_NORMAL
	217	*
	218	* This is why we're reverting polarity in this case.
	219	*/
	220	if (tcbpwm->duty == 0)
	221	polarity = !polarity;
	222
	223	spin_lock(&tcbpwmc->lock);
061f8572	224	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
9421bade BB	225
	226	/* flush old setting and set the new one */
	227	cmr &= ~ATMEL_TC_TCCLKS;
	228
061f8572	229	if (pwm->hwpwm == 0) {
9421bade BB	230	cmr &= ~ATMEL_TC_ACMR_MASK;
	231
	232	/* Set CMR flags according to given polarity */
	233	if (polarity == PWM_POLARITY_INVERSED)
	234	cmr \|= ATMEL_TC_ASWTRG_CLEAR;
	235	else
	236	cmr \|= ATMEL_TC_ASWTRG_SET;
	237	} else {
	238	cmr &= ~ATMEL_TC_BCMR_MASK;
	239	if (polarity == PWM_POLARITY_INVERSED)
	240	cmr \|= ATMEL_TC_BSWTRG_CLEAR;
	241	else
	242	cmr \|= ATMEL_TC_BSWTRG_SET;
	243	}
	244
	245	/*
	246	* If duty is 0 or equal to period there's no need to register
	247	* a specific action on RA/RB and RC compare.
	248	* The output will be configured on software trigger and keep
	249	* this config till next config call.
	250	*/
	251	if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
061f8572	252	if (pwm->hwpwm == 0) {
9421bade BB	253	if (polarity == PWM_POLARITY_INVERSED)
	254	cmr \|= ATMEL_TC_ACPA_SET \| ATMEL_TC_ACPC_CLEAR;
	255	else
	256	cmr \|= ATMEL_TC_ACPA_CLEAR \| ATMEL_TC_ACPC_SET;
	257	} else {
	258	if (polarity == PWM_POLARITY_INVERSED)
	259	cmr \|= ATMEL_TC_BCPB_SET \| ATMEL_TC_BCPC_CLEAR;
	260	else
	261	cmr \|= ATMEL_TC_BCPB_CLEAR \| ATMEL_TC_BCPC_SET;
	262	}
	263	}
	264
f3a82170 BB	265	cmr \|= (tcbpwm->div & ATMEL_TC_TCCLKS);
f3a82170 BB	266
061f8572	267	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
9421bade	268
061f8572 AB	269	if (pwm->hwpwm == 0)
	270	regmap_write(tcbpwmc->regmap,
	271	ATMEL_TC_REG(tcbpwmc->channel, RA),
	272	tcbpwm->duty);
9421bade	273	else
061f8572 AB	274	regmap_write(tcbpwmc->regmap,
	275	ATMEL_TC_REG(tcbpwmc->channel, RB),
	276	tcbpwm->duty);
9421bade	277
061f8572 AB	278	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
061f8572 AB	279	tcbpwm->period);
9421bade BB	280
9421bade BB	281	/* Use software trigger to apply the new setting */
061f8572 AB	282	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
	283	ATMEL_TC_SWTRG \| ATMEL_TC_CLKEN);
	284	tcbpwmc->bkup.enabled = 1;
9421bade BB	285	spin_unlock(&tcbpwmc->lock);
	286	return 0;
	287	}
	288
	289	static int atmel_tcb_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	290	int duty_ns, int period_ns)
	291	{
	292	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
fdaa6efc	293	struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
9421bade	294	struct atmel_tcb_pwm_device *atcbpwm = NULL;
34cbcd72	295	int i = 0;
9421bade BB	296	int slowclk = 0;
	297	unsigned period;
	298	unsigned duty;
061f8572	299	unsigned rate = clk_get_rate(tcbpwmc->clk);
9421bade BB	300	unsigned long long min;
	301	unsigned long long max;
	302
	303	/*
	304	* Find best clk divisor:
	305	* the smallest divisor which can fulfill the period_ns requirements.
f6bc65d3	306	* If there is a gclk, the first divisor is actually the gclk selector
9421bade	307	*/
34cbcd72 AB	308	if (tcbpwmc->gclk)
	309	i = 1;
	310	for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
061f8572	311	if (atmel_tcb_divisors[i] == 0) {
9421bade BB	312	slowclk = i;
	313	continue;
	314	}
061f8572 AB	315	min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
061f8572 AB	316	max = min << tcbpwmc->width;
9421bade BB	317	if (max >= period_ns)
	318	break;
	319	}
	320
	321	/*
	322	* If none of the divisor are small enough to represent period_ns
	323	* take slow clock (32KHz).
	324	*/
061f8572	325	if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
9421bade	326	i = slowclk;
061f8572	327	rate = clk_get_rate(tcbpwmc->slow_clk);
9421bade	328	min = div_u64(NSEC_PER_SEC, rate);
061f8572	329	max = min << tcbpwmc->width;
9421bade BB	330
	331	/* If period is too big return ERANGE error */
	332	if (max < period_ns)
	333	return -ERANGE;
	334	}
	335
	336	duty = div_u64(duty_ns, min);
	337	period = div_u64(period_ns, min);
	338
061f8572 AB	339	if (pwm->hwpwm == 0)
061f8572 AB	340	atcbpwm = tcbpwmc->pwms[1];
9421bade	341	else
061f8572	342	atcbpwm = tcbpwmc->pwms[0];
9421bade BB	343
9421bade BB	344	/*
061f8572	345	* PWM devices provided by the TCB driver are grouped by 2.
9421bade BB	346	* PWM devices in a given group must be configured with the
	347	* same period_ns.
	348	*
	349	* We're checking the period value of the second PWM device
	350	* in this group before applying the new config.
	351	*/
	352	if ((atcbpwm && atcbpwm->duty > 0 &&
	353	atcbpwm->duty != atcbpwm->period) &&
	354	(atcbpwm->div != i \|\| atcbpwm->period != period)) {
	355	dev_err(chip->dev,
	356	"failed to configure period_ns: PWM group already configured with a different value\n");
	357	return -EINVAL;
	358	}
	359
	360	tcbpwm->period = period;
	361	tcbpwm->div = i;
	362	tcbpwm->duty = duty;
	363
9421bade BB	364	return 0;
	365	}
	366
30882cf1 UKK	367	static int atmel_tcb_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	368	const struct pwm_state *state)
	369	{
	370	int duty_cycle, period;
	371	int ret;
	372
	373	/* This function only sets a flag in driver data */
	374	atmel_tcb_pwm_set_polarity(chip, pwm, state->polarity);
	375
	376	if (!state->enabled) {
	377	atmel_tcb_pwm_disable(chip, pwm);
	378	return 0;
	379	}
	380
	381	period = state->period < INT_MAX ? state->period : INT_MAX;
	382	duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;
	383
	384	ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
	385	if (ret)
	386	return ret;
	387
	388	return atmel_tcb_pwm_enable(chip, pwm);
	389	}
	390
9421bade BB	391	static const struct pwm_ops atmel_tcb_pwm_ops = {
	392	.request = atmel_tcb_pwm_request,
	393	.free = atmel_tcb_pwm_free,
30882cf1	394	.apply = atmel_tcb_pwm_apply,
83c80dc5	395	.owner = THIS_MODULE,
9421bade BB	396	};
9421bade BB	397
061f8572 AB	398	static struct atmel_tcb_config tcb_rm9200_config = {
	399	.counter_width = 16,
	400	};
	401
	402	static struct atmel_tcb_config tcb_sam9x5_config = {
	403	.counter_width = 32,
	404	};
	405
34cbcd72 AB	406	static struct atmel_tcb_config tcb_sama5d2_config = {
	407	.counter_width = 32,
	408	.has_gclk = 1,
	409	};
	410
061f8572 AB	411	static const struct of_device_id atmel_tcb_of_match[] = {
	412	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
	413	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
34cbcd72	414	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
061f8572 AB	415	{ /* sentinel */ }
	416	};
	417
9421bade BB	418	static int atmel_tcb_pwm_probe(struct platform_device *pdev)
9421bade BB	419	{
061f8572	420	const struct of_device_id *match;
9421bade	421	struct atmel_tcb_pwm_chip *tcbpwm;
061f8572	422	const struct atmel_tcb_config *config;
9421bade	423	struct device_node *np = pdev->dev.of_node;
061f8572	424	char clk_name[] = "t0_clk";
9421bade	425	int err;
061f8572	426	int channel;
9421bade	427
0323e8fe UKK	428	tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
	429	if (tcbpwm == NULL)
	430	return -ENOMEM;
	431
061f8572	432	err = of_property_read_u32(np, "reg", &channel);
9421bade BB	433	if (err < 0) {
9421bade BB	434	dev_err(&pdev->dev,
061f8572	435	"failed to get Timer Counter Block channel from device tree (error: %d)\n",
9421bade BB	436	err);
	437	return err;
	438	}
	439
0323e8fe UKK	440	tcbpwm->regmap = syscon_node_to_regmap(np->parent);
	441	if (IS_ERR(tcbpwm->regmap))
	442	return PTR_ERR(tcbpwm->regmap);
061f8572	443
0323e8fe UKK	444	tcbpwm->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
	445	if (IS_ERR(tcbpwm->slow_clk))
	446	return PTR_ERR(tcbpwm->slow_clk);
061f8572 AB	447
061f8572 AB	448	clk_name[1] += channel;
0323e8fe UKK	449	tcbpwm->clk = of_clk_get_by_name(np->parent, clk_name);
	450	if (IS_ERR(tcbpwm->clk))
	451	tcbpwm->clk = of_clk_get_by_name(np->parent, "t0_clk");
	452	if (IS_ERR(tcbpwm->clk))
	453	return PTR_ERR(tcbpwm->clk);
061f8572 AB	454
	455	match = of_match_node(atmel_tcb_of_match, np->parent);
	456	config = match->data;
9421bade	457
34cbcd72	458	if (config->has_gclk) {
0323e8fe UKK	459	tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk");
	460	if (IS_ERR(tcbpwm->gclk))
	461	return PTR_ERR(tcbpwm->gclk);
9421bade BB	462	}
	463
	464	tcbpwm->chip.dev = &pdev->dev;
	465	tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
9421bade	466	tcbpwm->chip.npwm = NPWM;
061f8572	467	tcbpwm->channel = channel;
061f8572	468	tcbpwm->width = config->counter_width;
9421bade	469
0323e8fe	470	err = clk_prepare_enable(tcbpwm->slow_clk);
7d8d05d1	471	if (err)
061f8572	472	goto err_slow_clk;
7d8d05d1	473
9421bade BB	474	spin_lock_init(&tcbpwm->lock);
	475
	476	err = pwmchip_add(&tcbpwm->chip);
7d8d05d1 BB	477	if (err < 0)
7d8d05d1 BB	478	goto err_disable_clk;
9421bade BB	479
	480	platform_set_drvdata(pdev, tcbpwm);
	481
	482	return 0;
7d8d05d1 BB	483
7d8d05d1 BB	484	err_disable_clk:
061f8572	485	clk_disable_unprepare(tcbpwm->slow_clk);
7d8d05d1	486
061f8572	487	err_slow_clk:
0323e8fe	488	clk_put(tcbpwm->slow_clk);
7d8d05d1 BB	489
7d8d05d1 BB	490	return err;
9421bade BB	491	}
9421bade BB	492
9609284a	493	static void atmel_tcb_pwm_remove(struct platform_device *pdev)
9421bade BB	494	{
9421bade BB	495	struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
9421bade	496
319333b0	497	pwmchip_remove(&tcbpwm->chip);
9421bade	498
c77e99f4 UKK	499	clk_disable_unprepare(tcbpwm->slow_clk);
	500	clk_put(tcbpwm->slow_clk);
	501	clk_put(tcbpwm->clk);
9421bade BB	502	}
	503
	504	static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
	505	{ .compatible = "atmel,tcb-pwm", },
	506	{ /* sentinel */ }
	507	};
	508	MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
	509
1b3d9a93 RI	510	#ifdef CONFIG_PM_SLEEP
	511	static int atmel_tcb_pwm_suspend(struct device *dev)
	512	{
692099cd	513	struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
061f8572 AB	514	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
061f8572 AB	515	unsigned int channel = tcbpwm->channel;
1b3d9a93	516
061f8572 AB	517	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
	518	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
	519	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
	520	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
1b3d9a93	521
1b3d9a93 RI	522	return 0;
	523	}
	524
	525	static int atmel_tcb_pwm_resume(struct device *dev)
	526	{
692099cd	527	struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
061f8572 AB	528	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
061f8572 AB	529	unsigned int channel = tcbpwm->channel;
1b3d9a93	530
061f8572 AB	531	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
	532	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
	533	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
	534	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
	535
	536	if (chan->enabled)
	537	regmap_write(tcbpwm->regmap,
	538	ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG,
	539	ATMEL_TC_REG(channel, CCR));
1b3d9a93	540
1b3d9a93 RI	541	return 0;
	542	}
	543	#endif
	544
	545	static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
	546	atmel_tcb_pwm_resume);
	547
9421bade BB	548	static struct platform_driver atmel_tcb_pwm_driver = {
	549	.driver = {
	550	.name = "atmel-tcb-pwm",
	551	.of_match_table = atmel_tcb_pwm_dt_ids,
1b3d9a93	552	.pm = &atmel_tcb_pwm_pm_ops,
9421bade BB	553	},
9421bade BB	554	.probe = atmel_tcb_pwm_probe,
9609284a	555	.remove_new = atmel_tcb_pwm_remove,
9421bade BB	556	};
	557	module_platform_driver(atmel_tcb_pwm_driver);
	558
	559	MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
	560	MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
	561	MODULE_LICENSE("GPL v2");