[linux-block.git] / drivers / pwm / pwm-atmel-tcb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) Overkiz SAS 2012
 *
 * Author: Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <soc/at91/atmel_tcb.h>

#define NPWM	2

#define ATMEL_TC_ACMR_MASK	(ATMEL_TC_ACPA | ATMEL_TC_ACPC |	\
				 ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)

#define ATMEL_TC_BCMR_MASK	(ATMEL_TC_BCPB | ATMEL_TC_BCPC |	\
				 ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)

struct atmel_tcb_pwm_device {
	unsigned div;			/* PWM clock divider */
	unsigned duty;			/* PWM duty expressed in clk cycles */
	unsigned period;		/* PWM period expressed in clk cycles */
};

struct atmel_tcb_channel {
	u32 enabled;
	u32 cmr;
	u32 ra;
	u32 rb;
	u32 rc;
};

struct atmel_tcb_pwm_chip {
	spinlock_t lock;
	u8 channel;
	u8 width;
	struct regmap *regmap;
	struct clk *clk;
	struct clk *gclk;
	struct clk *slow_clk;
	struct atmel_tcb_pwm_device pwms[NPWM];
	struct atmel_tcb_channel bkup;
};

static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };

static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static int atmel_tcb_pwm_request(struct pwm_chip *chip,
				 struct pwm_device *pwm)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
	unsigned cmr;
	int ret;

	ret = clk_prepare_enable(tcbpwmc->clk);
	if (ret)
		return ret;

	tcbpwm->duty = 0;
	tcbpwm->period = 0;
	tcbpwm->div = 0;

	spin_lock(&tcbpwmc->lock);
	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
	/*
	 * Get init config from Timer Counter registers if
	 * Timer Counter is already configured as a PWM generator.
	 */
	if (cmr & ATMEL_TC_WAVE) {
		if (pwm->hwpwm == 0)
			regmap_read(tcbpwmc->regmap,
				    ATMEL_TC_REG(tcbpwmc->channel, RA),
				    &tcbpwm->duty);
		else
			regmap_read(tcbpwmc->regmap,
				    ATMEL_TC_REG(tcbpwmc->channel, RB),
				    &tcbpwm->duty);

		tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
		regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
			    &tcbpwm->period);
		cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
			ATMEL_TC_BCMR_MASK);
	} else
		cmr = 0;

	cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
	spin_unlock(&tcbpwmc->lock);

	return 0;
}

static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);

	clk_disable_unprepare(tcbpwmc->clk);
}

static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
				  enum pwm_polarity polarity)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
	unsigned cmr;

	/*
	 * If duty is 0 the timer will be stopped and we have to
	 * configure the output correctly on software trigger:
	 *  - set output to high if PWM_POLARITY_INVERSED
	 *  - set output to low if PWM_POLARITY_NORMAL
	 *
	 * This is why we're reverting polarity in this case.
	 */
	if (tcbpwm->duty == 0)
		polarity = !polarity;

	spin_lock(&tcbpwmc->lock);
	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);

	/* flush old setting and set the new one */
	if (pwm->hwpwm == 0) {
		cmr &= ~ATMEL_TC_ACMR_MASK;
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_ASWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_ASWTRG_SET;
	} else {
		cmr &= ~ATMEL_TC_BCMR_MASK;
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_BSWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_BSWTRG_SET;
	}

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);

	/*
	 * Use software trigger to apply the new setting.
	 * If both PWM devices in this group are disabled we stop the clock.
	 */
	if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, CCR),
			     ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
		tcbpwmc->bkup.enabled = 1;
	} else {
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, CCR),
			     ATMEL_TC_SWTRG);
		tcbpwmc->bkup.enabled = 0;
	}

	spin_unlock(&tcbpwmc->lock);
}

static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
				enum pwm_polarity polarity)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
	u32 cmr;

	/*
	 * If duty is 0 the timer will be stopped and we have to
	 * configure the output correctly on software trigger:
	 *  - set output to high if PWM_POLARITY_INVERSED
	 *  - set output to low if PWM_POLARITY_NORMAL
	 *
	 * This is why we're reverting polarity in this case.
	 */
	if (tcbpwm->duty == 0)
		polarity = !polarity;

	spin_lock(&tcbpwmc->lock);
	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);

	/* flush old setting and set the new one */
	cmr &= ~ATMEL_TC_TCCLKS;

	if (pwm->hwpwm == 0) {
		cmr &= ~ATMEL_TC_ACMR_MASK;

		/* Set CMR flags according to given polarity */
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_ASWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_ASWTRG_SET;
	} else {
		cmr &= ~ATMEL_TC_BCMR_MASK;
		if (polarity == PWM_POLARITY_INVERSED)
			cmr |= ATMEL_TC_BSWTRG_CLEAR;
		else
			cmr |= ATMEL_TC_BSWTRG_SET;
	}

	/*
	 * If duty is 0 or equal to period there's no need to register
	 * a specific action on RA/RB and RC compare.
	 * The output will be configured on software trigger and keep
	 * this config till next config call.
	 */
	if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
		if (pwm->hwpwm == 0) {
			if (polarity == PWM_POLARITY_INVERSED)
				cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
			else
				cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
		} else {
			if (polarity == PWM_POLARITY_INVERSED)
				cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
			else
				cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
		}
	}

	cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);

	if (pwm->hwpwm == 0)
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, RA),
			     tcbpwm->duty);
	else
		regmap_write(tcbpwmc->regmap,
			     ATMEL_TC_REG(tcbpwmc->channel, RB),
			     tcbpwm->duty);

	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
		     tcbpwm->period);

	/* Use software trigger to apply the new setting */
	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
		     ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
	tcbpwmc->bkup.enabled = 1;
	spin_unlock(&tcbpwmc->lock);
	return 0;
}

static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
				int duty_ns, int period_ns)
{
	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
	struct atmel_tcb_pwm_device *atcbpwm = NULL;
	int i = 0;
	int slowclk = 0;
	unsigned period;
	unsigned duty;
	unsigned rate = clk_get_rate(tcbpwmc->clk);
	unsigned long long min;
	unsigned long long max;

	/*
	 * Find best clk divisor:
	 * the smallest divisor which can fulfill the period_ns requirements.
	 * If there is a gclk, the first divisor is actually the gclk selector
	 */
	if (tcbpwmc->gclk)
		i = 1;
	for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
		if (atmel_tcb_divisors[i] == 0) {
			slowclk = i;
			continue;
		}
		min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
		max = min << tcbpwmc->width;
		if (max >= period_ns)
			break;
	}

	/*
	 * If none of the divisor are small enough to represent period_ns
	 * take slow clock (32KHz).
	 */
	if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
		i = slowclk;
		rate = clk_get_rate(tcbpwmc->slow_clk);
		min = div_u64(NSEC_PER_SEC, rate);
		max = min << tcbpwmc->width;

		/* If period is too big return ERANGE error */
		if (max < period_ns)
			return -ERANGE;
	}

	duty = div_u64(duty_ns, min);
	period = div_u64(period_ns, min);

	if (pwm->hwpwm == 0)
		atcbpwm = &tcbpwmc->pwms[1];
	else
		atcbpwm = &tcbpwmc->pwms[0];

	/*
	 * PWM devices provided by the TCB driver are grouped by 2.
	 * PWM devices in a given group must be configured with the
	 * same period_ns.
	 *
	 * We're checking the period value of the second PWM device
	 * in this group before applying the new config.
	 */
	if ((atcbpwm && atcbpwm->duty > 0 &&
			atcbpwm->duty != atcbpwm->period) &&
		(atcbpwm->div != i || atcbpwm->period != period)) {
		dev_err(pwmchip_parent(chip),
			"failed to configure period_ns: PWM group already configured with a different value\n");
		return -EINVAL;
	}

	tcbpwm->period = period;
	tcbpwm->div = i;
	tcbpwm->duty = duty;

	return 0;
}

static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			       const struct pwm_state *state)
{
	int duty_cycle, period;
	int ret;

	if (!state->enabled) {
		atmel_tcb_pwm_disable(chip, pwm, state->polarity);
		return 0;
	}

	period = state->period < INT_MAX ? state->period : INT_MAX;
	duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;

	ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
	if (ret)
		return ret;

	return atmel_tcb_pwm_enable(chip, pwm, state->polarity);
}

static const struct pwm_ops atmel_tcb_pwm_ops = {
	.request = atmel_tcb_pwm_request,
	.free = atmel_tcb_pwm_free,
	.apply = atmel_tcb_pwm_apply,
};

static struct atmel_tcb_config tcb_rm9200_config = {
	.counter_width = 16,
};

static struct atmel_tcb_config tcb_sam9x5_config = {
	.counter_width = 32,
};

static struct atmel_tcb_config tcb_sama5d2_config = {
	.counter_width = 32,
	.has_gclk = 1,
};

static const struct of_device_id atmel_tcb_of_match[] = {
	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
	{ /* sentinel */ }
};

static int atmel_tcb_pwm_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	const struct of_device_id *match;
	struct atmel_tcb_pwm_chip *tcbpwm;
	const struct atmel_tcb_config *config;
	struct device_node *np = pdev->dev.of_node;
	char clk_name[] = "t0_clk";
	int err;
	int channel;

	chip = devm_pwmchip_alloc(&pdev->dev, NPWM, sizeof(*tcbpwm));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	tcbpwm = to_tcb_chip(chip);

	err = of_property_read_u32(np, "reg", &channel);
	if (err < 0) {
		dev_err(&pdev->dev,
			"failed to get Timer Counter Block channel from device tree (error: %d)\n",
			err);
		return err;
	}

	tcbpwm->regmap = syscon_node_to_regmap(np->parent);
	if (IS_ERR(tcbpwm->regmap))
		return PTR_ERR(tcbpwm->regmap);

	tcbpwm->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
	if (IS_ERR(tcbpwm->slow_clk))
		return PTR_ERR(tcbpwm->slow_clk);

	clk_name[1] += channel;
	tcbpwm->clk = of_clk_get_by_name(np->parent, clk_name);
	if (IS_ERR(tcbpwm->clk))
		tcbpwm->clk = of_clk_get_by_name(np->parent, "t0_clk");
	if (IS_ERR(tcbpwm->clk)) {
		err = PTR_ERR(tcbpwm->clk);
		goto err_slow_clk;
	}

	match = of_match_node(atmel_tcb_of_match, np->parent);
	config = match->data;

	if (config->has_gclk) {
		tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk");
		if (IS_ERR(tcbpwm->gclk)) {
			err = PTR_ERR(tcbpwm->gclk);
			goto err_clk;
		}
	}

	chip->ops = &atmel_tcb_pwm_ops;
	tcbpwm->channel = channel;
	tcbpwm->width = config->counter_width;

	err = clk_prepare_enable(tcbpwm->slow_clk);
	if (err)
		goto err_gclk;

	spin_lock_init(&tcbpwm->lock);

	err = pwmchip_add(chip);
	if (err < 0)
		goto err_disable_clk;

	platform_set_drvdata(pdev, chip);

	return 0;

err_disable_clk:
	clk_disable_unprepare(tcbpwm->slow_clk);

err_gclk:
	clk_put(tcbpwm->gclk);

err_clk:
	clk_put(tcbpwm->clk);

err_slow_clk:
	clk_put(tcbpwm->slow_clk);

	return err;
}

static void atmel_tcb_pwm_remove(struct platform_device *pdev)
{
	struct pwm_chip *chip = platform_get_drvdata(pdev);
	struct atmel_tcb_pwm_chip *tcbpwm = to_tcb_chip(chip);

	pwmchip_remove(chip);

	clk_disable_unprepare(tcbpwm->slow_clk);
	clk_put(tcbpwm->gclk);
	clk_put(tcbpwm->clk);
	clk_put(tcbpwm->slow_clk);
}

static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
	{ .compatible = "atmel,tcb-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);

static int atmel_tcb_pwm_suspend(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct atmel_tcb_pwm_chip *tcbpwm = to_tcb_chip(chip);
	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
	unsigned int channel = tcbpwm->channel;

	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);

	return 0;
}

static int atmel_tcb_pwm_resume(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct atmel_tcb_pwm_chip *tcbpwm = to_tcb_chip(chip);
	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
	unsigned int channel = tcbpwm->channel;

	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);

	if (chan->enabled)
		regmap_write(tcbpwm->regmap,
			     ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
			     ATMEL_TC_REG(channel, CCR));

	return 0;
}

static DEFINE_SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
				atmel_tcb_pwm_resume);

static struct platform_driver atmel_tcb_pwm_driver = {
	.driver = {
		.name = "atmel-tcb-pwm",
		.of_match_table = atmel_tcb_pwm_dt_ids,
		.pm = pm_ptr(&atmel_tcb_pwm_pm_ops),
	},
	.probe = atmel_tcb_pwm_probe,
	.remove_new = atmel_tcb_pwm_remove,
};
module_platform_driver(atmel_tcb_pwm_driver);

MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
af873fce	1	// SPDX-License-Identifier: GPL-2.0-only
9421bade BB	2	/*
	3	* Copyright (C) Overkiz SAS 2012
	4	*
	5	* Author: Boris BREZILLON <b.brezillon@overkiz.com>
9421bade BB	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/init.h>
	10	#include <linux/clocksource.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/ioport.h>
	18	#include <linux/io.h>
061f8572	19	#include <linux/mfd/syscon.h>
9421bade	20	#include <linux/platform_device.h>
9421bade	21	#include <linux/pwm.h>
0a41b0c5	22	#include <linux/of.h>
061f8572	23	#include <linux/regmap.h>
9421bade	24	#include <linux/slab.h>
c2c9136b	25	#include <soc/at91/atmel_tcb.h>
9421bade	26
061f8572	27	#define NPWM 2
9421bade BB	28
	29	#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA \| ATMEL_TC_ACPC \| \
	30	ATMEL_TC_AEEVT \| ATMEL_TC_ASWTRG)
	31
	32	#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB \| ATMEL_TC_BCPC \| \
	33	ATMEL_TC_BEEVT \| ATMEL_TC_BSWTRG)
	34
	35	struct atmel_tcb_pwm_device {
9421bade BB	36	unsigned div; /* PWM clock divider */
	37	unsigned duty; /* PWM duty expressed in clk cycles */
	38	unsigned period; /* PWM period expressed in clk cycles */
	39	};
	40
1b3d9a93 RI	41	struct atmel_tcb_channel {
	42	u32 enabled;
	43	u32 cmr;
	44	u32 ra;
	45	u32 rb;
	46	u32 rc;
	47	};
	48
9421bade	49	struct atmel_tcb_pwm_chip {
9421bade	50	spinlock_t lock;
061f8572 AB	51	u8 channel;
	52	u8 width;
	53	struct regmap *regmap;
	54	struct clk *clk;
34cbcd72	55	struct clk *gclk;
061f8572	56	struct clk *slow_clk;
78dca23b	57	struct atmel_tcb_pwm_device pwms[NPWM];
061f8572	58	struct atmel_tcb_channel bkup;
9421bade BB	59	};
9421bade BB	60
d7b44083	61	static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
061f8572	62
9421bade BB	63	static inline struct atmel_tcb_pwm_chip to_tcb_chip(struct pwm_chip chip)
9421bade BB	64	{
af184748	65	return pwmchip_get_drvdata(chip);
9421bade BB	66	}
9421bade BB	67
9421bade BB	68	static int atmel_tcb_pwm_request(struct pwm_chip *chip,
	69	struct pwm_device *pwm)
	70	{
	71	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
78dca23b	72	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
9421bade BB	73	unsigned cmr;
	74	int ret;
	75
061f8572	76	ret = clk_prepare_enable(tcbpwmc->clk);
78dca23b	77	if (ret)
9421bade	78	return ret;
9421bade	79
9421bade BB	80	tcbpwm->duty = 0;
	81	tcbpwm->period = 0;
	82	tcbpwm->div = 0;
	83
	84	spin_lock(&tcbpwmc->lock);
061f8572	85	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
9421bade BB	86	/*
	87	* Get init config from Timer Counter registers if
	88	* Timer Counter is already configured as a PWM generator.
	89	*/
	90	if (cmr & ATMEL_TC_WAVE) {
061f8572 AB	91	if (pwm->hwpwm == 0)
	92	regmap_read(tcbpwmc->regmap,
	93	ATMEL_TC_REG(tcbpwmc->channel, RA),
	94	&tcbpwm->duty);
9421bade	95	else
061f8572 AB	96	regmap_read(tcbpwmc->regmap,
	97	ATMEL_TC_REG(tcbpwmc->channel, RB),
	98	&tcbpwm->duty);
9421bade BB	99
9421bade BB	100	tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
061f8572 AB	101	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
061f8572 AB	102	&tcbpwm->period);
9421bade BB	103	cmr &= (ATMEL_TC_TCCLKS \| ATMEL_TC_ACMR_MASK \|
	104	ATMEL_TC_BCMR_MASK);
	105	} else
	106	cmr = 0;
	107
	108	cmr \|= ATMEL_TC_WAVE \| ATMEL_TC_WAVESEL_UP_AUTO \| ATMEL_TC_EEVT_XC0;
061f8572	109	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
9421bade BB	110	spin_unlock(&tcbpwmc->lock);
9421bade BB	111
9421bade BB	112	return 0;
	113	}
	114
	115	static void atmel_tcb_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	116	{
	117	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
9421bade	118
061f8572	119	clk_disable_unprepare(tcbpwmc->clk);
9421bade BB	120	}
9421bade BB	121
28a1dadc UKK	122	static void atmel_tcb_pwm_disable(struct pwm_chip chip, struct pwm_device pwm,
28a1dadc UKK	123	enum pwm_polarity polarity)
9421bade BB	124	{
9421bade BB	125	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
78dca23b	126	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
9421bade	127	unsigned cmr;
9421bade BB	128
	129	/*
	130	* If duty is 0 the timer will be stopped and we have to
	131	* configure the output correctly on software trigger:
	132	* - set output to high if PWM_POLARITY_INVERSED
	133	* - set output to low if PWM_POLARITY_NORMAL
	134	*
	135	* This is why we're reverting polarity in this case.
	136	*/
	137	if (tcbpwm->duty == 0)
	138	polarity = !polarity;
	139
	140	spin_lock(&tcbpwmc->lock);
061f8572	141	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
9421bade BB	142
9421bade BB	143	/* flush old setting and set the new one */
061f8572	144	if (pwm->hwpwm == 0) {
9421bade BB	145	cmr &= ~ATMEL_TC_ACMR_MASK;
	146	if (polarity == PWM_POLARITY_INVERSED)
	147	cmr \|= ATMEL_TC_ASWTRG_CLEAR;
	148	else
	149	cmr \|= ATMEL_TC_ASWTRG_SET;
	150	} else {
	151	cmr &= ~ATMEL_TC_BCMR_MASK;
	152	if (polarity == PWM_POLARITY_INVERSED)
	153	cmr \|= ATMEL_TC_BSWTRG_CLEAR;
	154	else
	155	cmr \|= ATMEL_TC_BSWTRG_SET;
	156	}
	157
061f8572	158	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
9421bade BB	159
	160	/*
	161	* Use software trigger to apply the new setting.
	162	* If both PWM devices in this group are disabled we stop the clock.
	163	*/
1b3d9a93	164	if (!(cmr & (ATMEL_TC_ACPC \| ATMEL_TC_BCPC))) {
061f8572 AB	165	regmap_write(tcbpwmc->regmap,
	166	ATMEL_TC_REG(tcbpwmc->channel, CCR),
	167	ATMEL_TC_SWTRG \| ATMEL_TC_CLKDIS);
	168	tcbpwmc->bkup.enabled = 1;
1b3d9a93	169	} else {
061f8572 AB	170	regmap_write(tcbpwmc->regmap,
	171	ATMEL_TC_REG(tcbpwmc->channel, CCR),
	172	ATMEL_TC_SWTRG);
	173	tcbpwmc->bkup.enabled = 0;
1b3d9a93	174	}
9421bade BB	175
	176	spin_unlock(&tcbpwmc->lock);
	177	}
	178
28a1dadc UKK	179	static int atmel_tcb_pwm_enable(struct pwm_chip chip, struct pwm_device pwm,
28a1dadc UKK	180	enum pwm_polarity polarity)
9421bade BB	181	{
9421bade BB	182	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
78dca23b	183	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
9421bade	184	u32 cmr;
9421bade BB	185
	186	/*
	187	* If duty is 0 the timer will be stopped and we have to
	188	* configure the output correctly on software trigger:
	189	* - set output to high if PWM_POLARITY_INVERSED
	190	* - set output to low if PWM_POLARITY_NORMAL
	191	*
	192	* This is why we're reverting polarity in this case.
	193	*/
	194	if (tcbpwm->duty == 0)
	195	polarity = !polarity;
	196
	197	spin_lock(&tcbpwmc->lock);
061f8572	198	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
9421bade BB	199
	200	/* flush old setting and set the new one */
	201	cmr &= ~ATMEL_TC_TCCLKS;
	202
061f8572	203	if (pwm->hwpwm == 0) {
9421bade BB	204	cmr &= ~ATMEL_TC_ACMR_MASK;
	205
	206	/* Set CMR flags according to given polarity */
	207	if (polarity == PWM_POLARITY_INVERSED)
	208	cmr \|= ATMEL_TC_ASWTRG_CLEAR;
	209	else
	210	cmr \|= ATMEL_TC_ASWTRG_SET;
	211	} else {
	212	cmr &= ~ATMEL_TC_BCMR_MASK;
	213	if (polarity == PWM_POLARITY_INVERSED)
	214	cmr \|= ATMEL_TC_BSWTRG_CLEAR;
	215	else
	216	cmr \|= ATMEL_TC_BSWTRG_SET;
	217	}
	218
	219	/*
	220	* If duty is 0 or equal to period there's no need to register
	221	* a specific action on RA/RB and RC compare.
	222	* The output will be configured on software trigger and keep
	223	* this config till next config call.
	224	*/
	225	if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
061f8572	226	if (pwm->hwpwm == 0) {
9421bade BB	227	if (polarity == PWM_POLARITY_INVERSED)
	228	cmr \|= ATMEL_TC_ACPA_SET \| ATMEL_TC_ACPC_CLEAR;
	229	else
	230	cmr \|= ATMEL_TC_ACPA_CLEAR \| ATMEL_TC_ACPC_SET;
	231	} else {
	232	if (polarity == PWM_POLARITY_INVERSED)
	233	cmr \|= ATMEL_TC_BCPB_SET \| ATMEL_TC_BCPC_CLEAR;
	234	else
	235	cmr \|= ATMEL_TC_BCPB_CLEAR \| ATMEL_TC_BCPC_SET;
	236	}
	237	}
	238
f3a82170 BB	239	cmr \|= (tcbpwm->div & ATMEL_TC_TCCLKS);
f3a82170 BB	240
061f8572	241	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
9421bade	242
061f8572 AB	243	if (pwm->hwpwm == 0)
	244	regmap_write(tcbpwmc->regmap,
	245	ATMEL_TC_REG(tcbpwmc->channel, RA),
	246	tcbpwm->duty);
9421bade	247	else
061f8572 AB	248	regmap_write(tcbpwmc->regmap,
	249	ATMEL_TC_REG(tcbpwmc->channel, RB),
	250	tcbpwm->duty);
9421bade	251
061f8572 AB	252	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
061f8572 AB	253	tcbpwm->period);
9421bade BB	254
9421bade BB	255	/* Use software trigger to apply the new setting */
061f8572 AB	256	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
	257	ATMEL_TC_SWTRG \| ATMEL_TC_CLKEN);
	258	tcbpwmc->bkup.enabled = 1;
9421bade BB	259	spin_unlock(&tcbpwmc->lock);
	260	return 0;
	261	}
	262
	263	static int atmel_tcb_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	264	int duty_ns, int period_ns)
	265	{
	266	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
78dca23b	267	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
9421bade	268	struct atmel_tcb_pwm_device *atcbpwm = NULL;
34cbcd72	269	int i = 0;
9421bade BB	270	int slowclk = 0;
	271	unsigned period;
	272	unsigned duty;
061f8572	273	unsigned rate = clk_get_rate(tcbpwmc->clk);
9421bade BB	274	unsigned long long min;
	275	unsigned long long max;
	276
	277	/*
	278	* Find best clk divisor:
	279	* the smallest divisor which can fulfill the period_ns requirements.
f6bc65d3	280	* If there is a gclk, the first divisor is actually the gclk selector
9421bade	281	*/
34cbcd72 AB	282	if (tcbpwmc->gclk)
	283	i = 1;
	284	for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
061f8572	285	if (atmel_tcb_divisors[i] == 0) {
9421bade BB	286	slowclk = i;
	287	continue;
	288	}
061f8572 AB	289	min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
061f8572 AB	290	max = min << tcbpwmc->width;
9421bade BB	291	if (max >= period_ns)
	292	break;
	293	}
	294
	295	/*
	296	* If none of the divisor are small enough to represent period_ns
	297	* take slow clock (32KHz).
	298	*/
061f8572	299	if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
9421bade	300	i = slowclk;
061f8572	301	rate = clk_get_rate(tcbpwmc->slow_clk);
9421bade	302	min = div_u64(NSEC_PER_SEC, rate);
061f8572	303	max = min << tcbpwmc->width;
9421bade BB	304
	305	/* If period is too big return ERANGE error */
	306	if (max < period_ns)
	307	return -ERANGE;
	308	}
	309
	310	duty = div_u64(duty_ns, min);
	311	period = div_u64(period_ns, min);
	312
061f8572	313	if (pwm->hwpwm == 0)
78dca23b	314	atcbpwm = &tcbpwmc->pwms[1];
9421bade	315	else
78dca23b	316	atcbpwm = &tcbpwmc->pwms[0];
9421bade BB	317
9421bade BB	318	/*
061f8572	319	* PWM devices provided by the TCB driver are grouped by 2.
9421bade BB	320	* PWM devices in a given group must be configured with the
	321	* same period_ns.
	322	*
	323	* We're checking the period value of the second PWM device
	324	* in this group before applying the new config.
	325	*/
	326	if ((atcbpwm && atcbpwm->duty > 0 &&
	327	atcbpwm->duty != atcbpwm->period) &&
	328	(atcbpwm->div != i \|\| atcbpwm->period != period)) {
44fe6578	329	dev_err(pwmchip_parent(chip),
9421bade BB	330	"failed to configure period_ns: PWM group already configured with a different value\n");
	331	return -EINVAL;
	332	}
	333
	334	tcbpwm->period = period;
	335	tcbpwm->div = i;
	336	tcbpwm->duty = duty;
	337
9421bade BB	338	return 0;
	339	}
	340
30882cf1 UKK	341	static int atmel_tcb_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	342	const struct pwm_state *state)
	343	{
	344	int duty_cycle, period;
	345	int ret;
	346
30882cf1	347	if (!state->enabled) {
28a1dadc	348	atmel_tcb_pwm_disable(chip, pwm, state->polarity);
30882cf1 UKK	349	return 0;
	350	}
	351
	352	period = state->period < INT_MAX ? state->period : INT_MAX;
	353	duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;
	354
	355	ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
	356	if (ret)
	357	return ret;
	358
28a1dadc	359	return atmel_tcb_pwm_enable(chip, pwm, state->polarity);
30882cf1 UKK	360	}
30882cf1 UKK	361
9421bade BB	362	static const struct pwm_ops atmel_tcb_pwm_ops = {
	363	.request = atmel_tcb_pwm_request,
	364	.free = atmel_tcb_pwm_free,
30882cf1	365	.apply = atmel_tcb_pwm_apply,
9421bade BB	366	};
9421bade BB	367
061f8572 AB	368	static struct atmel_tcb_config tcb_rm9200_config = {
	369	.counter_width = 16,
	370	};
	371
	372	static struct atmel_tcb_config tcb_sam9x5_config = {
	373	.counter_width = 32,
	374	};
	375
34cbcd72 AB	376	static struct atmel_tcb_config tcb_sama5d2_config = {
	377	.counter_width = 32,
	378	.has_gclk = 1,
	379	};
	380
061f8572 AB	381	static const struct of_device_id atmel_tcb_of_match[] = {
	382	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
	383	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
34cbcd72	384	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
061f8572 AB	385	{ /* sentinel */ }
	386	};
	387
9421bade BB	388	static int atmel_tcb_pwm_probe(struct platform_device *pdev)
9421bade BB	389	{
dfab73eb	390	struct pwm_chip *chip;
061f8572	391	const struct of_device_id *match;
9421bade	392	struct atmel_tcb_pwm_chip *tcbpwm;
061f8572	393	const struct atmel_tcb_config *config;
9421bade	394	struct device_node *np = pdev->dev.of_node;
061f8572	395	char clk_name[] = "t0_clk";
9421bade	396	int err;
061f8572	397	int channel;
9421bade	398
af184748 UKK	399	chip = devm_pwmchip_alloc(&pdev->dev, NPWM, sizeof(*tcbpwm));
	400	if (IS_ERR(chip))
	401	return PTR_ERR(chip);
	402	tcbpwm = to_tcb_chip(chip);
0323e8fe	403
061f8572	404	err = of_property_read_u32(np, "reg", &channel);
9421bade BB	405	if (err < 0) {
9421bade BB	406	dev_err(&pdev->dev,
061f8572	407	"failed to get Timer Counter Block channel from device tree (error: %d)\n",
9421bade BB	408	err);
	409	return err;
	410	}
	411
0323e8fe UKK	412	tcbpwm->regmap = syscon_node_to_regmap(np->parent);
	413	if (IS_ERR(tcbpwm->regmap))
	414	return PTR_ERR(tcbpwm->regmap);
061f8572	415
0323e8fe UKK	416	tcbpwm->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
	417	if (IS_ERR(tcbpwm->slow_clk))
	418	return PTR_ERR(tcbpwm->slow_clk);
061f8572 AB	419
061f8572 AB	420	clk_name[1] += channel;
0323e8fe UKK	421	tcbpwm->clk = of_clk_get_by_name(np->parent, clk_name);
	422	if (IS_ERR(tcbpwm->clk))
	423	tcbpwm->clk = of_clk_get_by_name(np->parent, "t0_clk");
c1162232 UKK	424	if (IS_ERR(tcbpwm->clk)) {
	425	err = PTR_ERR(tcbpwm->clk);
	426	goto err_slow_clk;
	427	}
061f8572 AB	428
	429	match = of_match_node(atmel_tcb_of_match, np->parent);
	430	config = match->data;
9421bade	431
34cbcd72	432	if (config->has_gclk) {
0323e8fe	433	tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk");
c1162232 UKK	434	if (IS_ERR(tcbpwm->gclk)) {
	435	err = PTR_ERR(tcbpwm->gclk);
	436	goto err_clk;
	437	}
9421bade BB	438	}
9421bade BB	439
dfab73eb	440	chip->ops = &atmel_tcb_pwm_ops;
061f8572	441	tcbpwm->channel = channel;
061f8572	442	tcbpwm->width = config->counter_width;
9421bade	443
0323e8fe	444	err = clk_prepare_enable(tcbpwm->slow_clk);
7d8d05d1	445	if (err)
c1162232	446	goto err_gclk;
7d8d05d1	447
9421bade BB	448	spin_lock_init(&tcbpwm->lock);
9421bade BB	449
dfab73eb	450	err = pwmchip_add(chip);
7d8d05d1 BB	451	if (err < 0)
7d8d05d1 BB	452	goto err_disable_clk;
9421bade	453
dfab73eb	454	platform_set_drvdata(pdev, chip);
9421bade BB	455
9421bade BB	456	return 0;
7d8d05d1 BB	457
7d8d05d1 BB	458	err_disable_clk:
061f8572	459	clk_disable_unprepare(tcbpwm->slow_clk);
7d8d05d1	460
c1162232 UKK	461	err_gclk:
	462	clk_put(tcbpwm->gclk);
	463
	464	err_clk:
	465	clk_put(tcbpwm->clk);
	466
061f8572	467	err_slow_clk:
0323e8fe	468	clk_put(tcbpwm->slow_clk);
7d8d05d1 BB	469
7d8d05d1 BB	470	return err;
9421bade BB	471	}
9421bade BB	472
9609284a	473	static void atmel_tcb_pwm_remove(struct platform_device *pdev)
9421bade	474	{
dfab73eb UKK	475	struct pwm_chip *chip = platform_get_drvdata(pdev);
dfab73eb UKK	476	struct atmel_tcb_pwm_chip *tcbpwm = to_tcb_chip(chip);
9421bade	477
dfab73eb	478	pwmchip_remove(chip);
9421bade	479
c77e99f4	480	clk_disable_unprepare(tcbpwm->slow_clk);
c1162232	481	clk_put(tcbpwm->gclk);
c77e99f4	482	clk_put(tcbpwm->clk);
c1162232	483	clk_put(tcbpwm->slow_clk);
9421bade BB	484	}
	485
	486	static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
	487	{ .compatible = "atmel,tcb-pwm", },
	488	{ /* sentinel */ }
	489	};
	490	MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
	491
1b3d9a93 RI	492	static int atmel_tcb_pwm_suspend(struct device *dev)
1b3d9a93 RI	493	{
dfab73eb UKK	494	struct pwm_chip *chip = dev_get_drvdata(dev);
dfab73eb UKK	495	struct atmel_tcb_pwm_chip *tcbpwm = to_tcb_chip(chip);
061f8572 AB	496	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
061f8572 AB	497	unsigned int channel = tcbpwm->channel;
1b3d9a93	498
061f8572 AB	499	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
	500	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
	501	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
	502	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
1b3d9a93	503
1b3d9a93 RI	504	return 0;
	505	}
	506
	507	static int atmel_tcb_pwm_resume(struct device *dev)
	508	{
dfab73eb UKK	509	struct pwm_chip *chip = dev_get_drvdata(dev);
dfab73eb UKK	510	struct atmel_tcb_pwm_chip *tcbpwm = to_tcb_chip(chip);
061f8572 AB	511	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
061f8572 AB	512	unsigned int channel = tcbpwm->channel;
1b3d9a93	513
061f8572 AB	514	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
	515	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
	516	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
	517	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
	518
	519	if (chan->enabled)
	520	regmap_write(tcbpwm->regmap,
	521	ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG,
	522	ATMEL_TC_REG(channel, CCR));
1b3d9a93	523
1b3d9a93 RI	524	return 0;
1b3d9a93 RI	525	}
1b3d9a93	526
a7bab37f UKK	527	static DEFINE_SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
a7bab37f UKK	528	atmel_tcb_pwm_resume);
1b3d9a93	529
9421bade BB	530	static struct platform_driver atmel_tcb_pwm_driver = {
	531	.driver = {
	532	.name = "atmel-tcb-pwm",
	533	.of_match_table = atmel_tcb_pwm_dt_ids,
a7bab37f	534	.pm = pm_ptr(&atmel_tcb_pwm_pm_ops),
9421bade BB	535	},
9421bade BB	536	.probe = atmel_tcb_pwm_probe,
9609284a	537	.remove_new = atmel_tcb_pwm_remove,
9421bade BB	538	};
	539	module_platform_driver(atmel_tcb_pwm_driver);
	540
	541	MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
	542	MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
	543	MODULE_LICENSE("GPL v2");