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af873fce | 1 | // SPDX-License-Identifier: GPL-2.0-only |
9421bade BB |
2 | /* |
3 | * Copyright (C) Overkiz SAS 2012 | |
4 | * | |
5 | * Author: Boris BREZILLON <b.brezillon@overkiz.com> | |
9421bade BB |
6 | */ |
7 | ||
8 | #include <linux/module.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/clocksource.h> | |
11 | #include <linux/clockchips.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/irq.h> | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/io.h> | |
061f8572 | 19 | #include <linux/mfd/syscon.h> |
9421bade | 20 | #include <linux/platform_device.h> |
9421bade BB |
21 | #include <linux/pwm.h> |
22 | #include <linux/of_device.h> | |
061f8572 AB |
23 | #include <linux/of_irq.h> |
24 | #include <linux/regmap.h> | |
9421bade | 25 | #include <linux/slab.h> |
c2c9136b | 26 | #include <soc/at91/atmel_tcb.h> |
9421bade | 27 | |
061f8572 | 28 | #define NPWM 2 |
9421bade BB |
29 | |
30 | #define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \ | |
31 | ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG) | |
32 | ||
33 | #define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \ | |
34 | ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG) | |
35 | ||
36 | struct atmel_tcb_pwm_device { | |
37 | enum pwm_polarity polarity; /* PWM polarity */ | |
38 | unsigned div; /* PWM clock divider */ | |
39 | unsigned duty; /* PWM duty expressed in clk cycles */ | |
40 | unsigned period; /* PWM period expressed in clk cycles */ | |
41 | }; | |
42 | ||
1b3d9a93 RI |
43 | struct atmel_tcb_channel { |
44 | u32 enabled; | |
45 | u32 cmr; | |
46 | u32 ra; | |
47 | u32 rb; | |
48 | u32 rc; | |
49 | }; | |
50 | ||
9421bade BB |
51 | struct atmel_tcb_pwm_chip { |
52 | struct pwm_chip chip; | |
53 | spinlock_t lock; | |
061f8572 AB |
54 | u8 channel; |
55 | u8 width; | |
56 | struct regmap *regmap; | |
57 | struct clk *clk; | |
34cbcd72 | 58 | struct clk *gclk; |
061f8572 | 59 | struct clk *slow_clk; |
9421bade | 60 | struct atmel_tcb_pwm_device *pwms[NPWM]; |
061f8572 | 61 | struct atmel_tcb_channel bkup; |
9421bade BB |
62 | }; |
63 | ||
d7b44083 | 64 | static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, }; |
061f8572 | 65 | |
9421bade BB |
66 | static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip) |
67 | { | |
68 | return container_of(chip, struct atmel_tcb_pwm_chip, chip); | |
69 | } | |
70 | ||
71 | static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip, | |
72 | struct pwm_device *pwm, | |
73 | enum pwm_polarity polarity) | |
74 | { | |
fdaa6efc UKK |
75 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); |
76 | struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm]; | |
9421bade BB |
77 | |
78 | tcbpwm->polarity = polarity; | |
79 | ||
80 | return 0; | |
81 | } | |
82 | ||
83 | static int atmel_tcb_pwm_request(struct pwm_chip *chip, | |
84 | struct pwm_device *pwm) | |
85 | { | |
86 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); | |
87 | struct atmel_tcb_pwm_device *tcbpwm; | |
9421bade BB |
88 | unsigned cmr; |
89 | int ret; | |
90 | ||
91 | tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL); | |
92 | if (!tcbpwm) | |
93 | return -ENOMEM; | |
94 | ||
061f8572 | 95 | ret = clk_prepare_enable(tcbpwmc->clk); |
9421bade BB |
96 | if (ret) { |
97 | devm_kfree(chip->dev, tcbpwm); | |
98 | return ret; | |
99 | } | |
100 | ||
9421bade BB |
101 | tcbpwm->polarity = PWM_POLARITY_NORMAL; |
102 | tcbpwm->duty = 0; | |
103 | tcbpwm->period = 0; | |
104 | tcbpwm->div = 0; | |
105 | ||
106 | spin_lock(&tcbpwmc->lock); | |
061f8572 | 107 | regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr); |
9421bade BB |
108 | /* |
109 | * Get init config from Timer Counter registers if | |
110 | * Timer Counter is already configured as a PWM generator. | |
111 | */ | |
112 | if (cmr & ATMEL_TC_WAVE) { | |
061f8572 AB |
113 | if (pwm->hwpwm == 0) |
114 | regmap_read(tcbpwmc->regmap, | |
115 | ATMEL_TC_REG(tcbpwmc->channel, RA), | |
116 | &tcbpwm->duty); | |
9421bade | 117 | else |
061f8572 AB |
118 | regmap_read(tcbpwmc->regmap, |
119 | ATMEL_TC_REG(tcbpwmc->channel, RB), | |
120 | &tcbpwm->duty); | |
9421bade BB |
121 | |
122 | tcbpwm->div = cmr & ATMEL_TC_TCCLKS; | |
061f8572 AB |
123 | regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC), |
124 | &tcbpwm->period); | |
9421bade BB |
125 | cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK | |
126 | ATMEL_TC_BCMR_MASK); | |
127 | } else | |
128 | cmr = 0; | |
129 | ||
130 | cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0; | |
061f8572 | 131 | regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr); |
9421bade BB |
132 | spin_unlock(&tcbpwmc->lock); |
133 | ||
134 | tcbpwmc->pwms[pwm->hwpwm] = tcbpwm; | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
140 | { | |
141 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); | |
fdaa6efc | 142 | struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm]; |
9421bade | 143 | |
061f8572 | 144 | clk_disable_unprepare(tcbpwmc->clk); |
9421bade BB |
145 | tcbpwmc->pwms[pwm->hwpwm] = NULL; |
146 | devm_kfree(chip->dev, tcbpwm); | |
147 | } | |
148 | ||
149 | static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
150 | { | |
151 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); | |
fdaa6efc | 152 | struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm]; |
9421bade BB |
153 | unsigned cmr; |
154 | enum pwm_polarity polarity = tcbpwm->polarity; | |
155 | ||
156 | /* | |
157 | * If duty is 0 the timer will be stopped and we have to | |
158 | * configure the output correctly on software trigger: | |
159 | * - set output to high if PWM_POLARITY_INVERSED | |
160 | * - set output to low if PWM_POLARITY_NORMAL | |
161 | * | |
162 | * This is why we're reverting polarity in this case. | |
163 | */ | |
164 | if (tcbpwm->duty == 0) | |
165 | polarity = !polarity; | |
166 | ||
167 | spin_lock(&tcbpwmc->lock); | |
061f8572 | 168 | regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr); |
9421bade BB |
169 | |
170 | /* flush old setting and set the new one */ | |
061f8572 | 171 | if (pwm->hwpwm == 0) { |
9421bade BB |
172 | cmr &= ~ATMEL_TC_ACMR_MASK; |
173 | if (polarity == PWM_POLARITY_INVERSED) | |
174 | cmr |= ATMEL_TC_ASWTRG_CLEAR; | |
175 | else | |
176 | cmr |= ATMEL_TC_ASWTRG_SET; | |
177 | } else { | |
178 | cmr &= ~ATMEL_TC_BCMR_MASK; | |
179 | if (polarity == PWM_POLARITY_INVERSED) | |
180 | cmr |= ATMEL_TC_BSWTRG_CLEAR; | |
181 | else | |
182 | cmr |= ATMEL_TC_BSWTRG_SET; | |
183 | } | |
184 | ||
061f8572 | 185 | regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr); |
9421bade BB |
186 | |
187 | /* | |
188 | * Use software trigger to apply the new setting. | |
189 | * If both PWM devices in this group are disabled we stop the clock. | |
190 | */ | |
1b3d9a93 | 191 | if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) { |
061f8572 AB |
192 | regmap_write(tcbpwmc->regmap, |
193 | ATMEL_TC_REG(tcbpwmc->channel, CCR), | |
194 | ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS); | |
195 | tcbpwmc->bkup.enabled = 1; | |
1b3d9a93 | 196 | } else { |
061f8572 AB |
197 | regmap_write(tcbpwmc->regmap, |
198 | ATMEL_TC_REG(tcbpwmc->channel, CCR), | |
199 | ATMEL_TC_SWTRG); | |
200 | tcbpwmc->bkup.enabled = 0; | |
1b3d9a93 | 201 | } |
9421bade BB |
202 | |
203 | spin_unlock(&tcbpwmc->lock); | |
204 | } | |
205 | ||
206 | static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
207 | { | |
208 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); | |
fdaa6efc | 209 | struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm]; |
9421bade BB |
210 | u32 cmr; |
211 | enum pwm_polarity polarity = tcbpwm->polarity; | |
212 | ||
213 | /* | |
214 | * If duty is 0 the timer will be stopped and we have to | |
215 | * configure the output correctly on software trigger: | |
216 | * - set output to high if PWM_POLARITY_INVERSED | |
217 | * - set output to low if PWM_POLARITY_NORMAL | |
218 | * | |
219 | * This is why we're reverting polarity in this case. | |
220 | */ | |
221 | if (tcbpwm->duty == 0) | |
222 | polarity = !polarity; | |
223 | ||
224 | spin_lock(&tcbpwmc->lock); | |
061f8572 | 225 | regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr); |
9421bade BB |
226 | |
227 | /* flush old setting and set the new one */ | |
228 | cmr &= ~ATMEL_TC_TCCLKS; | |
229 | ||
061f8572 | 230 | if (pwm->hwpwm == 0) { |
9421bade BB |
231 | cmr &= ~ATMEL_TC_ACMR_MASK; |
232 | ||
233 | /* Set CMR flags according to given polarity */ | |
234 | if (polarity == PWM_POLARITY_INVERSED) | |
235 | cmr |= ATMEL_TC_ASWTRG_CLEAR; | |
236 | else | |
237 | cmr |= ATMEL_TC_ASWTRG_SET; | |
238 | } else { | |
239 | cmr &= ~ATMEL_TC_BCMR_MASK; | |
240 | if (polarity == PWM_POLARITY_INVERSED) | |
241 | cmr |= ATMEL_TC_BSWTRG_CLEAR; | |
242 | else | |
243 | cmr |= ATMEL_TC_BSWTRG_SET; | |
244 | } | |
245 | ||
246 | /* | |
247 | * If duty is 0 or equal to period there's no need to register | |
248 | * a specific action on RA/RB and RC compare. | |
249 | * The output will be configured on software trigger and keep | |
250 | * this config till next config call. | |
251 | */ | |
252 | if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) { | |
061f8572 | 253 | if (pwm->hwpwm == 0) { |
9421bade BB |
254 | if (polarity == PWM_POLARITY_INVERSED) |
255 | cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR; | |
256 | else | |
257 | cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET; | |
258 | } else { | |
259 | if (polarity == PWM_POLARITY_INVERSED) | |
260 | cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR; | |
261 | else | |
262 | cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET; | |
263 | } | |
264 | } | |
265 | ||
f3a82170 BB |
266 | cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS); |
267 | ||
061f8572 | 268 | regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr); |
9421bade | 269 | |
061f8572 AB |
270 | if (pwm->hwpwm == 0) |
271 | regmap_write(tcbpwmc->regmap, | |
272 | ATMEL_TC_REG(tcbpwmc->channel, RA), | |
273 | tcbpwm->duty); | |
9421bade | 274 | else |
061f8572 AB |
275 | regmap_write(tcbpwmc->regmap, |
276 | ATMEL_TC_REG(tcbpwmc->channel, RB), | |
277 | tcbpwm->duty); | |
9421bade | 278 | |
061f8572 AB |
279 | regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC), |
280 | tcbpwm->period); | |
9421bade BB |
281 | |
282 | /* Use software trigger to apply the new setting */ | |
061f8572 AB |
283 | regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR), |
284 | ATMEL_TC_SWTRG | ATMEL_TC_CLKEN); | |
285 | tcbpwmc->bkup.enabled = 1; | |
9421bade BB |
286 | spin_unlock(&tcbpwmc->lock); |
287 | return 0; | |
288 | } | |
289 | ||
290 | static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
291 | int duty_ns, int period_ns) | |
292 | { | |
293 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); | |
fdaa6efc | 294 | struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm]; |
9421bade | 295 | struct atmel_tcb_pwm_device *atcbpwm = NULL; |
34cbcd72 | 296 | int i = 0; |
9421bade BB |
297 | int slowclk = 0; |
298 | unsigned period; | |
299 | unsigned duty; | |
061f8572 | 300 | unsigned rate = clk_get_rate(tcbpwmc->clk); |
9421bade BB |
301 | unsigned long long min; |
302 | unsigned long long max; | |
303 | ||
304 | /* | |
305 | * Find best clk divisor: | |
306 | * the smallest divisor which can fulfill the period_ns requirements. | |
f6bc65d3 | 307 | * If there is a gclk, the first divisor is actually the gclk selector |
9421bade | 308 | */ |
34cbcd72 AB |
309 | if (tcbpwmc->gclk) |
310 | i = 1; | |
311 | for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) { | |
061f8572 | 312 | if (atmel_tcb_divisors[i] == 0) { |
9421bade BB |
313 | slowclk = i; |
314 | continue; | |
315 | } | |
061f8572 AB |
316 | min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate); |
317 | max = min << tcbpwmc->width; | |
9421bade BB |
318 | if (max >= period_ns) |
319 | break; | |
320 | } | |
321 | ||
322 | /* | |
323 | * If none of the divisor are small enough to represent period_ns | |
324 | * take slow clock (32KHz). | |
325 | */ | |
061f8572 | 326 | if (i == ARRAY_SIZE(atmel_tcb_divisors)) { |
9421bade | 327 | i = slowclk; |
061f8572 | 328 | rate = clk_get_rate(tcbpwmc->slow_clk); |
9421bade | 329 | min = div_u64(NSEC_PER_SEC, rate); |
061f8572 | 330 | max = min << tcbpwmc->width; |
9421bade BB |
331 | |
332 | /* If period is too big return ERANGE error */ | |
333 | if (max < period_ns) | |
334 | return -ERANGE; | |
335 | } | |
336 | ||
337 | duty = div_u64(duty_ns, min); | |
338 | period = div_u64(period_ns, min); | |
339 | ||
061f8572 AB |
340 | if (pwm->hwpwm == 0) |
341 | atcbpwm = tcbpwmc->pwms[1]; | |
9421bade | 342 | else |
061f8572 | 343 | atcbpwm = tcbpwmc->pwms[0]; |
9421bade BB |
344 | |
345 | /* | |
061f8572 | 346 | * PWM devices provided by the TCB driver are grouped by 2. |
9421bade BB |
347 | * PWM devices in a given group must be configured with the |
348 | * same period_ns. | |
349 | * | |
350 | * We're checking the period value of the second PWM device | |
351 | * in this group before applying the new config. | |
352 | */ | |
353 | if ((atcbpwm && atcbpwm->duty > 0 && | |
354 | atcbpwm->duty != atcbpwm->period) && | |
355 | (atcbpwm->div != i || atcbpwm->period != period)) { | |
356 | dev_err(chip->dev, | |
357 | "failed to configure period_ns: PWM group already configured with a different value\n"); | |
358 | return -EINVAL; | |
359 | } | |
360 | ||
361 | tcbpwm->period = period; | |
362 | tcbpwm->div = i; | |
363 | tcbpwm->duty = duty; | |
364 | ||
9421bade BB |
365 | return 0; |
366 | } | |
367 | ||
30882cf1 UKK |
368 | static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
369 | const struct pwm_state *state) | |
370 | { | |
371 | int duty_cycle, period; | |
372 | int ret; | |
373 | ||
374 | /* This function only sets a flag in driver data */ | |
375 | atmel_tcb_pwm_set_polarity(chip, pwm, state->polarity); | |
376 | ||
377 | if (!state->enabled) { | |
378 | atmel_tcb_pwm_disable(chip, pwm); | |
379 | return 0; | |
380 | } | |
381 | ||
382 | period = state->period < INT_MAX ? state->period : INT_MAX; | |
383 | duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX; | |
384 | ||
385 | ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period); | |
386 | if (ret) | |
387 | return ret; | |
388 | ||
389 | return atmel_tcb_pwm_enable(chip, pwm); | |
390 | } | |
391 | ||
9421bade BB |
392 | static const struct pwm_ops atmel_tcb_pwm_ops = { |
393 | .request = atmel_tcb_pwm_request, | |
394 | .free = atmel_tcb_pwm_free, | |
30882cf1 | 395 | .apply = atmel_tcb_pwm_apply, |
83c80dc5 | 396 | .owner = THIS_MODULE, |
9421bade BB |
397 | }; |
398 | ||
061f8572 AB |
399 | static struct atmel_tcb_config tcb_rm9200_config = { |
400 | .counter_width = 16, | |
401 | }; | |
402 | ||
403 | static struct atmel_tcb_config tcb_sam9x5_config = { | |
404 | .counter_width = 32, | |
405 | }; | |
406 | ||
34cbcd72 AB |
407 | static struct atmel_tcb_config tcb_sama5d2_config = { |
408 | .counter_width = 32, | |
409 | .has_gclk = 1, | |
410 | }; | |
411 | ||
061f8572 AB |
412 | static const struct of_device_id atmel_tcb_of_match[] = { |
413 | { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, }, | |
414 | { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, }, | |
34cbcd72 | 415 | { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, }, |
061f8572 AB |
416 | { /* sentinel */ } |
417 | }; | |
418 | ||
9421bade BB |
419 | static int atmel_tcb_pwm_probe(struct platform_device *pdev) |
420 | { | |
061f8572 | 421 | const struct of_device_id *match; |
9421bade | 422 | struct atmel_tcb_pwm_chip *tcbpwm; |
061f8572 | 423 | const struct atmel_tcb_config *config; |
9421bade | 424 | struct device_node *np = pdev->dev.of_node; |
061f8572 | 425 | struct regmap *regmap; |
34cbcd72 | 426 | struct clk *clk, *gclk = NULL; |
061f8572 AB |
427 | struct clk *slow_clk; |
428 | char clk_name[] = "t0_clk"; | |
9421bade | 429 | int err; |
061f8572 | 430 | int channel; |
9421bade | 431 | |
061f8572 | 432 | err = of_property_read_u32(np, "reg", &channel); |
9421bade BB |
433 | if (err < 0) { |
434 | dev_err(&pdev->dev, | |
061f8572 | 435 | "failed to get Timer Counter Block channel from device tree (error: %d)\n", |
9421bade BB |
436 | err); |
437 | return err; | |
438 | } | |
439 | ||
061f8572 AB |
440 | regmap = syscon_node_to_regmap(np->parent); |
441 | if (IS_ERR(regmap)) | |
442 | return PTR_ERR(regmap); | |
443 | ||
444 | slow_clk = of_clk_get_by_name(np->parent, "slow_clk"); | |
445 | if (IS_ERR(slow_clk)) | |
446 | return PTR_ERR(slow_clk); | |
447 | ||
448 | clk_name[1] += channel; | |
449 | clk = of_clk_get_by_name(np->parent, clk_name); | |
450 | if (IS_ERR(clk)) | |
451 | clk = of_clk_get_by_name(np->parent, "t0_clk"); | |
452 | if (IS_ERR(clk)) | |
453 | return PTR_ERR(clk); | |
454 | ||
455 | match = of_match_node(atmel_tcb_of_match, np->parent); | |
456 | config = match->data; | |
9421bade | 457 | |
34cbcd72 AB |
458 | if (config->has_gclk) { |
459 | gclk = of_clk_get_by_name(np->parent, "gclk"); | |
460 | if (IS_ERR(gclk)) | |
461 | return PTR_ERR(gclk); | |
462 | } | |
463 | ||
9421bade BB |
464 | tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL); |
465 | if (tcbpwm == NULL) { | |
7d8d05d1 | 466 | err = -ENOMEM; |
061f8572 | 467 | goto err_slow_clk; |
9421bade BB |
468 | } |
469 | ||
470 | tcbpwm->chip.dev = &pdev->dev; | |
471 | tcbpwm->chip.ops = &atmel_tcb_pwm_ops; | |
9421bade | 472 | tcbpwm->chip.npwm = NPWM; |
061f8572 AB |
473 | tcbpwm->channel = channel; |
474 | tcbpwm->regmap = regmap; | |
475 | tcbpwm->clk = clk; | |
34cbcd72 | 476 | tcbpwm->gclk = gclk; |
061f8572 AB |
477 | tcbpwm->slow_clk = slow_clk; |
478 | tcbpwm->width = config->counter_width; | |
9421bade | 479 | |
061f8572 | 480 | err = clk_prepare_enable(slow_clk); |
7d8d05d1 | 481 | if (err) |
061f8572 | 482 | goto err_slow_clk; |
7d8d05d1 | 483 | |
9421bade BB |
484 | spin_lock_init(&tcbpwm->lock); |
485 | ||
486 | err = pwmchip_add(&tcbpwm->chip); | |
7d8d05d1 BB |
487 | if (err < 0) |
488 | goto err_disable_clk; | |
9421bade BB |
489 | |
490 | platform_set_drvdata(pdev, tcbpwm); | |
491 | ||
492 | return 0; | |
7d8d05d1 BB |
493 | |
494 | err_disable_clk: | |
061f8572 | 495 | clk_disable_unprepare(tcbpwm->slow_clk); |
7d8d05d1 | 496 | |
061f8572 AB |
497 | err_slow_clk: |
498 | clk_put(slow_clk); | |
7d8d05d1 BB |
499 | |
500 | return err; | |
9421bade BB |
501 | } |
502 | ||
9609284a | 503 | static void atmel_tcb_pwm_remove(struct platform_device *pdev) |
9421bade BB |
504 | { |
505 | struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev); | |
9421bade | 506 | |
319333b0 | 507 | pwmchip_remove(&tcbpwm->chip); |
9421bade | 508 | |
c77e99f4 UKK |
509 | clk_disable_unprepare(tcbpwm->slow_clk); |
510 | clk_put(tcbpwm->slow_clk); | |
511 | clk_put(tcbpwm->clk); | |
9421bade BB |
512 | } |
513 | ||
514 | static const struct of_device_id atmel_tcb_pwm_dt_ids[] = { | |
515 | { .compatible = "atmel,tcb-pwm", }, | |
516 | { /* sentinel */ } | |
517 | }; | |
518 | MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids); | |
519 | ||
1b3d9a93 RI |
520 | #ifdef CONFIG_PM_SLEEP |
521 | static int atmel_tcb_pwm_suspend(struct device *dev) | |
522 | { | |
692099cd | 523 | struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev); |
061f8572 AB |
524 | struct atmel_tcb_channel *chan = &tcbpwm->bkup; |
525 | unsigned int channel = tcbpwm->channel; | |
1b3d9a93 | 526 | |
061f8572 AB |
527 | regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr); |
528 | regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra); | |
529 | regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb); | |
530 | regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc); | |
1b3d9a93 | 531 | |
1b3d9a93 RI |
532 | return 0; |
533 | } | |
534 | ||
535 | static int atmel_tcb_pwm_resume(struct device *dev) | |
536 | { | |
692099cd | 537 | struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev); |
061f8572 AB |
538 | struct atmel_tcb_channel *chan = &tcbpwm->bkup; |
539 | unsigned int channel = tcbpwm->channel; | |
1b3d9a93 | 540 | |
061f8572 AB |
541 | regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr); |
542 | regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra); | |
543 | regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb); | |
544 | regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc); | |
545 | ||
546 | if (chan->enabled) | |
547 | regmap_write(tcbpwm->regmap, | |
548 | ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, | |
549 | ATMEL_TC_REG(channel, CCR)); | |
1b3d9a93 | 550 | |
1b3d9a93 RI |
551 | return 0; |
552 | } | |
553 | #endif | |
554 | ||
555 | static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend, | |
556 | atmel_tcb_pwm_resume); | |
557 | ||
9421bade BB |
558 | static struct platform_driver atmel_tcb_pwm_driver = { |
559 | .driver = { | |
560 | .name = "atmel-tcb-pwm", | |
561 | .of_match_table = atmel_tcb_pwm_dt_ids, | |
1b3d9a93 | 562 | .pm = &atmel_tcb_pwm_pm_ops, |
9421bade BB |
563 | }, |
564 | .probe = atmel_tcb_pwm_probe, | |
9609284a | 565 | .remove_new = atmel_tcb_pwm_remove, |
9421bade BB |
566 | }; |
567 | module_platform_driver(atmel_tcb_pwm_driver); | |
568 | ||
569 | MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>"); | |
570 | MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver"); | |
571 | MODULE_LICENSE("GPL v2"); |