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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2b4984be BB |
2 | /* |
3 | * Copyright (C) 2014 Free Electrons | |
4 | * Copyright (C) 2014 Atmel | |
5 | * | |
6 | * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> | |
2b4984be BB |
7 | */ |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/mfd/atmel-hlcdc.h> | |
12 | #include <linux/module.h> | |
0a41b0c5 | 13 | #include <linux/of.h> |
2b4984be BB |
14 | #include <linux/platform_device.h> |
15 | #include <linux/pwm.h> | |
16 | #include <linux/regmap.h> | |
17 | ||
18 | #define ATMEL_HLCDC_PWMCVAL_MASK GENMASK(15, 8) | |
19 | #define ATMEL_HLCDC_PWMCVAL(x) (((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK) | |
20 | #define ATMEL_HLCDC_PWMPOL BIT(4) | |
21 | #define ATMEL_HLCDC_PWMPS_MASK GENMASK(2, 0) | |
22 | #define ATMEL_HLCDC_PWMPS_MAX 0x6 | |
23 | #define ATMEL_HLCDC_PWMPS(x) ((x) & ATMEL_HLCDC_PWMPS_MASK) | |
24 | ||
39e046f2 BB |
25 | struct atmel_hlcdc_pwm_errata { |
26 | bool slow_clk_erratum; | |
27 | bool div1_clk_erratum; | |
28 | }; | |
29 | ||
2b4984be | 30 | struct atmel_hlcdc_pwm { |
2b4984be BB |
31 | struct atmel_hlcdc *hlcdc; |
32 | struct clk *cur_clk; | |
39e046f2 | 33 | const struct atmel_hlcdc_pwm_errata *errata; |
2b4984be BB |
34 | }; |
35 | ||
36 | static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip) | |
37 | { | |
93dcf8e0 | 38 | return pwmchip_get_drvdata(chip); |
2b4984be BB |
39 | } |
40 | ||
aecab554 | 41 | static int atmel_hlcdc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
71523d18 | 42 | const struct pwm_state *state) |
2b4984be | 43 | { |
aecab554 UKK |
44 | struct atmel_hlcdc_pwm *atmel = to_atmel_hlcdc_pwm(chip); |
45 | struct atmel_hlcdc *hlcdc = atmel->hlcdc; | |
2267517c BB |
46 | unsigned int status; |
47 | int ret; | |
2b4984be | 48 | |
2267517c BB |
49 | if (state->enabled) { |
50 | struct clk *new_clk = hlcdc->slow_clk; | |
51 | u64 pwmcval = state->duty_cycle * 256; | |
52 | unsigned long clk_freq; | |
53 | u64 clk_period_ns; | |
54 | u32 pwmcfg; | |
55 | int pres; | |
56 | ||
aecab554 | 57 | if (!atmel->errata || !atmel->errata->slow_clk_erratum) { |
2267517c BB |
58 | clk_freq = clk_get_rate(new_clk); |
59 | if (!clk_freq) | |
60 | return -EINVAL; | |
61 | ||
62 | clk_period_ns = (u64)NSEC_PER_SEC * 256; | |
63 | do_div(clk_period_ns, clk_freq); | |
64 | } | |
65 | ||
66 | /* Errata: cannot use slow clk on some IP revisions */ | |
aecab554 | 67 | if ((atmel->errata && atmel->errata->slow_clk_erratum) || |
2267517c BB |
68 | clk_period_ns > state->period) { |
69 | new_clk = hlcdc->sys_clk; | |
70 | clk_freq = clk_get_rate(new_clk); | |
71 | if (!clk_freq) | |
72 | return -EINVAL; | |
73 | ||
74 | clk_period_ns = (u64)NSEC_PER_SEC * 256; | |
75 | do_div(clk_period_ns, clk_freq); | |
76 | } | |
77 | ||
78 | for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) { | |
39e046f2 | 79 | /* Errata: cannot divide by 1 on some IP revisions */ |
aecab554 UKK |
80 | if (!pres && atmel->errata && |
81 | atmel->errata->div1_clk_erratum) | |
2267517c | 82 | continue; |
2b4984be | 83 | |
2267517c BB |
84 | if ((clk_period_ns << pres) >= state->period) |
85 | break; | |
86 | } | |
2b4984be | 87 | |
2267517c BB |
88 | if (pres > ATMEL_HLCDC_PWMPS_MAX) |
89 | return -EINVAL; | |
2b4984be | 90 | |
2267517c | 91 | pwmcfg = ATMEL_HLCDC_PWMPS(pres); |
2b4984be | 92 | |
aecab554 | 93 | if (new_clk != atmel->cur_clk) { |
2267517c BB |
94 | u32 gencfg = 0; |
95 | int ret; | |
2b4984be | 96 | |
2267517c BB |
97 | ret = clk_prepare_enable(new_clk); |
98 | if (ret) | |
99 | return ret; | |
2b4984be | 100 | |
aecab554 UKK |
101 | clk_disable_unprepare(atmel->cur_clk); |
102 | atmel->cur_clk = new_clk; | |
2b4984be | 103 | |
2267517c BB |
104 | if (new_clk == hlcdc->sys_clk) |
105 | gencfg = ATMEL_HLCDC_CLKPWMSEL; | |
2b4984be | 106 | |
2267517c BB |
107 | ret = regmap_update_bits(hlcdc->regmap, |
108 | ATMEL_HLCDC_CFG(0), | |
109 | ATMEL_HLCDC_CLKPWMSEL, | |
110 | gencfg); | |
111 | if (ret) | |
112 | return ret; | |
113 | } | |
2b4984be | 114 | |
2267517c | 115 | do_div(pwmcval, state->period); |
2b4984be | 116 | |
2267517c BB |
117 | /* |
118 | * The PWM duty cycle is configurable from 0/256 to 255/256 of | |
119 | * the period cycle. Hence we can't set a duty cycle occupying | |
120 | * the whole period cycle if we're asked to. | |
121 | * Set it to 255 if pwmcval is greater than 256. | |
122 | */ | |
123 | if (pwmcval > 255) | |
124 | pwmcval = 255; | |
2b4984be | 125 | |
2267517c | 126 | pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval); |
2b4984be | 127 | |
2267517c BB |
128 | if (state->polarity == PWM_POLARITY_NORMAL) |
129 | pwmcfg |= ATMEL_HLCDC_PWMPOL; | |
2b4984be | 130 | |
2267517c BB |
131 | ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6), |
132 | ATMEL_HLCDC_PWMCVAL_MASK | | |
133 | ATMEL_HLCDC_PWMPS_MASK | | |
134 | ATMEL_HLCDC_PWMPOL, | |
135 | pwmcfg); | |
136 | if (ret) | |
137 | return ret; | |
2b4984be | 138 | |
2267517c BB |
139 | ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN, |
140 | ATMEL_HLCDC_PWM); | |
141 | if (ret) | |
142 | return ret; | |
2b4984be | 143 | |
2267517c BB |
144 | ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR, |
145 | status, | |
146 | status & ATMEL_HLCDC_PWM, | |
147 | 10, 0); | |
148 | if (ret) | |
149 | return ret; | |
150 | } else { | |
151 | ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS, | |
152 | ATMEL_HLCDC_PWM); | |
2b4984be BB |
153 | if (ret) |
154 | return ret; | |
155 | ||
2267517c BB |
156 | ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR, |
157 | status, | |
158 | !(status & ATMEL_HLCDC_PWM), | |
159 | 10, 0); | |
160 | if (ret) | |
161 | return ret; | |
2b4984be | 162 | |
aecab554 UKK |
163 | clk_disable_unprepare(atmel->cur_clk); |
164 | atmel->cur_clk = NULL; | |
2b4984be BB |
165 | } |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
2b4984be | 170 | static const struct pwm_ops atmel_hlcdc_pwm_ops = { |
2267517c | 171 | .apply = atmel_hlcdc_pwm_apply, |
2b4984be BB |
172 | }; |
173 | ||
39e046f2 BB |
174 | static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = { |
175 | .slow_clk_erratum = true, | |
176 | }; | |
177 | ||
178 | static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = { | |
179 | .div1_clk_erratum = true, | |
180 | }; | |
181 | ||
f9bb9da7 BB |
182 | static int atmel_hlcdc_pwm_suspend(struct device *dev) |
183 | { | |
0ba76822 UKK |
184 | struct pwm_chip *chip = dev_get_drvdata(dev); |
185 | struct atmel_hlcdc_pwm *atmel = to_atmel_hlcdc_pwm(chip); | |
186 | struct pwm_device *pwm = &chip->pwms[0]; | |
f9bb9da7 BB |
187 | |
188 | /* Keep the periph clock enabled if the PWM is still running. */ | |
c6c3f7e7 | 189 | if (!pwm->state.enabled) |
aecab554 | 190 | clk_disable_unprepare(atmel->hlcdc->periph_clk); |
f9bb9da7 BB |
191 | |
192 | return 0; | |
193 | } | |
194 | ||
195 | static int atmel_hlcdc_pwm_resume(struct device *dev) | |
196 | { | |
0ba76822 UKK |
197 | struct pwm_chip *chip = dev_get_drvdata(dev); |
198 | struct atmel_hlcdc_pwm *atmel = to_atmel_hlcdc_pwm(chip); | |
199 | struct pwm_device *pwm = &chip->pwms[0]; | |
f9bb9da7 BB |
200 | int ret; |
201 | ||
f9bb9da7 | 202 | /* Re-enable the periph clock it was stopped during suspend. */ |
c6c3f7e7 | 203 | if (!pwm->state.enabled) { |
aecab554 | 204 | ret = clk_prepare_enable(atmel->hlcdc->periph_clk); |
f9bb9da7 BB |
205 | if (ret) |
206 | return ret; | |
207 | } | |
208 | ||
0ba76822 | 209 | return atmel_hlcdc_pwm_apply(chip, pwm, &pwm->state); |
f9bb9da7 | 210 | } |
f9bb9da7 | 211 | |
ded38f87 UKK |
212 | static DEFINE_SIMPLE_DEV_PM_OPS(atmel_hlcdc_pwm_pm_ops, |
213 | atmel_hlcdc_pwm_suspend, atmel_hlcdc_pwm_resume); | |
f9bb9da7 | 214 | |
39e046f2 | 215 | static const struct of_device_id atmel_hlcdc_dt_ids[] = { |
7a593820 JW |
216 | { |
217 | .compatible = "atmel,at91sam9n12-hlcdc", | |
218 | /* 9n12 has same errata as 9x5 HLCDC PWM */ | |
219 | .data = &atmel_hlcdc_pwm_at91sam9x5_errata, | |
220 | }, | |
39e046f2 BB |
221 | { |
222 | .compatible = "atmel,at91sam9x5-hlcdc", | |
223 | .data = &atmel_hlcdc_pwm_at91sam9x5_errata, | |
224 | }, | |
2b8b0ef3 NF |
225 | { |
226 | .compatible = "atmel,sama5d2-hlcdc", | |
227 | }, | |
39e046f2 BB |
228 | { |
229 | .compatible = "atmel,sama5d3-hlcdc", | |
230 | .data = &atmel_hlcdc_pwm_sama5d3_errata, | |
231 | }, | |
054d3e1f NF |
232 | { |
233 | .compatible = "atmel,sama5d4-hlcdc", | |
234 | .data = &atmel_hlcdc_pwm_sama5d3_errata, | |
235 | }, | |
da9b3864 | 236 | { .compatible = "microchip,sam9x60-hlcdc", }, |
60cd67a4 | 237 | { /* sentinel */ } |
39e046f2 | 238 | }; |
a83a6a82 | 239 | MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids); |
39e046f2 | 240 | |
2b4984be BB |
241 | static int atmel_hlcdc_pwm_probe(struct platform_device *pdev) |
242 | { | |
39e046f2 | 243 | const struct of_device_id *match; |
2b4984be | 244 | struct device *dev = &pdev->dev; |
0ba76822 | 245 | struct pwm_chip *chip; |
aecab554 | 246 | struct atmel_hlcdc_pwm *atmel; |
2b4984be BB |
247 | struct atmel_hlcdc *hlcdc; |
248 | int ret; | |
249 | ||
250 | hlcdc = dev_get_drvdata(dev->parent); | |
251 | ||
93dcf8e0 UKK |
252 | chip = devm_pwmchip_alloc(dev, 1, sizeof(*atmel)); |
253 | if (IS_ERR(chip)) | |
254 | return PTR_ERR(chip); | |
255 | atmel = to_atmel_hlcdc_pwm(chip); | |
2b4984be BB |
256 | |
257 | ret = clk_prepare_enable(hlcdc->periph_clk); | |
258 | if (ret) | |
259 | return ret; | |
260 | ||
39e046f2 BB |
261 | match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node); |
262 | if (match) | |
aecab554 | 263 | atmel->errata = match->data; |
39e046f2 | 264 | |
aecab554 | 265 | atmel->hlcdc = hlcdc; |
0ba76822 | 266 | chip->ops = &atmel_hlcdc_pwm_ops; |
2b4984be | 267 | |
0ba76822 | 268 | ret = pwmchip_add(chip); |
2b4984be BB |
269 | if (ret) { |
270 | clk_disable_unprepare(hlcdc->periph_clk); | |
271 | return ret; | |
272 | } | |
273 | ||
0ba76822 | 274 | platform_set_drvdata(pdev, chip); |
2b4984be BB |
275 | |
276 | return 0; | |
277 | } | |
278 | ||
5fce9417 | 279 | static void atmel_hlcdc_pwm_remove(struct platform_device *pdev) |
2b4984be | 280 | { |
0ba76822 UKK |
281 | struct pwm_chip *chip = platform_get_drvdata(pdev); |
282 | struct atmel_hlcdc_pwm *atmel = to_atmel_hlcdc_pwm(chip); | |
2b4984be | 283 | |
0ba76822 | 284 | pwmchip_remove(chip); |
2b4984be | 285 | |
aecab554 | 286 | clk_disable_unprepare(atmel->hlcdc->periph_clk); |
2b4984be BB |
287 | } |
288 | ||
289 | static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = { | |
290 | { .compatible = "atmel,hlcdc-pwm" }, | |
60cd67a4 | 291 | { /* sentinel */ } |
2b4984be | 292 | }; |
433f1f79 | 293 | MODULE_DEVICE_TABLE(of, atmel_hlcdc_pwm_dt_ids); |
2b4984be BB |
294 | |
295 | static struct platform_driver atmel_hlcdc_pwm_driver = { | |
296 | .driver = { | |
297 | .name = "atmel-hlcdc-pwm", | |
298 | .of_match_table = atmel_hlcdc_pwm_dt_ids, | |
ded38f87 | 299 | .pm = pm_ptr(&atmel_hlcdc_pwm_pm_ops), |
2b4984be BB |
300 | }, |
301 | .probe = atmel_hlcdc_pwm_probe, | |
8db7fdff | 302 | .remove = atmel_hlcdc_pwm_remove, |
2b4984be BB |
303 | }; |
304 | module_platform_driver(atmel_hlcdc_pwm_driver); | |
305 | ||
306 | MODULE_ALIAS("platform:atmel-hlcdc-pwm"); | |
307 | MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>"); | |
308 | MODULE_DESCRIPTION("Atmel HLCDC PWM driver"); | |
309 | MODULE_LICENSE("GPL v2"); |