[linux-block.git] / drivers / pwm / pwm-atmel-hlcdc.c

/*
 * Copyright (C) 2014 Free Electrons
 * Copyright (C) 2014 Atmel
 *
 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/atmel-hlcdc.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/regmap.h>

#define ATMEL_HLCDC_PWMCVAL_MASK	GENMASK(15, 8)
#define ATMEL_HLCDC_PWMCVAL(x)		(((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
#define ATMEL_HLCDC_PWMPOL		BIT(4)
#define ATMEL_HLCDC_PWMPS_MASK		GENMASK(2, 0)
#define ATMEL_HLCDC_PWMPS_MAX		0x6
#define ATMEL_HLCDC_PWMPS(x)		((x) & ATMEL_HLCDC_PWMPS_MASK)

struct atmel_hlcdc_pwm_errata {
	bool slow_clk_erratum;
	bool div1_clk_erratum;
};

struct atmel_hlcdc_pwm {
	struct pwm_chip chip;
	struct atmel_hlcdc *hlcdc;
	struct clk *cur_clk;
	const struct atmel_hlcdc_pwm_errata *errata;
};

static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct atmel_hlcdc_pwm, chip);
}

static int atmel_hlcdc_pwm_apply(struct pwm_chip *c, struct pwm_device *pwm,
				 struct pwm_state *state)
{
	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
	struct atmel_hlcdc *hlcdc = chip->hlcdc;
	unsigned int status;
	int ret;

	if (state->enabled) {
		struct clk *new_clk = hlcdc->slow_clk;
		u64 pwmcval = state->duty_cycle * 256;
		unsigned long clk_freq;
		u64 clk_period_ns;
		u32 pwmcfg;
		int pres;

		if (!chip->errata || !chip->errata->slow_clk_erratum) {
			clk_freq = clk_get_rate(new_clk);
			if (!clk_freq)
				return -EINVAL;

			clk_period_ns = (u64)NSEC_PER_SEC * 256;
			do_div(clk_period_ns, clk_freq);
		}

		/* Errata: cannot use slow clk on some IP revisions */
		if ((chip->errata && chip->errata->slow_clk_erratum) ||
		    clk_period_ns > state->period) {
			new_clk = hlcdc->sys_clk;
			clk_freq = clk_get_rate(new_clk);
			if (!clk_freq)
				return -EINVAL;

			clk_period_ns = (u64)NSEC_PER_SEC * 256;
			do_div(clk_period_ns, clk_freq);
		}

		for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
		/* Errata: cannot divide by 1 on some IP revisions */
			if (!pres && chip->errata &&
			    chip->errata->div1_clk_erratum)
				continue;

			if ((clk_period_ns << pres) >= state->period)
				break;
		}

		if (pres > ATMEL_HLCDC_PWMPS_MAX)
			return -EINVAL;

		pwmcfg = ATMEL_HLCDC_PWMPS(pres);

		if (new_clk != chip->cur_clk) {
			u32 gencfg = 0;
			int ret;

			ret = clk_prepare_enable(new_clk);
			if (ret)
				return ret;

			clk_disable_unprepare(chip->cur_clk);
			chip->cur_clk = new_clk;

			if (new_clk == hlcdc->sys_clk)
				gencfg = ATMEL_HLCDC_CLKPWMSEL;

			ret = regmap_update_bits(hlcdc->regmap,
						 ATMEL_HLCDC_CFG(0),
						 ATMEL_HLCDC_CLKPWMSEL,
						 gencfg);
			if (ret)
				return ret;
		}

		do_div(pwmcval, state->period);

		/*
		 * The PWM duty cycle is configurable from 0/256 to 255/256 of
		 * the period cycle. Hence we can't set a duty cycle occupying
		 * the whole period cycle if we're asked to.
		 * Set it to 255 if pwmcval is greater than 256.
		 */
		if (pwmcval > 255)
			pwmcval = 255;

		pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);

		if (state->polarity == PWM_POLARITY_NORMAL)
			pwmcfg |= ATMEL_HLCDC_PWMPOL;

		ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
					 ATMEL_HLCDC_PWMCVAL_MASK |
					 ATMEL_HLCDC_PWMPS_MASK |
					 ATMEL_HLCDC_PWMPOL,
					 pwmcfg);
		if (ret)
			return ret;

		ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN,
				   ATMEL_HLCDC_PWM);
		if (ret)
			return ret;

		ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
					       status,
					       status & ATMEL_HLCDC_PWM,
					       10, 0);
		if (ret)
			return ret;
	} else {
		ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS,
				   ATMEL_HLCDC_PWM);
		if (ret)
			return ret;

		ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
					       status,
					       !(status & ATMEL_HLCDC_PWM),
					       10, 0);
		if (ret)
			return ret;

		clk_disable_unprepare(chip->cur_clk);
		chip->cur_clk = NULL;
	}

	return 0;
}

static const struct pwm_ops atmel_hlcdc_pwm_ops = {
	.apply = atmel_hlcdc_pwm_apply,
	.owner = THIS_MODULE,
};

static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
	.slow_clk_erratum = true,
};

static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
	.div1_clk_erratum = true,
};

static const struct of_device_id atmel_hlcdc_dt_ids[] = {
	{
		.compatible = "atmel,at91sam9n12-hlcdc",
		/* 9n12 has same errata as 9x5 HLCDC PWM */
		.data = &atmel_hlcdc_pwm_at91sam9x5_errata,
	},
	{
		.compatible = "atmel,at91sam9x5-hlcdc",
		.data = &atmel_hlcdc_pwm_at91sam9x5_errata,
	},
	{
		.compatible = "atmel,sama5d2-hlcdc",
	},
	{
		.compatible = "atmel,sama5d3-hlcdc",
		.data = &atmel_hlcdc_pwm_sama5d3_errata,
	},
	{
		.compatible = "atmel,sama5d4-hlcdc",
		.data = &atmel_hlcdc_pwm_sama5d3_errata,
	},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids);

static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct device *dev = &pdev->dev;
	struct atmel_hlcdc_pwm *chip;
	struct atmel_hlcdc *hlcdc;
	int ret;

	hlcdc = dev_get_drvdata(dev->parent);

	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	ret = clk_prepare_enable(hlcdc->periph_clk);
	if (ret)
		return ret;

	match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
	if (match)
		chip->errata = match->data;

	chip->hlcdc = hlcdc;
	chip->chip.ops = &atmel_hlcdc_pwm_ops;
	chip->chip.dev = dev;
	chip->chip.base = -1;
	chip->chip.npwm = 1;
	chip->chip.of_xlate = of_pwm_xlate_with_flags;
	chip->chip.of_pwm_n_cells = 3;

	ret = pwmchip_add_with_polarity(&chip->chip, PWM_POLARITY_INVERSED);
	if (ret) {
		clk_disable_unprepare(hlcdc->periph_clk);
		return ret;
	}

	platform_set_drvdata(pdev, chip);

	return 0;
}

static int atmel_hlcdc_pwm_remove(struct platform_device *pdev)
{
	struct atmel_hlcdc_pwm *chip = platform_get_drvdata(pdev);
	int ret;

	ret = pwmchip_remove(&chip->chip);
	if (ret)
		return ret;

	clk_disable_unprepare(chip->hlcdc->periph_clk);

	return 0;
}

static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
	{ .compatible = "atmel,hlcdc-pwm" },
	{ /* sentinel */ },
};

static struct platform_driver atmel_hlcdc_pwm_driver = {
	.driver = {
		.name = "atmel-hlcdc-pwm",
		.of_match_table = atmel_hlcdc_pwm_dt_ids,
	},
	.probe = atmel_hlcdc_pwm_probe,
	.remove = atmel_hlcdc_pwm_remove,
};
module_platform_driver(atmel_hlcdc_pwm_driver);

MODULE_ALIAS("platform:atmel-hlcdc-pwm");
MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2b4984be BB	1	/*
	2	* Copyright (C) 2014 Free Electrons
	3	* Copyright (C) 2014 Atmel
	4	*
	5	* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/clk.h>
	21	#include <linux/delay.h>
	22	#include <linux/mfd/atmel-hlcdc.h>
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/pwm.h>
	26	#include <linux/regmap.h>
	27
	28	#define ATMEL_HLCDC_PWMCVAL_MASK GENMASK(15, 8)
	29	#define ATMEL_HLCDC_PWMCVAL(x) (((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
	30	#define ATMEL_HLCDC_PWMPOL BIT(4)
	31	#define ATMEL_HLCDC_PWMPS_MASK GENMASK(2, 0)
	32	#define ATMEL_HLCDC_PWMPS_MAX 0x6
	33	#define ATMEL_HLCDC_PWMPS(x) ((x) & ATMEL_HLCDC_PWMPS_MASK)
	34
39e046f2 BB	35	struct atmel_hlcdc_pwm_errata {
	36	bool slow_clk_erratum;
	37	bool div1_clk_erratum;
	38	};
	39
2b4984be BB	40	struct atmel_hlcdc_pwm {
	41	struct pwm_chip chip;
	42	struct atmel_hlcdc *hlcdc;
	43	struct clk *cur_clk;
39e046f2	44	const struct atmel_hlcdc_pwm_errata *errata;
2b4984be BB	45	};
	46
	47	static inline struct atmel_hlcdc_pwm to_atmel_hlcdc_pwm(struct pwm_chip chip)
	48	{
	49	return container_of(chip, struct atmel_hlcdc_pwm, chip);
	50	}
	51
2267517c BB	52	static int atmel_hlcdc_pwm_apply(struct pwm_chip c, struct pwm_device pwm,
2267517c BB	53	struct pwm_state *state)
2b4984be BB	54	{
	55	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
	56	struct atmel_hlcdc *hlcdc = chip->hlcdc;
2267517c BB	57	unsigned int status;
2267517c BB	58	int ret;
2b4984be	59
2267517c BB	60	if (state->enabled) {
	61	struct clk *new_clk = hlcdc->slow_clk;
	62	u64 pwmcval = state->duty_cycle * 256;
	63	unsigned long clk_freq;
	64	u64 clk_period_ns;
	65	u32 pwmcfg;
	66	int pres;
	67
	68	if (!chip->errata \|\| !chip->errata->slow_clk_erratum) {
	69	clk_freq = clk_get_rate(new_clk);
	70	if (!clk_freq)
	71	return -EINVAL;
	72
	73	clk_period_ns = (u64)NSEC_PER_SEC * 256;
	74	do_div(clk_period_ns, clk_freq);
	75	}
	76
	77	/* Errata: cannot use slow clk on some IP revisions */
	78	if ((chip->errata && chip->errata->slow_clk_erratum) \|\|
	79	clk_period_ns > state->period) {
	80	new_clk = hlcdc->sys_clk;
	81	clk_freq = clk_get_rate(new_clk);
	82	if (!clk_freq)
	83	return -EINVAL;
	84
	85	clk_period_ns = (u64)NSEC_PER_SEC * 256;
	86	do_div(clk_period_ns, clk_freq);
	87	}
	88
	89	for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
39e046f2	90	/* Errata: cannot divide by 1 on some IP revisions */
2267517c BB	91	if (!pres && chip->errata &&
	92	chip->errata->div1_clk_erratum)
	93	continue;
2b4984be	94
2267517c BB	95	if ((clk_period_ns << pres) >= state->period)
	96	break;
	97	}
2b4984be	98
2267517c BB	99	if (pres > ATMEL_HLCDC_PWMPS_MAX)
2267517c BB	100	return -EINVAL;
2b4984be	101
2267517c	102	pwmcfg = ATMEL_HLCDC_PWMPS(pres);
2b4984be	103
2267517c BB	104	if (new_clk != chip->cur_clk) {
	105	u32 gencfg = 0;
	106	int ret;
2b4984be	107
2267517c BB	108	ret = clk_prepare_enable(new_clk);
	109	if (ret)
	110	return ret;
2b4984be	111
2267517c BB	112	clk_disable_unprepare(chip->cur_clk);
2267517c BB	113	chip->cur_clk = new_clk;
2b4984be	114
2267517c BB	115	if (new_clk == hlcdc->sys_clk)
2267517c BB	116	gencfg = ATMEL_HLCDC_CLKPWMSEL;
2b4984be	117
2267517c BB	118	ret = regmap_update_bits(hlcdc->regmap,
	119	ATMEL_HLCDC_CFG(0),
	120	ATMEL_HLCDC_CLKPWMSEL,
	121	gencfg);
	122	if (ret)
	123	return ret;
	124	}
2b4984be	125
2267517c	126	do_div(pwmcval, state->period);
2b4984be	127
2267517c BB	128	/*
	129	* The PWM duty cycle is configurable from 0/256 to 255/256 of
	130	* the period cycle. Hence we can't set a duty cycle occupying
	131	* the whole period cycle if we're asked to.
	132	* Set it to 255 if pwmcval is greater than 256.
	133	*/
	134	if (pwmcval > 255)
	135	pwmcval = 255;
2b4984be	136
2267517c	137	pwmcfg \|= ATMEL_HLCDC_PWMCVAL(pwmcval);
2b4984be	138
2267517c BB	139	if (state->polarity == PWM_POLARITY_NORMAL)
2267517c BB	140	pwmcfg \|= ATMEL_HLCDC_PWMPOL;
2b4984be	141
2267517c BB	142	ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
	143	ATMEL_HLCDC_PWMCVAL_MASK \|
	144	ATMEL_HLCDC_PWMPS_MASK \|
	145	ATMEL_HLCDC_PWMPOL,
	146	pwmcfg);
	147	if (ret)
	148	return ret;
2b4984be	149
2267517c BB	150	ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN,
	151	ATMEL_HLCDC_PWM);
	152	if (ret)
	153	return ret;
2b4984be	154
2267517c BB	155	ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
	156	status,
	157	status & ATMEL_HLCDC_PWM,
	158	10, 0);
	159	if (ret)
	160	return ret;
	161	} else {
	162	ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS,
	163	ATMEL_HLCDC_PWM);
2b4984be BB	164	if (ret)
	165	return ret;
	166
2267517c BB	167	ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
	168	status,
	169	!(status & ATMEL_HLCDC_PWM),
	170	10, 0);
	171	if (ret)
	172	return ret;
2b4984be	173
2267517c BB	174	clk_disable_unprepare(chip->cur_clk);
2267517c BB	175	chip->cur_clk = NULL;
2b4984be BB	176	}
	177
	178	return 0;
	179	}
	180
2b4984be	181	static const struct pwm_ops atmel_hlcdc_pwm_ops = {
2267517c	182	.apply = atmel_hlcdc_pwm_apply,
2b4984be BB	183	.owner = THIS_MODULE,
	184	};
	185
39e046f2 BB	186	static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
	187	.slow_clk_erratum = true,
	188	};
	189
	190	static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
	191	.div1_clk_erratum = true,
	192	};
	193
	194	static const struct of_device_id atmel_hlcdc_dt_ids[] = {
7a593820 JW	195	{
	196	.compatible = "atmel,at91sam9n12-hlcdc",
	197	/* 9n12 has same errata as 9x5 HLCDC PWM */
	198	.data = &atmel_hlcdc_pwm_at91sam9x5_errata,
	199	},
39e046f2 BB	200	{
	201	.compatible = "atmel,at91sam9x5-hlcdc",
	202	.data = &atmel_hlcdc_pwm_at91sam9x5_errata,
	203	},
2b8b0ef3 NF	204	{
	205	.compatible = "atmel,sama5d2-hlcdc",
	206	},
39e046f2 BB	207	{
	208	.compatible = "atmel,sama5d3-hlcdc",
	209	.data = &atmel_hlcdc_pwm_sama5d3_errata,
	210	},
054d3e1f NF	211	{
	212	.compatible = "atmel,sama5d4-hlcdc",
	213	.data = &atmel_hlcdc_pwm_sama5d3_errata,
	214	},
39e046f2 BB	215	{ /* sentinel */ },
39e046f2 BB	216	};
a83a6a82	217	MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids);
39e046f2	218
2b4984be BB	219	static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
2b4984be BB	220	{
39e046f2	221	const struct of_device_id *match;
2b4984be BB	222	struct device *dev = &pdev->dev;
	223	struct atmel_hlcdc_pwm *chip;
	224	struct atmel_hlcdc *hlcdc;
	225	int ret;
	226
	227	hlcdc = dev_get_drvdata(dev->parent);
	228
	229	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	230	if (!chip)
	231	return -ENOMEM;
	232
	233	ret = clk_prepare_enable(hlcdc->periph_clk);
	234	if (ret)
	235	return ret;
	236
39e046f2 BB	237	match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
	238	if (match)
	239	chip->errata = match->data;
	240
2b4984be BB	241	chip->hlcdc = hlcdc;
	242	chip->chip.ops = &atmel_hlcdc_pwm_ops;
	243	chip->chip.dev = dev;
	244	chip->chip.base = -1;
	245	chip->chip.npwm = 1;
	246	chip->chip.of_xlate = of_pwm_xlate_with_flags;
	247	chip->chip.of_pwm_n_cells = 3;
2b4984be	248
cc51846b	249	ret = pwmchip_add_with_polarity(&chip->chip, PWM_POLARITY_INVERSED);
2b4984be BB	250	if (ret) {
	251	clk_disable_unprepare(hlcdc->periph_clk);
	252	return ret;
	253	}
	254
	255	platform_set_drvdata(pdev, chip);
	256
	257	return 0;
	258	}
	259
	260	static int atmel_hlcdc_pwm_remove(struct platform_device *pdev)
	261	{
	262	struct atmel_hlcdc_pwm *chip = platform_get_drvdata(pdev);
	263	int ret;
	264
	265	ret = pwmchip_remove(&chip->chip);
	266	if (ret)
	267	return ret;
	268
	269	clk_disable_unprepare(chip->hlcdc->periph_clk);
	270
	271	return 0;
	272	}
	273
	274	static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
	275	{ .compatible = "atmel,hlcdc-pwm" },
	276	{ /* sentinel */ },
	277	};
	278
	279	static struct platform_driver atmel_hlcdc_pwm_driver = {
	280	.driver = {
	281	.name = "atmel-hlcdc-pwm",
	282	.of_match_table = atmel_hlcdc_pwm_dt_ids,
	283	},
	284	.probe = atmel_hlcdc_pwm_probe,
	285	.remove = atmel_hlcdc_pwm_remove,
	286	};
	287	module_platform_driver(atmel_hlcdc_pwm_driver);
	288
	289	MODULE_ALIAS("platform:atmel-hlcdc-pwm");
	290	MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
	291	MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
	292	MODULE_LICENSE("GPL v2");